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mcs48.c: Modernized cpu core (nw)

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This commit is contained in:
Wilbert Pol 2013-08-23 19:14:49 +00:00
parent 871ec5a881
commit ec1b639847
12 changed files with 1275 additions and 987 deletions
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1625
src/emu/cpu/mcs48/mcs48.c
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File diff suppressed because it is too large Load Diff

560
src/emu/cpu/mcs48/mcs48.h
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@ -94,44 +94,548 @@ enum
attotime::from_hz(_clock/(3*5)) attotime::from_hz(_clock/(3*5))
/* Official Intel MCS-48 parts */ /* Official Intel MCS-48 parts */
DECLARE_LEGACY_CPU_DEVICE(I8021, i8021); /* 1k internal ROM, 64 bytes internal RAM */ extern const device_type I8021; /* 1k internal ROM, 64 bytes internal RAM */
DECLARE_LEGACY_CPU_DEVICE(I8022, i8022); /* 2k internal ROM, 128 bytes internal RAM */ extern const device_type I8022; /* 2k internal ROM, 128 bytes internal RAM */
DECLARE_LEGACY_CPU_DEVICE(I8035, i8035); /* external ROM, 64 bytes internal RAM */ extern const device_type I8035; /* external ROM, 64 bytes internal RAM */
DECLARE_LEGACY_CPU_DEVICE(I8048, i8048); /* 1k internal ROM, 64 bytes internal RAM */ extern const device_type I8048; /* 1k internal ROM, 64 bytes internal RAM */
DECLARE_LEGACY_CPU_DEVICE(I8648, i8648); /* 1k internal OTP ROM, 64 bytes internal RAM */ extern const device_type I8648; /* 1k internal OTP ROM, 64 bytes internal RAM */
DECLARE_LEGACY_CPU_DEVICE(I8748, i8748); /* 1k internal EEPROM, 64 bytes internal RAM */ extern const device_type I8748; /* 1k internal EEPROM, 64 bytes internal RAM */
DECLARE_LEGACY_CPU_DEVICE(I8039, i8039); /* external ROM, 128 bytes internal RAM */ extern const device_type I8039; /* external ROM, 128 bytes internal RAM */
DECLARE_LEGACY_CPU_DEVICE(I8049, i8049); /* 2k internal ROM, 128 bytes internal RAM */ extern const device_type I8049; /* 2k internal ROM, 128 bytes internal RAM */
DECLARE_LEGACY_CPU_DEVICE(I8749, i8749); /* 2k internal EEPROM, 128 bytes internal RAM */ extern const device_type I8749; /* 2k internal EEPROM, 128 bytes internal RAM */
DECLARE_LEGACY_CPU_DEVICE(I8040, i8040); /* external ROM, 256 bytes internal RAM */ extern const device_type I8040; /* external ROM, 256 bytes internal RAM */
DECLARE_LEGACY_CPU_DEVICE(I8050, i8050); /* 4k internal ROM, 256 bytes internal RAM */ extern const device_type I8050; /* 4k internal ROM, 256 bytes internal RAM */
/* Official Intel UPI-41 parts */ /* Official Intel UPI-41 parts */
DECLARE_LEGACY_CPU_DEVICE(I8041, i8041); /* 1k internal ROM, 128 bytes internal RAM */ extern const device_type I8041; /* 1k internal ROM, 128 bytes internal RAM */
DECLARE_LEGACY_CPU_DEVICE(I8741, i8741); /* 1k internal EEPROM, 128 bytes internal RAM */ extern const device_type I8741; /* 1k internal EEPROM, 128 bytes internal RAM */
DECLARE_LEGACY_CPU_DEVICE(I8042, i8042); /* 2k internal ROM, 256 bytes internal RAM */ extern const device_type I8042; /* 2k internal ROM, 256 bytes internal RAM */
DECLARE_LEGACY_CPU_DEVICE(I8242, i8242); /* 2k internal ROM, 256 bytes internal RAM */ extern const device_type I8242; /* 2k internal ROM, 256 bytes internal RAM */
DECLARE_LEGACY_CPU_DEVICE(I8742, i8742); /* 2k internal EEPROM, 256 bytes internal RAM */ extern const device_type I8742; /* 2k internal EEPROM, 256 bytes internal RAM */
/* Clones */ /* Clones */
DECLARE_LEGACY_CPU_DEVICE(MB8884, mb8884); /* 8035 clone */ extern const device_type MB8884; /* 8035 clone */
DECLARE_LEGACY_CPU_DEVICE(N7751, n7751); /* 8048 clone */ extern const device_type N7751; /* 8048 clone */
DECLARE_LEGACY_CPU_DEVICE(M58715, m58715); /* 8049 clone */ extern const device_type M58715; /* 8049 clone */
/*************************************************************************** class mcs48_cpu_device : public cpu_device
FUNCTION PROTOTYPES {
***************************************************************************/ public:
// construction/destruction
mcs48_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int rom_size, int ram_size, UINT8 feature_mask = 0);
/* functions for talking to the input/output buffers on the UPI41-class chips */ protected:
UINT8 upi41_master_r(device_t *device, UINT8 a0); // device-level overrides
void upi41_master_w(device_t *device, UINT8 a0, UINT8 data); virtual void device_start();
virtual void device_reset();
// device_execute_interface overrides
virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 15 - 1) / 15; }
virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 15); }
virtual UINT32 execute_min_cycles() const { return 1; }
virtual UINT32 execute_max_cycles() const { return 3; }
virtual UINT32 execute_input_lines() const { return 2; }
virtual UINT32 execute_default_irq_vector() const { return MCS48_INPUT_IRQ; }
virtual void execute_run();
virtual void execute_set_input(int inputnum, int state);
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
{
return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ) );
}
// device_state_interface overrides
virtual void state_import(const device_state_entry &entry);
virtual void state_export(const device_state_entry &entry);
void state_string_export(const device_state_entry &entry, astring &string);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
virtual UINT32 disasm_max_opcode_bytes() const { return 2; }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
protected:
address_space_config m_program_config;
address_space_config m_data_config;
address_space_config m_io_config;
UINT16 m_prevpc; /* 16-bit previous program counter */
UINT16 m_pc; /* 16-bit program counter */
UINT8 m_a; /* 8-bit accumulator */
UINT8 * m_regptr; /* pointer to r0-r7 */
UINT8 m_psw; /* 8-bit psw */
UINT8 m_p1; /* 8-bit latched port 1 */
UINT8 m_p2; /* 8-bit latched port 2 */
UINT8 m_ea; /* 1-bit latched ea input */
UINT8 m_timer; /* 8-bit timer */
UINT8 m_prescaler; /* 5-bit timer prescaler */
UINT8 m_t1_history; /* 8-bit history of the T1 input */
UINT8 m_sts; /* 8-bit status register (UPI-41 only, except for F1) */
UINT8 m_dbbi; /* 8-bit input data buffer (UPI-41 only) */
UINT8 m_dbbo; /* 8-bit output data buffer (UPI-41 only) */
UINT8 m_irq_state; /* TRUE if an IRQ is pending */
UINT8 m_irq_in_progress; /* TRUE if an IRQ is in progress */
UINT8 m_timer_overflow; /* TRUE on a timer overflow; cleared by taking interrupt */
UINT8 m_timer_flag; /* TRUE on a timer overflow; cleared on JTF */
UINT8 m_tirq_enabled; /* TRUE if the timer IRQ is enabled */
UINT8 m_xirq_enabled; /* TRUE if the external IRQ is enabled */
UINT8 m_timecount_enabled; /* bitmask of timer/counter enabled */
UINT8 m_flags_enabled; /* TRUE if I/O flags have been enabled (UPI-41 only) */
UINT8 m_dma_enabled; /* TRUE if DMA has been enabled (UPI-41 only) */
UINT16 m_a11; /* A11 value, either 0x000 or 0x800 */
int m_icount;
/* Memory spaces */
address_space *m_program;
direct_read_data *m_direct;
address_space *m_data;
address_space *m_io;
UINT8 m_feature_mask; /* processor feature flags */
UINT16 m_int_rom_size; /* internal rom size */
UINT8 m_rtemp; /* temporary for import/export */
typedef int (mcs48_cpu_device::*mcs48_ophandler)();
static const mcs48_ophandler s_opcode_table[256];
UINT8 opcode_fetch();
UINT8 argument_fetch();
void update_regptr();
void push_pc_psw();
void pull_pc_psw();
void pull_pc();
void execute_add(UINT8 dat);
void execute_addc(UINT8 dat);
void execute_jmp(UINT16 address);
void execute_call(UINT16 address);
void execute_jcc(UINT8 result);
UINT8 p2_mask();
void expander_operation(UINT8 operation, UINT8 port);
int check_irqs();
void burn_cycles(int count);
int illegal();
int add_a_r0();
int add_a_r1();
int add_a_r2();
int add_a_r3();
int add_a_r4();
int add_a_r5();
int add_a_r6();
int add_a_r7();
int add_a_xr0();
int add_a_xr1();
int add_a_n();
int adc_a_r0();
int adc_a_r1();
int adc_a_r2();
int adc_a_r3();
int adc_a_r4();
int adc_a_r5();
int adc_a_r6();
int adc_a_r7();
int adc_a_xr0();
int adc_a_xr1();
int adc_a_n();
int anl_a_r0();
int anl_a_r1();
int anl_a_r2();
int anl_a_r3();
int anl_a_r4();
int anl_a_r5();
int anl_a_r6();
int anl_a_r7();
int anl_a_xr0();
int anl_a_xr1();
int anl_a_n();
int anl_bus_n();
int anl_p1_n();
int anl_p2_n();
int anld_p4_a();
int anld_p5_a();
int anld_p6_a();
int anld_p7_a();
int call_0();
int call_1();
int call_2();
int call_3();
int call_4();
int call_5();
int call_6();
int call_7();
int clr_a();
int clr_c();
int clr_f0();
int clr_f1();
int cpl_a();
int cpl_c();
int cpl_f0();
int cpl_f1();
int da_a();
int dec_a();
int dec_r0();
int dec_r1();
int dec_r2();
int dec_r3();
int dec_r4();
int dec_r5();
int dec_r6();
int dec_r7();
int dis_i();
int dis_tcnti();
int djnz_r0();
int djnz_r1();
int djnz_r2();
int djnz_r3();
int djnz_r4();
int djnz_r5();
int djnz_r6();
int djnz_r7();
int en_i();
int en_tcnti();
int en_dma();
int en_flags();
int ent0_clk();
int in_a_p1();
int in_a_p2();
int ins_a_bus();
int in_a_dbb();
int inc_a();
int inc_r0();
int inc_r1();
int inc_r2();
int inc_r3();
int inc_r4();
int inc_r5();
int inc_r6();
int inc_r7();
int inc_xr0();
int inc_xr1();
int jb_0();
int jb_1();
int jb_2();
int jb_3();
int jb_4();
int jb_5();
int jb_6();
int jb_7();
int jc();
int jf0();
int jf1();
int jnc();
int jni();
int jnibf();
int jnt_0();
int jnt_1();
int jnz();
int jobf();
int jtf();
int jt_0();
int jt_1();
int jz();
int jmp_0();
int jmp_1();
int jmp_2();
int jmp_3();
int jmp_4();
int jmp_5();
int jmp_6();
int jmp_7();
int jmpp_xa();
int mov_a_n();
int mov_a_psw();
int mov_a_r0();
int mov_a_r1();
int mov_a_r2();
int mov_a_r3();
int mov_a_r4();
int mov_a_r5();
int mov_a_r6();
int mov_a_r7();
int mov_a_xr0();
int mov_a_xr1();
int mov_a_t();
int mov_psw_a();
int mov_sts_a();
int mov_r0_a();
int mov_r1_a();
int mov_r2_a();
int mov_r3_a();
int mov_r4_a();
int mov_r5_a();
int mov_r6_a();
int mov_r7_a();
int mov_r0_n();
int mov_r1_n();
int mov_r2_n();
int mov_r3_n();
int mov_r4_n();
int mov_r5_n();
int mov_r6_n();
int mov_r7_n();
int mov_t_a();
int mov_xr0_a();
int mov_xr1_a();
int mov_xr0_n();
int mov_xr1_n();
int movd_a_p4();
int movd_a_p5();
int movd_a_p6();
int movd_a_p7();
int movd_p4_a();
int movd_p5_a();
int movd_p6_a();
int movd_p7_a();
int movp_a_xa();
int movp3_a_xa();
int movx_a_xr0();
int movx_a_xr1();
int movx_xr0_a();
int movx_xr1_a();
int nop();
int orl_a_r0();
int orl_a_r1();
int orl_a_r2();
int orl_a_r3();
int orl_a_r4();
int orl_a_r5();
int orl_a_r6();
int orl_a_r7();
int orl_a_xr0();
int orl_a_xr1();
int orl_a_n();
int orl_bus_n();
int orl_p1_n();
int orl_p2_n();
int orld_p4_a();
int orld_p5_a();
int orld_p6_a();
int orld_p7_a();
int outl_bus_a();
int outl_p1_a();
int outl_p2_a();
int out_dbb_a();
int ret();
int retr();
int rl_a();
int rlc_a();
int rr_a();
int rrc_a();
int sel_mb0();
int sel_mb1();
int sel_rb0();
int sel_rb1();
int stop_tcnt();
int strt_cnt();
int strt_t();
int swap_a();
int xch_a_r0();
int xch_a_r1();
int xch_a_r2();
int xch_a_r3();
int xch_a_r4();
int xch_a_r5();
int xch_a_r6();
int xch_a_r7();
int xch_a_xr0();
int xch_a_xr1();
int xchd_a_xr0();
int xchd_a_xr1();
int xrl_a_r0();
int xrl_a_r1();
int xrl_a_r2();
int xrl_a_r3();
int xrl_a_r4();
int xrl_a_r5();
int xrl_a_r6();
int xrl_a_r7();
int xrl_a_xr0();
int xrl_a_xr1();
int xrl_a_n();
int split_02();
int split_08();
int split_22();
int split_75();
int split_80();
int split_81();
int split_86();
int split_88();
int split_90();
int split_91();
int split_98();
int split_d6();
int split_e5();
int split_f5();
};
class i8021_device : public mcs48_cpu_device
{
public:
// construction/destruction
i8021_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
protected:
// device_execute_interface overrides
virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 30 - 1) / 30; }
virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 30); }
};
class i8022_device : public mcs48_cpu_device
{
public:
// construction/destruction
i8022_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
protected:
// device_execute_interface overrides
virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 30 - 1) / 30; }
virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 30); }
};
class i8035_device : public mcs48_cpu_device
{
public:
// construction/destruction
i8035_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class i8048_device : public mcs48_cpu_device
{
public:
// construction/destruction
i8048_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class i8648_device : public mcs48_cpu_device
{
public:
// construction/destruction
i8648_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class i8748_device : public mcs48_cpu_device
{
public:
// construction/destruction
i8748_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class i8039_device : public mcs48_cpu_device
{
public:
// construction/destruction
i8039_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class i8049_device : public mcs48_cpu_device
{
public:
// construction/destruction
i8049_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class i8749_device : public mcs48_cpu_device
{
public:
// construction/destruction
i8749_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class i8040_device : public mcs48_cpu_device
{
public:
// construction/destruction
i8040_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class i8050_device : public mcs48_cpu_device
{
public:
// construction/destruction
i8050_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class mb8884_device : public mcs48_cpu_device
{
public:
// construction/destruction
mb8884_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class n7751_device : public mcs48_cpu_device
{
public:
// construction/destruction
n7751_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class m58715_device : public mcs48_cpu_device
{
public:
// construction/destruction
m58715_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
/* disassemblers */ class upi41_cpu_device : public mcs48_cpu_device
CPU_DISASSEMBLE( mcs48 ); {
CPU_DISASSEMBLE( upi41 ); public:
// construction/destruction
upi41_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int rom_size, int ram_size);
/* functions for talking to the input/output buffers on the UPI41-class chips */
DECLARE_READ8_MEMBER(upi41_master_r);
DECLARE_WRITE8_MEMBER(upi41_master_w);
protected:
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
TIMER_CALLBACK_MEMBER( master_callback );
};
class i8041_device : public upi41_cpu_device
{
public:
// construction/destruction
i8041_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class i8741_device : public upi41_cpu_device
{
public:
// construction/destruction
i8741_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class i8042_device : public upi41_cpu_device
{
public:
// construction/destruction
i8042_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class i8242_device : public upi41_cpu_device
{
public:
// construction/destruction
i8242_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class i8742_device : public upi41_cpu_device
{
public:
// construction/destruction
i8742_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
#endif /* __MCS48_H__ */ #endif /* __MCS48_H__ */

3
src/mame/includes/decocass.h
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@ -6,6 +6,7 @@
#define LOG(n,x) do { if (LOGLEVEL >= n) logerror x; } while (0) #define LOG(n,x) do { if (LOGLEVEL >= n) logerror x; } while (0)
#include "machine/decocass_tape.h" #include "machine/decocass_tape.h"
#include "cpu/mcs48/mcs48.h"
#define T1PROM 1 #define T1PROM 1
#define T1DIRECT 2 #define T1DIRECT 2
@ -35,7 +36,7 @@ public:
/* devices */ /* devices */
required_device<cpu_device> m_maincpu; required_device<cpu_device> m_maincpu;
required_device<cpu_device> m_audiocpu; required_device<cpu_device> m_audiocpu;
required_device<cpu_device> m_mcu; required_device<upi41_cpu_device> m_mcu;
required_device<decocass_tape_device> m_cassette; required_device<decocass_tape_device> m_cassette;
/* memory pointers */ /* memory pointers */

3
src/mame/includes/tnzs.h
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@ -1,6 +1,7 @@
#include "sound/dac.h" #include "sound/dac.h"
#include "sound/samples.h" #include "sound/samples.h"
#include "video/seta001.h" #include "video/seta001.h"
#include "cpu/mcs48/mcs48.h"
#define MAX_SAMPLES 0x2f /* max samples */ #define MAX_SAMPLES 0x2f /* max samples */
@ -64,7 +65,7 @@ public:
/* devices */ /* devices */
optional_device<cpu_device> m_audiocpu; optional_device<cpu_device> m_audiocpu;
optional_device<cpu_device> m_subcpu; optional_device<cpu_device> m_subcpu;
optional_device<cpu_device> m_mcu; optional_device<upi41_cpu_device> m_mcu;
DECLARE_WRITE8_MEMBER(tnzsb_sound_command_w); DECLARE_WRITE8_MEMBER(tnzsb_sound_command_w);
DECLARE_WRITE8_MEMBER(jpopnics_palette_w); DECLARE_WRITE8_MEMBER(jpopnics_palette_w);
DECLARE_WRITE8_MEMBER(jpopnics_subbankswitch_w); DECLARE_WRITE8_MEMBER(jpopnics_subbankswitch_w);

32
src/mame/machine/decocass.c
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@ -249,7 +249,7 @@ READ8_MEMBER(decocass_state::decocass_type1_r)
if (1 == (offset & 1)) if (1 == (offset & 1))
{ {
if (0 == (offset & E5XX_MASK)) if (0 == (offset & E5XX_MASK))
data = upi41_master_r(m_mcu, 1); data = m_mcu->upi41_master_r(space,1);
else else
data = 0xff; data = 0xff;
@ -279,7 +279,7 @@ READ8_MEMBER(decocass_state::decocass_type1_r)
} }
if (0 == (offset & E5XX_MASK)) if (0 == (offset & E5XX_MASK))
data = upi41_master_r(m_mcu, 0); data = m_mcu->upi41_master_r(space,0);
else else
data = 0xff; data = 0xff;
@ -426,7 +426,7 @@ READ8_MEMBER(decocass_state::decocass_type2_r)
else else
{ {
if (0 == (offset & E5XX_MASK)) if (0 == (offset & E5XX_MASK))
data = upi41_master_r(m_mcu, offset); data = m_mcu->upi41_master_r(space,offset);
else else
data = offset & 0xff; data = offset & 0xff;
@ -463,7 +463,7 @@ WRITE8_MEMBER(decocass_state::decocass_type2_w)
LOG(3,("PROM:%s D2:%d", m_type2_xx_latch ? "on" : "off", m_type2_d2_latch)); LOG(3,("PROM:%s D2:%d", m_type2_xx_latch ? "on" : "off", m_type2_d2_latch));
} }
} }
upi41_master_w(m_mcu, offset & 1, data); m_mcu->upi41_master_w(space,offset & 1, data);
#ifdef MAME_DEBUG #ifdef MAME_DEBUG
decocass_fno(offset, data); decocass_fno(offset, data);
@ -506,7 +506,7 @@ READ8_MEMBER(decocass_state::decocass_type3_r)
{ {
if (0 == (offset & E5XX_MASK)) if (0 == (offset & E5XX_MASK))
{ {
data = upi41_master_r(m_mcu, 1); data = m_mcu->upi41_master_r(space,1);
LOG(4,("%10s 6502-PC: %04x decocass_type3_r(%02x): $%02x <- 8041 STATUS\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data)); LOG(4,("%10s 6502-PC: %04x decocass_type3_r(%02x): $%02x <- 8041 STATUS\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data));
} }
else else
@ -527,7 +527,7 @@ READ8_MEMBER(decocass_state::decocass_type3_r)
{ {
if (0 == (offset & E5XX_MASK)) if (0 == (offset & E5XX_MASK))
{ {
save = upi41_master_r(m_mcu, 0); save = m_mcu->upi41_master_r(space,0);
switch (m_type3_swap) switch (m_type3_swap)
{ {
case TYPE3_SWAP_01: case TYPE3_SWAP_01:
@ -710,7 +710,7 @@ WRITE8_MEMBER(decocass_state::decocass_type3_w)
} }
} }
LOG(3,("%10s 6502-PC: %04x decocass_e5xx_w(%02x): $%02x -> %s\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, offset & 1 ? "8041-CMND" : "8041-DATA")); LOG(3,("%10s 6502-PC: %04x decocass_e5xx_w(%02x): $%02x -> %s\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, offset & 1 ? "8041-CMND" : "8041-DATA"));
upi41_master_w(m_mcu, offset, data); m_mcu->upi41_master_w(space,offset, data);
} }
/*************************************************************************** /***************************************************************************
@ -734,7 +734,7 @@ READ8_MEMBER(decocass_state::decocass_type4_r)
{ {
if (0 == (offset & E5XX_MASK)) if (0 == (offset & E5XX_MASK))
{ {
data = upi41_master_r(m_mcu, 1); data = m_mcu->upi41_master_r(space,1);
LOG(4,("%10s 6502-PC: %04x decocass_type4_r(%02x): $%02x <- 8041 STATUS\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data)); LOG(4,("%10s 6502-PC: %04x decocass_type4_r(%02x): $%02x <- 8041 STATUS\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data));
} }
else else
@ -757,7 +757,7 @@ READ8_MEMBER(decocass_state::decocass_type4_r)
{ {
if (0 == (offset & E5XX_MASK)) if (0 == (offset & E5XX_MASK))
{ {
data = upi41_master_r(m_mcu, 0); data = m_mcu->upi41_master_r(space,0);
LOG(3,("%10s 6502-PC: %04x decocass_type4_r(%02x): $%02x '%c' <- open bus (D0 replaced with latch)\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, (data >= 32) ? data : '.')); LOG(3,("%10s 6502-PC: %04x decocass_type4_r(%02x): $%02x '%c' <- open bus (D0 replaced with latch)\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, (data >= 32) ? data : '.'));
} }
else else
@ -797,7 +797,7 @@ WRITE8_MEMBER(decocass_state::decocass_type4_w)
} }
} }
LOG(3,("%10s 6502-PC: %04x decocass_e5xx_w(%02x): $%02x -> %s\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, offset & 1 ? "8041-CMND" : "8041-DATA")); LOG(3,("%10s 6502-PC: %04x decocass_e5xx_w(%02x): $%02x -> %s\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, offset & 1 ? "8041-CMND" : "8041-DATA"));
upi41_master_w(m_mcu, offset, data); m_mcu->upi41_master_w(space,offset, data);
} }
/*************************************************************************** /***************************************************************************
@ -817,7 +817,7 @@ READ8_MEMBER(decocass_state::decocass_type5_r)
{ {
if (0 == (offset & E5XX_MASK)) if (0 == (offset & E5XX_MASK))
{ {
data = upi41_master_r(m_mcu, 1); data = m_mcu->upi41_master_r(space,1);
LOG(4,("%10s 6502-PC: %04x decocass_type5_r(%02x): $%02x <- 8041 STATUS\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data)); LOG(4,("%10s 6502-PC: %04x decocass_type5_r(%02x): $%02x <- 8041 STATUS\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data));
} }
else else
@ -837,7 +837,7 @@ READ8_MEMBER(decocass_state::decocass_type5_r)
{ {
if (0 == (offset & E5XX_MASK)) if (0 == (offset & E5XX_MASK))
{ {
data = upi41_master_r(m_mcu, 0); data = m_mcu->upi41_master_r(space,0);
LOG(3,("%10s 6502-PC: %04x decocass_type5_r(%02x): $%02x '%c' <- open bus (D0 replaced with latch)\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, (data >= 32) ? data : '.')); LOG(3,("%10s 6502-PC: %04x decocass_type5_r(%02x): $%02x '%c' <- open bus (D0 replaced with latch)\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, (data >= 32) ? data : '.'));
} }
else else
@ -874,7 +874,7 @@ WRITE8_MEMBER(decocass_state::decocass_type5_w)
} }
} }
LOG(3,("%10s 6502-PC: %04x decocass_e5xx_w(%02x): $%02x -> %s\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, offset & 1 ? "8041-CMND" : "8041-DATA")); LOG(3,("%10s 6502-PC: %04x decocass_e5xx_w(%02x): $%02x -> %s\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, offset & 1 ? "8041-CMND" : "8041-DATA"));
upi41_master_w(m_mcu, offset, data); m_mcu->upi41_master_w(space,offset, data);
} }
/*************************************************************************** /***************************************************************************
@ -893,7 +893,7 @@ READ8_MEMBER(decocass_state::decocass_nodong_r)
{ {
if (0 == (offset & E5XX_MASK)) if (0 == (offset & E5XX_MASK))
{ {
data = upi41_master_r(m_mcu, 1); data = m_mcu->upi41_master_r(space,1);
LOG(4,("%10s 6502-PC: %04x decocass_nodong_r(%02x): $%02x <- 8041 STATUS\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data)); LOG(4,("%10s 6502-PC: %04x decocass_nodong_r(%02x): $%02x <- 8041 STATUS\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data));
} }
else else
@ -906,7 +906,7 @@ READ8_MEMBER(decocass_state::decocass_nodong_r)
{ {
if (0 == (offset & E5XX_MASK)) if (0 == (offset & E5XX_MASK))
{ {
data = upi41_master_r(m_mcu, 0); data = m_mcu->upi41_master_r(space,0);
LOG(3,("%10s 6502-PC: %04x decocass_nodong_r(%02x): $%02x '%c' <- open bus (D0 replaced with latch)\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, (data >= 32) ? data : '.')); LOG(3,("%10s 6502-PC: %04x decocass_nodong_r(%02x): $%02x '%c' <- open bus (D0 replaced with latch)\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, (data >= 32) ? data : '.'));
} }
else else
@ -978,7 +978,7 @@ WRITE8_MEMBER(decocass_state::decocass_e5xx_w)
if (0 == (offset & E5XX_MASK)) if (0 == (offset & E5XX_MASK))
{ {
LOG(3,("%10s 6502-PC: %04x decocass_e5xx_w(%02x): $%02x -> %s\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, offset & 1 ? "8041-CMND" : "8041-DATA")); LOG(3,("%10s 6502-PC: %04x decocass_e5xx_w(%02x): $%02x -> %s\n", space.machine().time().as_string(6), space.device().safe_pcbase(), offset, data, offset & 1 ? "8041-CMND" : "8041-DATA"));
upi41_master_w(m_mcu, offset & 1, data); m_mcu->upi41_master_w(space,offset & 1, data);
#ifdef MAME_DEBUG #ifdef MAME_DEBUG
decocass_fno(offset, data); decocass_fno(offset, data);
#endif #endif

4
src/mame/machine/tnzs.c
View File

@ -47,7 +47,7 @@ READ8_MEMBER(tnzs_state::mcu_tnzs_r)
{ {
UINT8 data; UINT8 data;
data = upi41_master_r(m_mcu, offset & 1); data = m_mcu->upi41_master_r(space, offset & 1);
space.device().execute().yield(); space.device().execute().yield();
// logerror("PC %04x: read %02x from mcu $c00%01x\n", space.device().safe_pcbase(), data, offset); // logerror("PC %04x: read %02x from mcu $c00%01x\n", space.device().safe_pcbase(), data, offset);
@ -59,7 +59,7 @@ WRITE8_MEMBER(tnzs_state::mcu_tnzs_w)
{ {
// logerror("PC %04x: write %02x to mcu $c00%01x\n", space.device().safe_pcbase(), data, offset); // logerror("PC %04x: write %02x to mcu $c00%01x\n", space.device().safe_pcbase(), data, offset);
upi41_master_w(m_mcu, offset & 1, data); m_mcu->upi41_master_w(space, offset & 1, data);
} }

4
src/mess/drivers/dmv.c
View File

@ -133,12 +133,12 @@ READ8_MEMBER(dmv_state::sys_status_r)
READ8_MEMBER(dmv_state::kb_ctrl_mcu_r) READ8_MEMBER(dmv_state::kb_ctrl_mcu_r)
{ {
return upi41_master_r(machine().device("kb_ctrl_mcu"), offset); return machine().device<upi41_cpu_device>("kb_ctrl_mcu")->upi41_master_r(space, offset);
} }
WRITE8_MEMBER(dmv_state::kb_ctrl_mcu_w) WRITE8_MEMBER(dmv_state::kb_ctrl_mcu_w)
{ {
upi41_master_w(machine().device("kb_ctrl_mcu"), offset, data); machine().device<upi41_cpu_device>("kb_ctrl_mcu")->upi41_master_w(space, offset, data);
} }
static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels ) static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels )

8
src/mess/drivers/fidelz80.c
View File

@ -976,22 +976,22 @@ WRITE8_MEMBER(fidelz80_state::digit_w)
WRITE8_MEMBER(fidelz80_state::mcu_data_w) WRITE8_MEMBER(fidelz80_state::mcu_data_w)
{ {
upi41_master_w(m_i8041, 0, data); m_i8041->upi41_master_w(space, 0, data);
} }
WRITE8_MEMBER(fidelz80_state::mcu_command_w) WRITE8_MEMBER(fidelz80_state::mcu_command_w)
{ {
upi41_master_w(m_i8041, 1, data); m_i8041->upi41_master_w(space, 1, data);
} }
READ8_MEMBER(fidelz80_state::mcu_data_r) READ8_MEMBER(fidelz80_state::mcu_data_r)
{ {
return upi41_master_r(m_i8041, 0); return m_i8041->upi41_master_r(space, 0);
} }
READ8_MEMBER(fidelz80_state::mcu_status_r) READ8_MEMBER(fidelz80_state::mcu_status_r)
{ {
return upi41_master_r(m_i8041, 1); return m_i8041->upi41_master_r(space, 1);
} }
WRITE8_MEMBER( fidelz80_state::bridgec_speech_w ) WRITE8_MEMBER( fidelz80_state::bridgec_speech_w )

8
src/mess/drivers/pcw.c
View File

@ -641,14 +641,14 @@ void pcw_state::pcw_printer_fire_pins(UINT16 pins)
WRITE8_MEMBER(pcw_state::pcw_printer_data_w) WRITE8_MEMBER(pcw_state::pcw_printer_data_w)
{ {
m_printer_data = data; m_printer_data = data;
upi41_master_w(machine().device("printer_mcu"),0,data); machine().device<upi41_cpu_device>("printer_mcu")->upi41_master_w(space,0,data);
logerror("PRN [0xFC]: Sent command %02x\n",data); logerror("PRN [0xFC]: Sent command %02x\n",data);
} }
WRITE8_MEMBER(pcw_state::pcw_printer_command_w) WRITE8_MEMBER(pcw_state::pcw_printer_command_w)
{ {
m_printer_command = data; m_printer_command = data;
upi41_master_w(machine().device("printer_mcu"),1,data); machine().device<upi41_cpu_device>("printer_mcu")->upi41_master_w(space,1,data);
logerror("PRN [0xFD]: Sent command %02x\n",data); logerror("PRN [0xFD]: Sent command %02x\n",data);
} }
@ -661,7 +661,7 @@ WRITE8_MEMBER(pcw_state::pcw_printer_command_w)
// anything else = no printer // anything else = no printer
READ8_MEMBER(pcw_state::pcw_printer_data_r) READ8_MEMBER(pcw_state::pcw_printer_data_r)
{ {
return upi41_master_r(machine().device("printer_mcu"),0); return machine().device<upi41_cpu_device>("printer_mcu")->upi41_master_r(space,0);
} }
// printer status // printer status
@ -675,7 +675,7 @@ READ8_MEMBER(pcw_state::pcw_printer_data_r)
// bit 0 - controller fault // bit 0 - controller fault
READ8_MEMBER(pcw_state::pcw_printer_status_r) READ8_MEMBER(pcw_state::pcw_printer_status_r)
{ {
return upi41_master_r(machine().device("printer_mcu"),1); return machine().device<upi41_cpu_device>("printer_mcu")->upi41_master_r(space,1);
} }
/* MCU handlers */ /* MCU handlers */

2
src/mess/includes/fidelz80.h
View File

@ -27,7 +27,7 @@ public:
required_device<cpu_device> m_maincpu; required_device<cpu_device> m_maincpu;
optional_device<s14001a_device> m_speech; optional_device<s14001a_device> m_speech;
optional_device<beep_device> m_beep; optional_device<beep_device> m_beep;
optional_device<cpu_device> m_i8041; optional_device<i8041_device> m_i8041;
optional_device<i8243_device> m_i8243; optional_device<i8243_device> m_i8243;
UINT16 m_kp_matrix; // keypad/leds matrix UINT16 m_kp_matrix; // keypad/leds matrix

10
src/mess/machine/at_keybc.c
View File

@ -108,7 +108,7 @@ void at_keyboard_controller_device::device_config_complete()
void at_keyboard_controller_device::device_start() void at_keyboard_controller_device::device_start()
{ {
// find our cpu // find our cpu
m_cpu = downcast<device_t *>(subdevice("at_keybc")); m_cpu = downcast<upi41_cpu_device *>(subdevice("at_keybc"));
// resolve callbacks // resolve callbacks
m_system_reset_func.resolve(m_system_reset_cb, *this); m_system_reset_func.resolve(m_system_reset_cb, *this);
@ -199,22 +199,22 @@ WRITE8_MEMBER( at_keyboard_controller_device::p2_w )
READ8_MEMBER( at_keyboard_controller_device::data_r ) READ8_MEMBER( at_keyboard_controller_device::data_r )
{ {
return upi41_master_r(m_cpu, 0); return m_cpu->upi41_master_r(space, 0);
} }
WRITE8_MEMBER( at_keyboard_controller_device::data_w ) WRITE8_MEMBER( at_keyboard_controller_device::data_w )
{ {
upi41_master_w(m_cpu, 0, data); m_cpu->upi41_master_w(space, 0, data);
} }
READ8_MEMBER( at_keyboard_controller_device::status_r ) READ8_MEMBER( at_keyboard_controller_device::status_r )
{ {
return upi41_master_r(m_cpu, 1); return m_cpu->upi41_master_r(space, 1);
} }
WRITE8_MEMBER( at_keyboard_controller_device::command_w ) WRITE8_MEMBER( at_keyboard_controller_device::command_w )
{ {
upi41_master_w(m_cpu, 1, data); m_cpu->upi41_master_w(space, 1, data);
} }
WRITE_LINE_MEMBER( at_keyboard_controller_device::keyboard_clock_w ) WRITE_LINE_MEMBER( at_keyboard_controller_device::keyboard_clock_w )

3
src/mess/machine/at_keybc.h
View File

@ -10,6 +10,7 @@
#define __AT_KEYBC_H__ #define __AT_KEYBC_H__
#include "emu.h" #include "emu.h"
#include "cpu/mcs48/mcs48.h"
//************************************************************************** //**************************************************************************
@ -76,7 +77,7 @@ protected:
virtual machine_config_constructor device_mconfig_additions() const; virtual machine_config_constructor device_mconfig_additions() const;
private: private:
// internal state // internal state
device_t *m_cpu; upi41_cpu_device *m_cpu;
devcb_resolved_write_line m_system_reset_func; devcb_resolved_write_line m_system_reset_func;
devcb_resolved_write_line m_gate_a20_func; devcb_resolved_write_line m_gate_a20_func;