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mc68hc11.c: Modernized cpu core (nw)

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This commit is contained in:
Wilbert Pol 2013-08-23 21:33:46 +00:00
parent 875f96a858
commit eccbdf381f
9 changed files with 2461 additions and 2233 deletions
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3020
src/emu/cpu/mc68hc11/hc11ops.c
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630
src/emu/cpu/mc68hc11/hc11ops.h
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@ -1,323 +1,317 @@
struct hc11_opcode_list_struct
{
int page;
int opcode;
void (*handler)(hc11_state *cpustate);
};
static const hc11_opcode_list_struct hc11_opcode_list[] = const mc68hc11_cpu_device::hc11_opcode_list_struct mc68hc11_cpu_device::hc11_opcode_list[] =
{ {
/* page opcode handler */ /* page opcode handler */
{ 0, 0x1b, HC11OP(aba) }, { 0, 0x1b, &HC11OP(aba) },
{ 0, 0x3a, HC11OP(abx) }, { 0, 0x3a, &HC11OP(abx) },
{ 0x18, 0x3a, HC11OP(aby) }, { 0x18, 0x3a, &HC11OP(aby) },
{ 0, 0x89, HC11OP(adca_imm) }, { 0, 0x89, &HC11OP(adca_imm) },
{ 0, 0x99, HC11OP(adca_dir) }, { 0, 0x99, &HC11OP(adca_dir) },
{ 0, 0xb9, HC11OP(adca_ext) }, { 0, 0xb9, &HC11OP(adca_ext) },
{ 0, 0xa9, HC11OP(adca_indx) }, { 0, 0xa9, &HC11OP(adca_indx) },
{ 0x18, 0xa9, HC11OP(adca_indy) }, { 0x18, 0xa9, &HC11OP(adca_indy) },
{ 0, 0xc9, HC11OP(adcb_imm) }, { 0, 0xc9, &HC11OP(adcb_imm) },
{ 0, 0xd9, HC11OP(adcb_dir) }, { 0, 0xd9, &HC11OP(adcb_dir) },
{ 0, 0xf9, HC11OP(adcb_ext) }, { 0, 0xf9, &HC11OP(adcb_ext) },
{ 0, 0xe9, HC11OP(adcb_indx) }, { 0, 0xe9, &HC11OP(adcb_indx) },
{ 0x18, 0xe9, HC11OP(adcb_indy) }, { 0x18, 0xe9, &HC11OP(adcb_indy) },
{ 0, 0x8b, HC11OP(adda_imm) }, { 0, 0x8b, &HC11OP(adda_imm) },
{ 0, 0x9b, HC11OP(adda_dir) }, { 0, 0x9b, &HC11OP(adda_dir) },
{ 0, 0xbb, HC11OP(adda_ext) }, { 0, 0xbb, &HC11OP(adda_ext) },
{ 0, 0xab, HC11OP(adda_indx) }, { 0, 0xab, &HC11OP(adda_indx) },
{ 0x18, 0xab, HC11OP(adda_indy) }, { 0x18, 0xab, &HC11OP(adda_indy) },
{ 0, 0xcb, HC11OP(addb_imm) }, { 0, 0xcb, &HC11OP(addb_imm) },
{ 0, 0xdb, HC11OP(addb_dir) }, { 0, 0xdb, &HC11OP(addb_dir) },
{ 0, 0xfb, HC11OP(addb_ext) }, { 0, 0xfb, &HC11OP(addb_ext) },
{ 0, 0xeb, HC11OP(addb_indx) }, { 0, 0xeb, &HC11OP(addb_indx) },
{ 0x18, 0xeb, HC11OP(addb_indy) }, { 0x18, 0xeb, &HC11OP(addb_indy) },
{ 0, 0xc3, HC11OP(addd_imm) }, { 0, 0xc3, &HC11OP(addd_imm) },
{ 0, 0xd3, HC11OP(addd_dir) }, { 0, 0xd3, &HC11OP(addd_dir) },
{ 0, 0xf3, HC11OP(addd_ext) }, { 0, 0xf3, &HC11OP(addd_ext) },
{ 0, 0xe3, HC11OP(addd_indx) }, { 0, 0xe3, &HC11OP(addd_indx) },
{ 0x18, 0xe3, HC11OP(addd_indy) }, { 0x18, 0xe3, &HC11OP(addd_indy) },
{ 0, 0x84, HC11OP(anda_imm) }, { 0, 0x84, &HC11OP(anda_imm) },
{ 0, 0x94, HC11OP(anda_dir) }, { 0, 0x94, &HC11OP(anda_dir) },
{ 0, 0xb4, HC11OP(anda_ext) }, { 0, 0xb4, &HC11OP(anda_ext) },
{ 0, 0xa4, HC11OP(anda_indx) }, { 0, 0xa4, &HC11OP(anda_indx) },
{ 0x18, 0xa4, HC11OP(anda_indy) }, { 0x18, 0xa4, &HC11OP(anda_indy) },
{ 0, 0xc4, HC11OP(andb_imm) }, { 0, 0xc4, &HC11OP(andb_imm) },
{ 0, 0xd4, HC11OP(andb_dir) }, { 0, 0xd4, &HC11OP(andb_dir) },
{ 0, 0xf4, HC11OP(andb_ext) }, { 0, 0xf4, &HC11OP(andb_ext) },
{ 0, 0xe4, HC11OP(andb_indx) }, { 0, 0xe4, &HC11OP(andb_indx) },
{ 0x18, 0xe4, HC11OP(andb_indy) }, { 0x18, 0xe4, &HC11OP(andb_indy) },
{ 0, 0x48, HC11OP(asla) }, { 0, 0x48, &HC11OP(asla) },
{ 0, 0x58, HC11OP(aslb) }, { 0, 0x58, &HC11OP(aslb) },
{ 0, 0x78, HC11OP(asl_ext) }, { 0, 0x78, &HC11OP(asl_ext) },
// { 0, 0x68, HC11OP(asl_indx) }, // { 0, 0x68, &HC11OP(asl_indx) },
// { 0x18, 0x68, HC11OP(asl_indy) }, // { 0x18, 0x68, &HC11OP(asl_indy) },
// { 0, 0x47, HC11OP(asra) }, // { 0, 0x47, &HC11OP(asra) },
// { 0, 0x57, HC11OP(asrb) }, // { 0, 0x57, &HC11OP(asrb) },
// { 0, 0x77, HC11OP(asr_ext) }, // { 0, 0x77, &HC11OP(asr_ext) },
// { 0, 0x67, HC11OP(asr_indx) }, // { 0, 0x67, &HC11OP(asr_indx) },
// { 0x18, 0x67, HC11OP(asr_indy) }, // { 0x18, 0x67, &HC11OP(asr_indy) },
{ 0, 0x24, HC11OP(bcc) }, { 0, 0x24, &HC11OP(bcc) },
{ 0, 0x15, HC11OP(bclr_dir) }, { 0, 0x15, &HC11OP(bclr_dir) },
{ 0, 0x1d, HC11OP(bclr_indx) }, { 0, 0x1d, &HC11OP(bclr_indx) },
// { 0x18, 0x1d, HC11OP(bclr_indy) }, // { 0x18, 0x1d, &HC11OP(bclr_indy) },
{ 0, 0x25, HC11OP(bcs) }, { 0, 0x25, &HC11OP(bcs) },
{ 0, 0x27, HC11OP(beq) }, { 0, 0x27, &HC11OP(beq) },
// { 0, 0x2c, HC11OP(bge) }, // { 0, 0x2c, &HC11OP(bge) },
// { 0, 0x2e, HC11OP(bgt) }, // { 0, 0x2e, &HC11OP(bgt) },
{ 0, 0x22, HC11OP(bhi) }, { 0, 0x22, &HC11OP(bhi) },
{ 0, 0x85, HC11OP(bita_imm) }, { 0, 0x85, &HC11OP(bita_imm) },
{ 0, 0x95, HC11OP(bita_dir) }, { 0, 0x95, &HC11OP(bita_dir) },
{ 0, 0xb5, HC11OP(bita_ext) }, { 0, 0xb5, &HC11OP(bita_ext) },
{ 0, 0xa5, HC11OP(bita_indx) }, { 0, 0xa5, &HC11OP(bita_indx) },
{ 0x18, 0xa5, HC11OP(bita_indy) }, { 0x18, 0xa5, &HC11OP(bita_indy) },
{ 0, 0xc5, HC11OP(bitb_imm) }, { 0, 0xc5, &HC11OP(bitb_imm) },
{ 0, 0xd5, HC11OP(bitb_dir) }, { 0, 0xd5, &HC11OP(bitb_dir) },
{ 0, 0xf5, HC11OP(bitb_ext) }, { 0, 0xf5, &HC11OP(bitb_ext) },
{ 0, 0xe5, HC11OP(bitb_indx) }, { 0, 0xe5, &HC11OP(bitb_indx) },
{ 0x18, 0xe5, HC11OP(bitb_indy) }, { 0x18, 0xe5, &HC11OP(bitb_indy) },
{ 0, 0x2f, HC11OP(ble) }, { 0, 0x2f, &HC11OP(ble) },
{ 0, 0x23, HC11OP(bls) }, { 0, 0x23, &HC11OP(bls) },
// { 0, 0x2d, HC11OP(blt) }, // { 0, 0x2d, &HC11OP(blt) },
{ 0, 0x2b, HC11OP(bmi) }, { 0, 0x2b, &HC11OP(bmi) },
{ 0, 0x26, HC11OP(bne) }, { 0, 0x26, &HC11OP(bne) },
{ 0, 0x2a, HC11OP(bpl) }, { 0, 0x2a, &HC11OP(bpl) },
{ 0, 0x20, HC11OP(bra) }, { 0, 0x20, &HC11OP(bra) },
{ 0, 0x13, HC11OP(brclr_dir) }, { 0, 0x13, &HC11OP(brclr_dir) },
{ 0, 0x1f, HC11OP(brclr_indx) }, { 0, 0x1f, &HC11OP(brclr_indx) },
// { 0x18, 0x1f, HC11OP(brclr_indy) }, // { 0x18, 0x1f, &HC11OP(brclr_indy) },
{ 0, 0x21, HC11OP(brn) }, { 0, 0x21, &HC11OP(brn) },
{ 0, 0x12, HC11OP(brset_dir) }, { 0, 0x12, &HC11OP(brset_dir) },
{ 0, 0x1e, HC11OP(brset_indx) }, { 0, 0x1e, &HC11OP(brset_indx) },
// { 0x18, 0x1e, HC11OP(brset_indy) }, // { 0x18, 0x1e, &HC11OP(brset_indy) },
{ 0, 0x14, HC11OP(bset_dir) }, { 0, 0x14, &HC11OP(bset_dir) },
{ 0, 0x1c, HC11OP(bset_indx) }, { 0, 0x1c, &HC11OP(bset_indx) },
// { 0x18, 0x1c, HC11OP(bset_indy) }, // { 0x18, 0x1c, &HC11OP(bset_indy) },
{ 0, 0x8d, HC11OP(bsr) }, { 0, 0x8d, &HC11OP(bsr) },
{ 0, 0x28, HC11OP(bvc) }, { 0, 0x28, &HC11OP(bvc) },
{ 0, 0x29, HC11OP(bvs) }, { 0, 0x29, &HC11OP(bvs) },
{ 0, 0x11, HC11OP(cba) }, { 0, 0x11, &HC11OP(cba) },
{ 0, 0x0c, HC11OP(clc) }, { 0, 0x0c, &HC11OP(clc) },
{ 0, 0x0e, HC11OP(cli) }, { 0, 0x0e, &HC11OP(cli) },
{ 0, 0x4f, HC11OP(clra) }, { 0, 0x4f, &HC11OP(clra) },
{ 0, 0x5f, HC11OP(clrb) }, { 0, 0x5f, &HC11OP(clrb) },
{ 0, 0x7f, HC11OP(clr_ext) }, { 0, 0x7f, &HC11OP(clr_ext) },
{ 0, 0x6f, HC11OP(clr_indx) }, { 0, 0x6f, &HC11OP(clr_indx) },
{ 0x18, 0x6f, HC11OP(clr_indy) }, { 0x18, 0x6f, &HC11OP(clr_indy) },
{ 0, 0x0a, HC11OP(clv) }, { 0, 0x0a, &HC11OP(clv) },
{ 0, 0x81, HC11OP(cmpa_imm) }, { 0, 0x81, &HC11OP(cmpa_imm) },
{ 0, 0x91, HC11OP(cmpa_dir) }, { 0, 0x91, &HC11OP(cmpa_dir) },
{ 0, 0xb1, HC11OP(cmpa_ext) }, { 0, 0xb1, &HC11OP(cmpa_ext) },
{ 0, 0xa1, HC11OP(cmpa_indx) }, { 0, 0xa1, &HC11OP(cmpa_indx) },
{ 0x18, 0xa1, HC11OP(cmpa_indy) }, { 0x18, 0xa1, &HC11OP(cmpa_indy) },
{ 0, 0xc1, HC11OP(cmpb_imm) }, { 0, 0xc1, &HC11OP(cmpb_imm) },
{ 0, 0xd1, HC11OP(cmpb_dir) }, { 0, 0xd1, &HC11OP(cmpb_dir) },
{ 0, 0xf1, HC11OP(cmpb_ext) }, { 0, 0xf1, &HC11OP(cmpb_ext) },
{ 0, 0xe1, HC11OP(cmpb_indx) }, { 0, 0xe1, &HC11OP(cmpb_indx) },
{ 0x18, 0xe1, HC11OP(cmpb_indy) }, { 0x18, 0xe1, &HC11OP(cmpb_indy) },
{ 0, 0x43, HC11OP(coma) }, { 0, 0x43, &HC11OP(coma) },
{ 0, 0x53, HC11OP(comb) }, { 0, 0x53, &HC11OP(comb) },
// { 0, 0x73, HC11OP(com_ext) }, // { 0, 0x73, &HC11OP(com_ext) },
// { 0, 0x63, HC11OP(com_indx) }, // { 0, 0x63, &HC11OP(com_indx) },
// { 0x18, 0x63, HC11OP(com_indy) }, // { 0x18, 0x63, &HC11OP(com_indy) },
{ 0x1a, 0x83, HC11OP(cpd_imm) }, { 0x1a, 0x83, &HC11OP(cpd_imm) },
{ 0x1a, 0x93, HC11OP(cpd_dir) }, { 0x1a, 0x93, &HC11OP(cpd_dir) },
{ 0x1a, 0xb3, HC11OP(cpd_ext) }, { 0x1a, 0xb3, &HC11OP(cpd_ext) },
{ 0x1a, 0xa3, HC11OP(cpd_indx) }, { 0x1a, 0xa3, &HC11OP(cpd_indx) },
{ 0xcd, 0xa3, HC11OP(cpd_indy) }, { 0xcd, 0xa3, &HC11OP(cpd_indy) },
{ 0, 0x8c, HC11OP(cpx_imm) }, { 0, 0x8c, &HC11OP(cpx_imm) },
{ 0, 0x9c, HC11OP(cpx_dir) }, { 0, 0x9c, &HC11OP(cpx_dir) },
{ 0, 0xbc, HC11OP(cpx_ext) }, { 0, 0xbc, &HC11OP(cpx_ext) },
{ 0, 0xac, HC11OP(cpx_indx) }, { 0, 0xac, &HC11OP(cpx_indx) },
{ 0xcd, 0xac, HC11OP(cpx_indy) }, { 0xcd, 0xac, &HC11OP(cpx_indy) },
{ 0x18, 0x8c, HC11OP(cpy_imm) }, { 0x18, 0x8c, &HC11OP(cpy_imm) },
{ 0x18, 0x9c, HC11OP(cpy_dir) }, { 0x18, 0x9c, &HC11OP(cpy_dir) },
{ 0x18, 0xbc, HC11OP(cpy_ext) }, { 0x18, 0xbc, &HC11OP(cpy_ext) },
{ 0x1a, 0xac, HC11OP(cpy_indx) }, { 0x1a, 0xac, &HC11OP(cpy_indx) },
{ 0x18, 0xac, HC11OP(cpy_indy) }, { 0x18, 0xac, &HC11OP(cpy_indy) },
// { 0, 0x19, HC11OP(daa) }, // { 0, 0x19, &HC11OP(daa) },
{ 0, 0x4a, HC11OP(deca) }, { 0, 0x4a, &HC11OP(deca) },
{ 0, 0x5a, HC11OP(decb) }, { 0, 0x5a, &HC11OP(decb) },
{ 0, 0x7a, HC11OP(dec_ext) }, { 0, 0x7a, &HC11OP(dec_ext) },
{ 0, 0x6a, HC11OP(dec_indx) }, { 0, 0x6a, &HC11OP(dec_indx) },
{ 0x18, 0x6a, HC11OP(dec_indy) }, { 0x18, 0x6a, &HC11OP(dec_indy) },
// { 0, 0x34, HC11OP(des) }, // { 0, 0x34, &HC11OP(des) },
{ 0, 0x09, HC11OP(dex) }, { 0, 0x09, &HC11OP(dex) },
{ 0x18, 0x09, HC11OP(dey) }, { 0x18, 0x09, &HC11OP(dey) },
{ 0, 0x88, HC11OP(eora_imm) }, { 0, 0x88, &HC11OP(eora_imm) },
{ 0, 0x98, HC11OP(eora_dir) }, { 0, 0x98, &HC11OP(eora_dir) },
{ 0, 0xb8, HC11OP(eora_ext) }, { 0, 0xb8, &HC11OP(eora_ext) },
{ 0, 0xa8, HC11OP(eora_indx) }, { 0, 0xa8, &HC11OP(eora_indx) },
{ 0x18, 0xa8, HC11OP(eora_indy) }, { 0x18, 0xa8, &HC11OP(eora_indy) },
{ 0, 0xc8, HC11OP(eorb_imm) }, { 0, 0xc8, &HC11OP(eorb_imm) },
{ 0, 0xd8, HC11OP(eorb_dir) }, { 0, 0xd8, &HC11OP(eorb_dir) },
{ 0, 0xf8, HC11OP(eorb_ext) }, { 0, 0xf8, &HC11OP(eorb_ext) },
{ 0, 0xe8, HC11OP(eorb_indx) }, { 0, 0xe8, &HC11OP(eorb_indx) },
{ 0x18, 0xe8, HC11OP(eorb_indy) }, { 0x18, 0xe8, &HC11OP(eorb_indy) },
// { 0, 0x03, HC11OP(fdiv) }, // { 0, 0x03, &HC11OP(fdiv) },
{ 0, 0x02, HC11OP(idiv) }, { 0, 0x02, &HC11OP(idiv) },
{ 0, 0x4c, HC11OP(inca) }, { 0, 0x4c, &HC11OP(inca) },
{ 0, 0x5c, HC11OP(incb) }, { 0, 0x5c, &HC11OP(incb) },
{ 0, 0x7c, HC11OP(inc_ext) }, { 0, 0x7c, &HC11OP(inc_ext) },
{ 0, 0x6c, HC11OP(inc_indx) }, { 0, 0x6c, &HC11OP(inc_indx) },
{ 0x18, 0x6c, HC11OP(inc_indy) }, { 0x18, 0x6c, &HC11OP(inc_indy) },
// { 0, 0x31, HC11OP(ins) }, // { 0, 0x31, &HC11OP(ins) },
{ 0, 0x08, HC11OP(inx) }, { 0, 0x08, &HC11OP(inx) },
{ 0x18, 0x08, HC11OP(iny) }, { 0x18, 0x08, &HC11OP(iny) },
{ 0, 0x7e, HC11OP(jmp_ext) }, { 0, 0x7e, &HC11OP(jmp_ext) },
{ 0, 0x6e, HC11OP(jmp_indx) }, { 0, 0x6e, &HC11OP(jmp_indx) },
{ 0x18, 0x6e, HC11OP(jmp_indy) }, { 0x18, 0x6e, &HC11OP(jmp_indy) },
{ 0, 0x9d, HC11OP(jsr_dir) }, { 0, 0x9d, &HC11OP(jsr_dir) },
{ 0, 0xbd, HC11OP(jsr_ext) }, { 0, 0xbd, &HC11OP(jsr_ext) },
{ 0, 0xad, HC11OP(jsr_indx) }, { 0, 0xad, &HC11OP(jsr_indx) },
{ 0x18, 0xad, HC11OP(jsr_indy) }, { 0x18, 0xad, &HC11OP(jsr_indy) },
{ 0, 0x86, HC11OP(ldaa_imm) }, { 0, 0x86, &HC11OP(ldaa_imm) },
{ 0, 0x96, HC11OP(ldaa_dir) }, { 0, 0x96, &HC11OP(ldaa_dir) },
{ 0, 0xb6, HC11OP(ldaa_ext) }, { 0, 0xb6, &HC11OP(ldaa_ext) },
{ 0, 0xa6, HC11OP(ldaa_indx) }, { 0, 0xa6, &HC11OP(ldaa_indx) },
{ 0x18, 0xa6, HC11OP(ldaa_indy) }, { 0x18, 0xa6, &HC11OP(ldaa_indy) },
{ 0, 0xc6, HC11OP(ldab_imm) }, { 0, 0xc6, &HC11OP(ldab_imm) },
{ 0, 0xd6, HC11OP(ldab_dir) }, { 0, 0xd6, &HC11OP(ldab_dir) },
{ 0, 0xf6, HC11OP(ldab_ext) }, { 0, 0xf6, &HC11OP(ldab_ext) },
{ 0, 0xe6, HC11OP(ldab_indx) }, { 0, 0xe6, &HC11OP(ldab_indx) },
{ 0x18, 0xe6, HC11OP(ldab_indy) }, { 0x18, 0xe6, &HC11OP(ldab_indy) },
{ 0, 0xcc, HC11OP(ldd_imm) }, { 0, 0xcc, &HC11OP(ldd_imm) },
{ 0, 0xdc, HC11OP(ldd_dir) }, { 0, 0xdc, &HC11OP(ldd_dir) },
{ 0, 0xfc, HC11OP(ldd_ext) }, { 0, 0xfc, &HC11OP(ldd_ext) },
{ 0, 0xec, HC11OP(ldd_indx) }, { 0, 0xec, &HC11OP(ldd_indx) },
{ 0x18, 0xec, HC11OP(ldd_indy) }, { 0x18, 0xec, &HC11OP(ldd_indy) },
{ 0, 0x8e, HC11OP(lds_imm) }, { 0, 0x8e, &HC11OP(lds_imm) },
{ 0, 0x9e, HC11OP(lds_dir) }, { 0, 0x9e, &HC11OP(lds_dir) },
{ 0, 0xbe, HC11OP(lds_ext) }, { 0, 0xbe, &HC11OP(lds_ext) },
{ 0, 0xae, HC11OP(lds_indx) }, { 0, 0xae, &HC11OP(lds_indx) },
{ 0x18, 0xae, HC11OP(lds_indy) }, { 0x18, 0xae, &HC11OP(lds_indy) },
{ 0, 0xce, HC11OP(ldx_imm) }, { 0, 0xce, &HC11OP(ldx_imm) },
{ 0, 0xde, HC11OP(ldx_dir) }, { 0, 0xde, &HC11OP(ldx_dir) },
{ 0, 0xfe, HC11OP(ldx_ext) }, { 0, 0xfe, &HC11OP(ldx_ext) },
{ 0, 0xee, HC11OP(ldx_indx) }, { 0, 0xee, &HC11OP(ldx_indx) },
{ 0xcd, 0xee, HC11OP(ldx_indy) }, { 0xcd, 0xee, &HC11OP(ldx_indy) },
{ 0x18, 0xce, HC11OP(ldy_imm) }, { 0x18, 0xce, &HC11OP(ldy_imm) },
{ 0x18, 0xde, HC11OP(ldy_dir) }, { 0x18, 0xde, &HC11OP(ldy_dir) },
{ 0x18, 0xfe, HC11OP(ldy_ext) }, { 0x18, 0xfe, &HC11OP(ldy_ext) },
{ 0x1a, 0xee, HC11OP(ldy_indx) }, { 0x1a, 0xee, &HC11OP(ldy_indx) },
{ 0x18, 0xee, HC11OP(ldy_indy) }, { 0x18, 0xee, &HC11OP(ldy_indy) },
{ 0, 0x05, HC11OP(lsld) }, { 0, 0x05, &HC11OP(lsld) },
{ 0, 0x44, HC11OP(lsra) }, { 0, 0x44, &HC11OP(lsra) },
{ 0, 0x54, HC11OP(lsrb) }, { 0, 0x54, &HC11OP(lsrb) },
// { 0, 0x74, HC11OP(lsr_ext) }, // { 0, 0x74, &HC11OP(lsr_ext) },
// { 0, 0x64, HC11OP(lsr_indx) }, // { 0, 0x64, &HC11OP(lsr_indx) },
// { 0x18, 0x64, HC11OP(lsr_indy) }, // { 0x18, 0x64, &HC11OP(lsr_indy) },
{ 0, 0x04, HC11OP(lsrd) }, { 0, 0x04, &HC11OP(lsrd) },
{ 0, 0x3d, HC11OP(mul) }, { 0, 0x3d, &HC11OP(mul) },
{ 0, 0x40, HC11OP(nega) }, { 0, 0x40, &HC11OP(nega) },
{ 0, 0x50, HC11OP(negb) }, { 0, 0x50, &HC11OP(negb) },
{ 0, 0x70, HC11OP(neg_ext) }, { 0, 0x70, &HC11OP(neg_ext) },
{ 0, 0x60, HC11OP(neg_indx) }, { 0, 0x60, &HC11OP(neg_indx) },
{ 0x18, 0x60, HC11OP(neg_indy) }, { 0x18, 0x60, &HC11OP(neg_indy) },
{ 0, 0x01, HC11OP(nop) }, { 0, 0x01, &HC11OP(nop) },
{ 0, 0x8a, HC11OP(oraa_imm) }, { 0, 0x8a, &HC11OP(oraa_imm) },
{ 0, 0x9a, HC11OP(oraa_dir) }, { 0, 0x9a, &HC11OP(oraa_dir) },
{ 0, 0xba, HC11OP(oraa_ext) }, { 0, 0xba, &HC11OP(oraa_ext) },
{ 0, 0xaa, HC11OP(oraa_indx) }, { 0, 0xaa, &HC11OP(oraa_indx) },
{ 0x18, 0xaa, HC11OP(oraa_indy) }, { 0x18, 0xaa, &HC11OP(oraa_indy) },
{ 0, 0xca, HC11OP(orab_imm) }, { 0, 0xca, &HC11OP(orab_imm) },
{ 0, 0xda, HC11OP(orab_dir) }, { 0, 0xda, &HC11OP(orab_dir) },
{ 0, 0xfa, HC11OP(orab_ext) }, { 0, 0xfa, &HC11OP(orab_ext) },
{ 0, 0xea, HC11OP(orab_indx) }, { 0, 0xea, &HC11OP(orab_indx) },
{ 0x18, 0xea, HC11OP(orab_indy) }, { 0x18, 0xea, &HC11OP(orab_indy) },
{ 0, 0x36, HC11OP(psha) }, { 0, 0x36, &HC11OP(psha) },
{ 0, 0x37, HC11OP(pshb) }, { 0, 0x37, &HC11OP(pshb) },
{ 0, 0x3c, HC11OP(pshx) }, { 0, 0x3c, &HC11OP(pshx) },
{ 0x18, 0x3c, HC11OP(pshy) }, { 0x18, 0x3c, &HC11OP(pshy) },
{ 0, 0x32, HC11OP(pula) }, { 0, 0x32, &HC11OP(pula) },
{ 0, 0x33, HC11OP(pulb) }, { 0, 0x33, &HC11OP(pulb) },
{ 0, 0x38, HC11OP(pulx) }, { 0, 0x38, &HC11OP(pulx) },
{ 0x18, 0x38, HC11OP(puly) }, { 0x18, 0x38, &HC11OP(puly) },
{ 0, 0x49, HC11OP(rola) }, { 0, 0x49, &HC11OP(rola) },
{ 0, 0x59, HC11OP(rolb) }, { 0, 0x59, &HC11OP(rolb) },
{ 0, 0x79, HC11OP(rol_ext) }, { 0, 0x79, &HC11OP(rol_ext) },
{ 0, 0x69, HC11OP(rol_indx) }, { 0, 0x69, &HC11OP(rol_indx) },
{ 0x18, 0x69, HC11OP(rol_indy) }, { 0x18, 0x69, &HC11OP(rol_indy) },
{ 0, 0x46, HC11OP(rora) }, { 0, 0x46, &HC11OP(rora) },
{ 0, 0x56, HC11OP(rorb) }, { 0, 0x56, &HC11OP(rorb) },
// { 0, 0x76, HC11OP(ror_ext) }, // { 0, 0x76, &HC11OP(ror_ext) },
// { 0, 0x66, HC11OP(ror_indx) }, // { 0, 0x66, &HC11OP(ror_indx) },
// { 0x18, 0x66, HC11OP(ror_indy) }, // { 0x18, 0x66, &HC11OP(ror_indy) },
{ 0, 0x3b, HC11OP(rti) }, { 0, 0x3b, &HC11OP(rti) },
{ 0, 0x39, HC11OP(rts) }, { 0, 0x39, &HC11OP(rts) },
{ 0, 0x10, HC11OP(sba) }, { 0, 0x10, &HC11OP(sba) },
{ 0, 0x82, HC11OP(sbca_imm) }, { 0, 0x82, &HC11OP(sbca_imm) },
// { 0, 0x92, HC11OP(sbca_dir) }, // { 0, 0x92, &HC11OP(sbca_dir) },
// { 0, 0xb2, HC11OP(sbca_ext) }, // { 0, 0xb2, &HC11OP(sbca_ext) },
{ 0, 0xa2, HC11OP(sbca_indx) }, { 0, 0xa2, &HC11OP(sbca_indx) },
{ 0x18, 0xa2, HC11OP(sbca_indy) }, { 0x18, 0xa2, &HC11OP(sbca_indy) },
{ 0, 0xc2, HC11OP(sbcb_imm) }, { 0, 0xc2, &HC11OP(sbcb_imm) },
// { 0, 0xd2, HC11OP(sbcb_dir) }, // { 0, 0xd2, &HC11OP(sbcb_dir) },
// { 0, 0xf2, HC11OP(sbcb_ext) }, // { 0, 0xf2, &HC11OP(sbcb_ext) },
{ 0, 0xe2, HC11OP(sbcb_indx) }, { 0, 0xe2, &HC11OP(sbcb_indx) },
{ 0x18, 0xe2, HC11OP(sbcb_indy) }, { 0x18, 0xe2, &HC11OP(sbcb_indy) },
{ 0, 0x0d, HC11OP(sec) }, { 0, 0x0d, &HC11OP(sec) },
{ 0, 0x0f, HC11OP(sei) }, { 0, 0x0f, &HC11OP(sei) },
{ 0, 0x0b, HC11OP(sev) }, { 0, 0x0b, &HC11OP(sev) },
{ 0, 0x97, HC11OP(staa_dir) }, { 0, 0x97, &HC11OP(staa_dir) },
{ 0, 0xb7, HC11OP(staa_ext) }, { 0, 0xb7, &HC11OP(staa_ext) },
{ 0, 0xa7, HC11OP(staa_indx) }, { 0, 0xa7, &HC11OP(staa_indx) },
{ 0x18, 0xa7, HC11OP(staa_indy) }, { 0x18, 0xa7, &HC11OP(staa_indy) },
{ 0, 0xd7, HC11OP(stab_dir) }, { 0, 0xd7, &HC11OP(stab_dir) },
{ 0, 0xf7, HC11OP(stab_ext) }, { 0, 0xf7, &HC11OP(stab_ext) },
{ 0, 0xe7, HC11OP(stab_indx) }, { 0, 0xe7, &HC11OP(stab_indx) },
{ 0x18, 0xe7, HC11OP(stab_indy) }, { 0x18, 0xe7, &HC11OP(stab_indy) },
{ 0, 0xdd, HC11OP(std_dir) }, { 0, 0xdd, &HC11OP(std_dir) },
{ 0, 0xfd, HC11OP(std_ext) }, { 0, 0xfd, &HC11OP(std_ext) },
{ 0, 0xed, HC11OP(std_indx) }, { 0, 0xed, &HC11OP(std_indx) },
{ 0x18, 0xed, HC11OP(std_indy) }, { 0x18, 0xed, &HC11OP(std_indy) },
{ 0, 0x9f, HC11OP(sts_dir) }, { 0, 0x9f, &HC11OP(sts_dir) },
// { 0, 0xbf, HC11OP(sts_ext) }, // { 0, 0xbf, &HC11OP(sts_ext) },
// { 0, 0xaf, HC11OP(sts_indx) }, // { 0, 0xaf, &HC11OP(sts_indx) },
// { 0x18, 0xaf, HC11OP(sts_indy) }, // { 0x18, 0xaf, &HC11OP(sts_indy) },
{ 0, 0xdf, HC11OP(stx_dir) }, { 0, 0xdf, &HC11OP(stx_dir) },
{ 0, 0xff, HC11OP(stx_ext) }, { 0, 0xff, &HC11OP(stx_ext) },
{ 0, 0xef, HC11OP(stx_indx) }, { 0, 0xef, &HC11OP(stx_indx) },
{ 0xcd, 0xef, HC11OP(stx_indy) }, { 0xcd, 0xef, &HC11OP(stx_indy) },
{ 0x18, 0xdf, HC11OP(sty_dir) }, { 0x18, 0xdf, &HC11OP(sty_dir) },
{ 0x18, 0xff, HC11OP(sty_ext) }, { 0x18, 0xff, &HC11OP(sty_ext) },
{ 0x1a, 0xef, HC11OP(sty_indx) }, { 0x1a, 0xef, &HC11OP(sty_indx) },
{ 0x18, 0xef, HC11OP(sty_indy) }, { 0x18, 0xef, &HC11OP(sty_indy) },
{ 0, 0xcf, HC11OP(stop) }, { 0, 0xcf, &HC11OP(stop) },
{ 0, 0x80, HC11OP(suba_imm) }, { 0, 0x80, &HC11OP(suba_imm) },
{ 0, 0x90, HC11OP(suba_dir) }, { 0, 0x90, &HC11OP(suba_dir) },
{ 0, 0xb0, HC11OP(suba_ext) }, { 0, 0xb0, &HC11OP(suba_ext) },
{ 0, 0xa0, HC11OP(suba_indx) }, { 0, 0xa0, &HC11OP(suba_indx) },
{ 0x18, 0xa0, HC11OP(suba_indy) }, { 0x18, 0xa0, &HC11OP(suba_indy) },
{ 0, 0xc0, HC11OP(subb_imm) }, { 0, 0xc0, &HC11OP(subb_imm) },
{ 0, 0xd0, HC11OP(subb_dir) }, { 0, 0xd0, &HC11OP(subb_dir) },
{ 0, 0xf0, HC11OP(subb_ext) }, { 0, 0xf0, &HC11OP(subb_ext) },
{ 0, 0xe0, HC11OP(subb_indx) }, { 0, 0xe0, &HC11OP(subb_indx) },
{ 0x18, 0xe0, HC11OP(subb_indy) }, { 0x18, 0xe0, &HC11OP(subb_indy) },
{ 0, 0x83, HC11OP(subd_imm) }, { 0, 0x83, &HC11OP(subd_imm) },
{ 0, 0x93, HC11OP(subd_dir) }, { 0, 0x93, &HC11OP(subd_dir) },
{ 0, 0xb3, HC11OP(subd_ext) }, { 0, 0xb3, &HC11OP(subd_ext) },
{ 0, 0xa3, HC11OP(subd_indx) }, { 0, 0xa3, &HC11OP(subd_indx) },
{ 0x18, 0xa3, HC11OP(subd_indy) }, { 0x18, 0xa3, &HC11OP(subd_indy) },
{ 0, 0x3f, HC11OP(swi) }, { 0, 0x3f, &HC11OP(swi) },
{ 0, 0x16, HC11OP(tab) }, { 0, 0x16, &HC11OP(tab) },
{ 0, 0x06, HC11OP(tap) }, { 0, 0x06, &HC11OP(tap) },
{ 0, 0x17, HC11OP(tba) }, { 0, 0x17, &HC11OP(tba) },
{ 0, 0x00, HC11OP(test) }, { 0, 0x00, &HC11OP(test) },
{ 0, 0x07, HC11OP(tpa) }, { 0, 0x07, &HC11OP(tpa) },
{ 0, 0x4d, HC11OP(tsta) }, { 0, 0x4d, &HC11OP(tsta) },
{ 0, 0x5d, HC11OP(tstb) }, { 0, 0x5d, &HC11OP(tstb) },
{ 0, 0x7d, HC11OP(tst_ext) }, { 0, 0x7d, &HC11OP(tst_ext) },
{ 0, 0x6d, HC11OP(tst_indx) }, { 0, 0x6d, &HC11OP(tst_indx) },
{ 0x18, 0x6d, HC11OP(tst_indy) }, { 0x18, 0x6d, &HC11OP(tst_indy) },
{ 0, 0x30, HC11OP(tsx) }, { 0, 0x30, &HC11OP(tsx) },
{ 0x18, 0x30, HC11OP(tsy) }, { 0x18, 0x30, &HC11OP(tsy) },
{ 0, 0x35, HC11OP(txs) }, { 0, 0x35, &HC11OP(txs) },
{ 0x18, 0x35, HC11OP(tys) }, { 0x18, 0x35, &HC11OP(tys) },
{ 0, 0x3e, HC11OP(wai) }, { 0, 0x3e, &HC11OP(wai) },
{ 0, 0x8f, HC11OP(xgdx) }, { 0, 0x8f, &HC11OP(xgdx) },
{ 0x18, 0x8f, HC11OP(xgdy) }, { 0x18, 0x8f, &HC11OP(xgdy) },
{ 0, 0x18, HC11OP(page2) }, { 0, 0x18, &HC11OP(page2) },
{ 0, 0x1a, HC11OP(page3) }, { 0, 0x1a, &HC11OP(page3) },
{ 0, 0xcd, HC11OP(page4) }, { 0, 0xcd, &HC11OP(page4) },
}; };

576
src/emu/cpu/mc68hc11/mc68hc11.c
View File

@ -36,148 +36,112 @@ enum
static const int div_tab[4] = { 1, 4, 8, 16 }; static const int div_tab[4] = { 1, 4, 8, 16 };
struct hc11_state
const device_type MC68HC11 = &device_creator<mc68hc11_cpu_device>;
mc68hc11_cpu_device::mc68hc11_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: cpu_device(mconfig, MC68HC11, "MC68HC11", tag, owner, clock, "mc68hc11", __FILE__)
, m_program_config("program", ENDIANNESS_LITTLE, 8, 16, 0 )
, m_io_config("io", ENDIANNESS_LITTLE, 8, 8, 0)
/* defaults it to the HC11M0 version for now (I might strip this down on a later date) */
, m_has_extended_io(1)
, m_internal_ram_size(1280)
, m_init_value(0x01)
{ {
union {
struct {
#ifdef LSB_FIRST
UINT8 b;
UINT8 a;
#else
UINT8 a;
UINT8 b;
#endif
} d8;
UINT16 d16;
} d;
UINT16 ix;
UINT16 iy;
UINT16 sp;
UINT16 pc;
UINT16 ppc;
UINT8 ccr;
UINT8 adctl;
int ad_channel;
device_irq_acknowledge_callback irq_callback;
UINT8 irq_state[2];
legacy_cpu_device *device;
direct_read_data *direct;
address_space *program;
address_space *io;
int icount;
int ram_position;
int reg_position;
UINT8 *internal_ram;
int has_extended_io; // extended I/O enable flag
int internal_ram_size;
int init_value;
UINT8 wait_state,stop_state;
UINT8 tflg1, tmsk1;
UINT16 toc1;
UINT16 tcnt;
// UINT8 por;
UINT8 pr;
UINT64 frc_base;
};
INLINE hc11_state *get_safe_token(device_t *device)
{
assert(device != NULL);
assert(device->type() == MC68HC11);
return (hc11_state *)downcast<legacy_cpu_device *>(device)->token();
} }
#define HC11OP(XX) hc11_##XX
offs_t mc68hc11_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
{
extern CPU_DISASSEMBLE( hc11 );
return CPU_DISASSEMBLE_NAME(hc11)(this, buffer, pc, oprom, opram, options);
}
#define HC11OP(XX) mc68hc11_cpu_device::hc11_##XX
/*****************************************************************************/ /*****************************************************************************/
/* Internal registers */ /* Internal registers */
static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address) UINT8 mc68hc11_cpu_device::hc11_regs_r(UINT32 address)
{ {
int reg = address & 0xff; int reg = address & 0xff;
switch(reg) switch(reg)
{ {
case 0x00: /* PORTA */ case 0x00: /* PORTA */
return cpustate->io->read_byte(MC68HC11_IO_PORTA); return m_io->read_byte(MC68HC11_IO_PORTA);
case 0x01: /* DDRA */ case 0x01: /* DDRA */
return 0; return 0;
case 0x02: /* PIOC */ case 0x02: /* PIOC */
return 0; return 0;
case 0x03: /* PORTC */ case 0x03: /* PORTC */
return cpustate->io->read_byte(MC68HC11_IO_PORTC); return m_io->read_byte(MC68HC11_IO_PORTC);
case 0x04: /* PORTB */ case 0x04: /* PORTB */
return cpustate->io->read_byte(MC68HC11_IO_PORTB); return m_io->read_byte(MC68HC11_IO_PORTB);
case 0x08: /* PORTD */ case 0x08: /* PORTD */
return cpustate->io->read_byte(MC68HC11_IO_PORTD); return m_io->read_byte(MC68HC11_IO_PORTD);
case 0x09: /* DDRD */ case 0x09: /* DDRD */
return 0; return 0;
case 0x0a: /* PORTE */ case 0x0a: /* PORTE */
return cpustate->io->read_byte(MC68HC11_IO_PORTE); return m_io->read_byte(MC68HC11_IO_PORTE);
case 0x0e: /* TCNT */ case 0x0e: /* TCNT */
return cpustate->tcnt >> 8; return m_tcnt >> 8;
case 0x0f: case 0x0f:
return cpustate->tcnt & 0xff; return m_tcnt & 0xff;
case 0x16: /* TOC1 */ case 0x16: /* TOC1 */
return cpustate->toc1 >> 8; return m_toc1 >> 8;
case 0x17: case 0x17:
return cpustate->toc1 & 0xff; return m_toc1 & 0xff;
case 0x23: case 0x23:
return cpustate->tflg1; return m_tflg1;
case 0x28: /* SPCR1 */ case 0x28: /* SPCR1 */
return 0; return 0;
case 0x30: /* ADCTL */ case 0x30: /* ADCTL */
return 0x80; return 0x80;
case 0x31: /* ADR1 */ case 0x31: /* ADR1 */
{ {
if (cpustate->adctl & 0x10) if (m_adctl & 0x10)
{ {
return cpustate->io->read_byte((cpustate->adctl & 0x4) + MC68HC11_IO_AD0); return m_io->read_byte((m_adctl & 0x4) + MC68HC11_IO_AD0);
} }
else else
{ {
return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0); return m_io->read_byte((m_adctl & 0x7) + MC68HC11_IO_AD0);
} }
} }
case 0x32: /* ADR2 */ case 0x32: /* ADR2 */
{ {
if (cpustate->adctl & 0x10) if (m_adctl & 0x10)
{ {
return cpustate->io->read_byte((cpustate->adctl & 0x4) + MC68HC11_IO_AD1); return m_io->read_byte((m_adctl & 0x4) + MC68HC11_IO_AD1);
} }
else else
{ {
return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0); return m_io->read_byte((m_adctl & 0x7) + MC68HC11_IO_AD0);
} }
} }
case 0x33: /* ADR3 */ case 0x33: /* ADR3 */
{ {
if (cpustate->adctl & 0x10) if (m_adctl & 0x10)
{ {
return cpustate->io->read_byte((cpustate->adctl & 0x4) + MC68HC11_IO_AD2); return m_io->read_byte((m_adctl & 0x4) + MC68HC11_IO_AD2);
} }
else else
{ {
return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0); return m_io->read_byte((m_adctl & 0x7) + MC68HC11_IO_AD0);
} }
} }
case 0x34: /* ADR4 */ case 0x34: /* ADR4 */
{ {
if (cpustate->adctl & 0x10) if (m_adctl & 0x10)
{ {
return cpustate->io->read_byte((cpustate->adctl & 0x4) + MC68HC11_IO_AD3); return m_io->read_byte((m_adctl & 0x4) + MC68HC11_IO_AD3);
} }
else else
{ {
return cpustate->io->read_byte((cpustate->adctl & 0x7) + MC68HC11_IO_AD0); return m_io->read_byte((m_adctl & 0x7) + MC68HC11_IO_AD0);
} }
} }
case 0x38: /* OPT2 */ case 0x38: /* OPT2 */
@ -193,9 +157,9 @@ static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address)
case 0x74: /* SCSR1 */ case 0x74: /* SCSR1 */
return 0x40; return 0x40;
case 0x7c: /* PORTH */ case 0x7c: /* PORTH */
return cpustate->io->read_byte(MC68HC11_IO_PORTH); return m_io->read_byte(MC68HC11_IO_PORTH);
case 0x7e: /* PORTG */ case 0x7e: /* PORTG */
return cpustate->io->read_byte(MC68HC11_IO_PORTG); return m_io->read_byte(MC68HC11_IO_PORTG);
case 0x7f: /* DDRG */ case 0x7f: /* DDRG */
return 0; return 0;
@ -204,7 +168,7 @@ static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address)
case 0x89: /* SPSR2 */ case 0x89: /* SPSR2 */
return 0x80; return 0x80;
case 0x8a: /* SPDR2 */ case 0x8a: /* SPDR2 */
return cpustate->io->read_byte(MC68HC11_IO_SPI2_DATA); return m_io->read_byte(MC68HC11_IO_SPI2_DATA);
case 0x8b: /* OPT4 */ case 0x8b: /* OPT4 */
return 0; return 0;
@ -214,32 +178,32 @@ static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address)
return 0; // Dummy return 0; // Dummy
} }
static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value) void mc68hc11_cpu_device::hc11_regs_w(UINT32 address, UINT8 value)
{ {
int reg = address & 0xff; int reg = address & 0xff;
switch(reg) switch(reg)
{ {
case 0x00: /* PORTA */ case 0x00: /* PORTA */
cpustate->io->write_byte(MC68HC11_IO_PORTA, value); m_io->write_byte(MC68HC11_IO_PORTA, value);
return; return;
case 0x01: /* DDRA */ case 0x01: /* DDRA */
//mame_printf_debug("HC11: ddra = %02X\n", value); //mame_printf_debug("HC11: ddra = %02X\n", value);
return; return;
case 0x03: /* PORTC */ case 0x03: /* PORTC */
cpustate->io->write_byte(MC68HC11_IO_PORTC, value); m_io->write_byte(MC68HC11_IO_PORTC, value);
return; return;
case 0x04: /* PORTC */ case 0x04: /* PORTC */
cpustate->io->write_byte(MC68HC11_IO_PORTB, value); m_io->write_byte(MC68HC11_IO_PORTB, value);
return; return;
case 0x08: /* PORTD */ case 0x08: /* PORTD */
cpustate->io->write_byte(MC68HC11_IO_PORTD, value); //mask & 0x3f? m_io->write_byte(MC68HC11_IO_PORTD, value); //mask & 0x3f?
return; return;
case 0x09: /* DDRD */ case 0x09: /* DDRD */
//mame_printf_debug("HC11: ddrd = %02X\n", value); //mame_printf_debug("HC11: ddrd = %02X\n", value);
return; return;
case 0x0a: /* PORTE */ case 0x0a: /* PORTE */
cpustate->io->write_byte(MC68HC11_IO_PORTE, value); m_io->write_byte(MC68HC11_IO_PORTE, value);
return; return;
case 0x0e: /* TCNT */ case 0x0e: /* TCNT */
case 0x0f: case 0x0f:
@ -247,24 +211,24 @@ static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value)
return; return;
case 0x16: /* TOC1 */ case 0x16: /* TOC1 */
/* TODO: inhibit for one bus cycle */ /* TODO: inhibit for one bus cycle */
cpustate->toc1 = (value << 8) | (cpustate->toc1 & 0xff); m_toc1 = (value << 8) | (m_toc1 & 0xff);
return; return;
case 0x17: case 0x17:
cpustate->toc1 = (value & 0xff) | (cpustate->toc1 & 0xff00); m_toc1 = (value & 0xff) | (m_toc1 & 0xff00);
return; return;
case 0x22: /* TMSK1 */ case 0x22: /* TMSK1 */
cpustate->tmsk1 = value; m_tmsk1 = value;
return; return;
case 0x23: case 0x23:
cpustate->tflg1 &= ~value; m_tflg1 &= ~value;
return; return;
case 0x24: /* TMSK2 */ case 0x24: /* TMSK2 */
cpustate->pr = value & 3; m_pr = value & 3;
return; return;
case 0x28: /* SPCR1 */ case 0x28: /* SPCR1 */
return; return;
case 0x30: /* ADCTL */ case 0x30: /* ADCTL */
cpustate->adctl = value; m_adctl = value;
return; return;
case 0x38: /* OPT2 */ case 0x38: /* OPT2 */
return; return;
@ -279,11 +243,11 @@ static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value)
int ram_page = (value >> 4) & 0xf; int ram_page = (value >> 4) & 0xf;
if (reg_page == ram_page) { if (reg_page == ram_page) {
cpustate->reg_position = reg_page << 12; m_reg_position = reg_page << 12;
cpustate->ram_position = (ram_page << 12) + ((cpustate->has_extended_io) ? 0x100 : 0x80); m_ram_position = (ram_page << 12) + ((m_has_extended_io) ? 0x100 : 0x80);
} else { } else {
cpustate->reg_position = reg_page << 12; m_reg_position = reg_page << 12;
cpustate->ram_position = ram_page << 12; m_ram_position = ram_page << 12;
} }
return; return;
} }
@ -302,16 +266,16 @@ static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value)
case 0x77: /* SCDRL */ case 0x77: /* SCDRL */
return; return;
case 0x7c: /* PORTH */ case 0x7c: /* PORTH */
cpustate->io->write_byte(MC68HC11_IO_PORTH, value); m_io->write_byte(MC68HC11_IO_PORTH, value);
return; return;
case 0x7d: /* DDRH */ case 0x7d: /* DDRH */
//mame_printf_debug("HC11: ddrh = %02X at %04X\n", value, cpustate->pc); //mame_printf_debug("HC11: ddrh = %02X at %04X\n", value, m_pc);
return; return;
case 0x7e: /* PORTG */ case 0x7e: /* PORTG */
cpustate->io->write_byte(MC68HC11_IO_PORTG, value); m_io->write_byte(MC68HC11_IO_PORTG, value);
return; return;
case 0x7f: /* DDRG */ case 0x7f: /* DDRG */
//mame_printf_debug("HC11: ddrg = %02X at %04X\n", value, cpustate->pc); //mame_printf_debug("HC11: ddrg = %02X at %04X\n", value, m_pc);
return; return;
case 0x88: /* SPCR2 */ case 0x88: /* SPCR2 */
@ -319,7 +283,7 @@ static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value)
case 0x89: /* SPSR2 */ case 0x89: /* SPSR2 */
return; return;
case 0x8a: /* SPDR2 */ case 0x8a: /* SPDR2 */
cpustate->io->write_byte(MC68HC11_IO_SPI2_DATA, value); m_io->write_byte(MC68HC11_IO_SPI2_DATA, value);
return; return;
case 0x8b: /* OPT4 */ case 0x8b: /* OPT4 */
@ -332,81 +296,74 @@ static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value)
/*****************************************************************************/ /*****************************************************************************/
INLINE UINT8 FETCH(hc11_state *cpustate) UINT8 mc68hc11_cpu_device::FETCH()
{ {
return cpustate->direct->read_decrypted_byte(cpustate->pc++); return m_direct->read_decrypted_byte(m_pc++);
} }
INLINE UINT16 FETCH16(hc11_state *cpustate) UINT16 mc68hc11_cpu_device::FETCH16()
{ {
UINT16 w; UINT16 w;
w = (cpustate->direct->read_decrypted_byte(cpustate->pc) << 8) | (cpustate->direct->read_decrypted_byte(cpustate->pc+1)); w = (m_direct->read_decrypted_byte(m_pc) << 8) | (m_direct->read_decrypted_byte(m_pc+1));
cpustate->pc += 2; m_pc += 2;
return w; return w;
} }
INLINE UINT8 READ8(hc11_state *cpustate, UINT32 address) UINT8 mc68hc11_cpu_device::READ8(UINT32 address)
{ {
if(address >= cpustate->reg_position && address < cpustate->reg_position+(cpustate->has_extended_io ? 0x100 : 0x40)) if(address >= m_reg_position && address < m_reg_position+(m_has_extended_io ? 0x100 : 0x40))
{ {
return hc11_regs_r(cpustate, address); return hc11_regs_r(address);
} }
else if(address >= cpustate->ram_position && address < cpustate->ram_position+cpustate->internal_ram_size) else if(address >= m_ram_position && address < m_ram_position+m_internal_ram_size)
{ {
return cpustate->internal_ram[address-cpustate->ram_position]; return m_internal_ram[address-m_ram_position];
} }
return cpustate->program->read_byte(address); return m_program->read_byte(address);
} }
INLINE void WRITE8(hc11_state *cpustate, UINT32 address, UINT8 value) void mc68hc11_cpu_device::WRITE8(UINT32 address, UINT8 value)
{ {
if(address >= cpustate->reg_position && address < cpustate->reg_position+(cpustate->has_extended_io ? 0x100 : 0x40)) if(address >= m_reg_position && address < m_reg_position+(m_has_extended_io ? 0x100 : 0x40))
{ {
hc11_regs_w(cpustate, address, value); hc11_regs_w(address, value);
return; return;
} }
else if(address >= cpustate->ram_position && address < cpustate->ram_position+cpustate->internal_ram_size) else if(address >= m_ram_position && address < m_ram_position+m_internal_ram_size)
{ {
cpustate->internal_ram[address-cpustate->ram_position] = value; m_internal_ram[address-m_ram_position] = value;
return; return;
} }
cpustate->program->write_byte(address, value); m_program->write_byte(address, value);
} }
INLINE UINT16 READ16(hc11_state *cpustate, UINT32 address) UINT16 mc68hc11_cpu_device::READ16(UINT32 address)
{ {
return (READ8(cpustate, address) << 8) | (READ8(cpustate, address+1)); return (READ8(address) << 8) | (READ8(address+1));
} }
INLINE void WRITE16(hc11_state *cpustate, UINT32 address, UINT16 value) void mc68hc11_cpu_device::WRITE16(UINT32 address, UINT16 value)
{ {
WRITE8(cpustate, address+0, (value >> 8) & 0xff); WRITE8(address+0, (value >> 8) & 0xff);
WRITE8(cpustate, address+1, (value >> 0) & 0xff); WRITE8(address+1, (value >> 0) & 0xff);
} }
/*****************************************************************************/ /*****************************************************************************/
static void (*hc11_optable[256])(hc11_state *cpustate);
static void (*hc11_optable_page2[256])(hc11_state *cpustate);
static void (*hc11_optable_page3[256])(hc11_state *cpustate);
static void (*hc11_optable_page4[256])(hc11_state *cpustate);
#include "hc11ops.c" #include "hc11ops.c"
#include "hc11ops.h" #include "hc11ops.h"
static CPU_INIT( hc11 ) void mc68hc11_cpu_device::device_start()
{ {
hc11_state *cpustate = get_safe_token(device);
int i; int i;
const hc11_config *conf = (const hc11_config *)device->static_config();
/* clear the opcode tables */ /* clear the opcode tables */
for(i=0; i < 256; i++) { for(i=0; i < 256; i++) {
hc11_optable[i] = HC11OP(invalid); hc11_optable[i] = &HC11OP(invalid);
hc11_optable_page2[i] = HC11OP(invalid); hc11_optable_page2[i] = &HC11OP(invalid);
hc11_optable_page3[i] = HC11OP(invalid); hc11_optable_page3[i] = &HC11OP(invalid);
hc11_optable_page4[i] = HC11OP(invalid); hc11_optable_page4[i] = &HC11OP(invalid);
} }
/* fill the opcode tables */ /* fill the opcode tables */
for(i=0; i < sizeof(hc11_opcode_list)/sizeof(hc11_opcode_list_struct); i++) for(i=0; i < sizeof(hc11_opcode_list)/sizeof(hc11_opcode_list_struct); i++)
@ -428,74 +385,98 @@ static CPU_INIT( hc11 )
} }
} }
if(conf) m_internal_ram = auto_alloc_array(machine(), UINT8, m_internal_ram_size);
{
cpustate->has_extended_io = conf->has_extended_io;
cpustate->internal_ram_size = conf->internal_ram_size;
cpustate->init_value = conf->init_value;
}
else
{
/* defaults it to the HC11M0 version for now (I might strip this down on a later date) */
cpustate->has_extended_io = 1;
cpustate->internal_ram_size = 1280;
cpustate->init_value = 0x01;
}
cpustate->internal_ram = auto_alloc_array(device->machine(), UINT8, cpustate->internal_ram_size); m_program = &space(AS_PROGRAM);
m_direct = &m_program->direct();
m_io = &space(AS_IO);
cpustate->irq_callback = irqcallback; save_item(NAME(m_pc));
cpustate->device = device; save_item(NAME(m_ix));
cpustate->program = &device->space(AS_PROGRAM); save_item(NAME(m_iy));
cpustate->direct = &cpustate->program->direct(); save_item(NAME(m_sp));
cpustate->io = &device->space(AS_IO); save_item(NAME(m_ppc));
save_item(NAME(m_ccr));
save_item(NAME(m_d.d8.a));
save_item(NAME(m_d.d8.b));
save_item(NAME(m_adctl));
save_item(NAME(m_ad_channel));
save_item(NAME(m_ram_position));
save_item(NAME(m_reg_position));
save_item(NAME(m_irq_state));
save_item(NAME(m_icount));
save_item(NAME(m_has_extended_io));
save_item(NAME(m_internal_ram_size));
save_item(NAME(m_init_value));
save_pointer(NAME(m_internal_ram),m_internal_ram_size);
save_item(NAME(m_wait_state));
save_item(NAME(m_stop_state));
save_item(NAME(m_tflg1));
save_item(NAME(m_tmsk1));
save_item(NAME(m_toc1));
save_item(NAME(m_tcnt));
// save_item(NAME(m_por));
save_item(NAME(m_pr));
save_item(NAME(m_frc_base));
device->save_item(NAME(cpustate->pc)); state_add( HC11_PC, "PC", m_pc).formatstr("%04X");
device->save_item(NAME(cpustate->ix)); state_add( HC11_SP, "SP", m_sp).formatstr("%04X");
device->save_item(NAME(cpustate->iy)); state_add( HC11_A, "A", m_d.d8.a).formatstr("%02X");
device->save_item(NAME(cpustate->sp)); state_add( HC11_B, "B", m_d.d8.b).formatstr("%02X");
device->save_item(NAME(cpustate->ppc)); state_add( HC11_IX, "IX", m_ix).formatstr("%04X");
device->save_item(NAME(cpustate->ccr)); state_add( HC11_IY, "IY", m_iy).formatstr("%04X");
device->save_item(NAME(cpustate->d.d8.a));
device->save_item(NAME(cpustate->d.d8.b)); state_add( STATE_GENPC, "GENPC", m_pc).noshow();
device->save_item(NAME(cpustate->adctl)); state_add( STATE_GENFLAGS, "GENFLAGS", m_ccr).formatstr("%8s").noshow();
device->save_item(NAME(cpustate->ad_channel));
device->save_item(NAME(cpustate->ram_position)); m_d.d16 = 0;
device->save_item(NAME(cpustate->reg_position)); m_ix = 0;
device->save_item(NAME(cpustate->irq_state)); m_iy = 0;
device->save_item(NAME(cpustate->icount)); m_sp = 0;
device->save_item(NAME(cpustate->has_extended_io)); m_ppc = 0;
device->save_item(NAME(cpustate->internal_ram_size)); m_adctl = 0;
device->save_item(NAME(cpustate->init_value)); m_ad_channel = 0;
device->save_pointer(NAME(cpustate->internal_ram),cpustate->internal_ram_size); m_irq_state[0] = m_irq_state[1] = 0;
device->save_item(NAME(cpustate->wait_state)); m_ram_position = 0;
device->save_item(NAME(cpustate->stop_state)); m_reg_position = 0;
device->save_item(NAME(cpustate->tflg1)); m_tflg1 = 0;
device->save_item(NAME(cpustate->tmsk1)); m_tmsk1 = 0;
device->save_item(NAME(cpustate->toc1));
device->save_item(NAME(cpustate->tcnt)); m_icountptr = &m_icount;
// device->save_item(NAME(cpustate->por));
device->save_item(NAME(cpustate->pr));
device->save_item(NAME(cpustate->frc_base));
} }
static CPU_RESET( hc11 )
void mc68hc11_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
{ {
hc11_state *cpustate = get_safe_token(device); switch (entry.index())
cpustate->pc = READ16(cpustate, 0xfffe); {
cpustate->wait_state = 0; case STATE_GENFLAGS:
cpustate->stop_state = 0; string.printf("%c%c%c%c%c%c%c%c",
cpustate->ccr = CC_X | CC_I | CC_S; (m_ccr & CC_S) ? 'S' : '.',
hc11_regs_w(cpustate,0x3d,cpustate->init_value); (m_ccr & CC_X) ? 'X' : '.',
cpustate->toc1 = 0xffff; (m_ccr & CC_H) ? 'H' : '.',
cpustate->tcnt = 0xffff; (m_ccr & CC_I) ? 'I' : '.',
// cpustate->por = 1; // for first timer overflow / compare stuff (m_ccr & CC_N) ? 'N' : '.',
cpustate->pr = 3; // timer prescale (m_ccr & CC_Z) ? 'Z' : '.',
cpustate->frc_base = 0; (m_ccr & CC_V) ? 'V' : '.',
(m_ccr & CC_C) ? 'C' : '.');
break;
}
} }
static CPU_EXIT( hc11 )
void mc68hc11_cpu_device::device_reset()
{ {
m_pc = READ16(0xfffe);
m_wait_state = 0;
m_stop_state = 0;
m_ccr = CC_X | CC_I | CC_S;
hc11_regs_w(0x3d,m_init_value);
m_toc1 = 0xffff;
m_tcnt = 0xffff;
// m_por = 1; // for first timer overflow / compare stuff
m_pr = 3; // timer prescale
m_frc_base = 0;
} }
/* /*
@ -523,200 +504,95 @@ IRQ table vectors:
0xfffe: RESET 0xfffe: RESET
*/ */
static void check_irq_lines(hc11_state *cpustate) void mc68hc11_cpu_device::check_irq_lines()
{ {
if( cpustate->irq_state[MC68HC11_IRQ_LINE]!=CLEAR_LINE && (!(cpustate->ccr & CC_I)) ) if( m_irq_state[MC68HC11_IRQ_LINE]!=CLEAR_LINE && (!(m_ccr & CC_I)) )
{ {
UINT16 pc_vector; UINT16 pc_vector;
if(cpustate->wait_state == 0) if(m_wait_state == 0)
{ {
PUSH16(cpustate, cpustate->pc); PUSH16(m_pc);
PUSH16(cpustate, cpustate->iy); PUSH16(m_iy);
PUSH16(cpustate, cpustate->ix); PUSH16(m_ix);
PUSH8(cpustate, REG_A); PUSH8(REG_A);
PUSH8(cpustate, REG_B); PUSH8(REG_B);
PUSH8(cpustate, cpustate->ccr); PUSH8(m_ccr);
} }
pc_vector = READ16(cpustate, 0xfff2); pc_vector = READ16(0xfff2);
SET_PC(cpustate, pc_vector); SET_PC(pc_vector);
cpustate->ccr |= CC_I; //irq taken, mask the flag m_ccr |= CC_I; //irq taken, mask the flag
if(cpustate->wait_state == 1) { cpustate->wait_state = 2; } if(m_wait_state == 1) { m_wait_state = 2; }
if(cpustate->stop_state == 1) { cpustate->stop_state = 2; } if(m_stop_state == 1) { m_stop_state = 2; }
(void)(*cpustate->irq_callback)(cpustate->device, MC68HC11_IRQ_LINE); standard_irq_callback(MC68HC11_IRQ_LINE);
} }
/* check timers here */ /* check timers here */
{ {
int divider = div_tab[cpustate->pr & 3]; int divider = div_tab[m_pr & 3];
UINT64 cur_time = cpustate->device->total_cycles(); UINT64 cur_time = total_cycles();
UINT32 add = (cur_time - cpustate->frc_base) / divider; UINT32 add = (cur_time - m_frc_base) / divider;
if (add > 0) if (add > 0)
{ {
for(UINT32 i=0;i<add;i++) for(UINT32 i=0;i<add;i++)
{ {
cpustate->tcnt++; m_tcnt++;
if(cpustate->tcnt == cpustate->toc1) if(m_tcnt == m_toc1)
{ {
cpustate->tflg1 |= 0x80; m_tflg1 |= 0x80;
cpustate->irq_state[MC68HC11_TOC1_LINE] = ASSERT_LINE; m_irq_state[MC68HC11_TOC1_LINE] = ASSERT_LINE;
} }
} }
cpustate->frc_base = cur_time; m_frc_base = cur_time;
} }
} }
if( cpustate->irq_state[MC68HC11_TOC1_LINE]!=CLEAR_LINE && (!(cpustate->ccr & CC_I)) && cpustate->tmsk1 & 0x80) if( m_irq_state[MC68HC11_TOC1_LINE]!=CLEAR_LINE && (!(m_ccr & CC_I)) && m_tmsk1 & 0x80)
{ {
UINT16 pc_vector; UINT16 pc_vector;
if(cpustate->wait_state == 0) if(m_wait_state == 0)
{ {
PUSH16(cpustate, cpustate->pc); PUSH16(m_pc);
PUSH16(cpustate, cpustate->iy); PUSH16(m_iy);
PUSH16(cpustate, cpustate->ix); PUSH16(m_ix);
PUSH8(cpustate, REG_A); PUSH8(REG_A);
PUSH8(cpustate, REG_B); PUSH8(REG_B);
PUSH8(cpustate, cpustate->ccr); PUSH8(m_ccr);
} }
pc_vector = READ16(cpustate, 0xffe8); pc_vector = READ16(0xffe8);
SET_PC(cpustate, pc_vector); SET_PC(pc_vector);
cpustate->ccr |= CC_I; //irq taken, mask the flag m_ccr |= CC_I; //irq taken, mask the flag
if(cpustate->wait_state == 1) { cpustate->wait_state = 2; } if(m_wait_state == 1) { m_wait_state = 2; }
if(cpustate->stop_state == 1) { cpustate->stop_state = 2; } if(m_stop_state == 1) { m_stop_state = 2; }
(void)(*cpustate->irq_callback)(cpustate->device, MC68HC11_TOC1_LINE); standard_irq_callback(MC68HC11_TOC1_LINE);
cpustate->irq_state[MC68HC11_TOC1_LINE] = CLEAR_LINE; // auto-ack irq m_irq_state[MC68HC11_TOC1_LINE] = CLEAR_LINE; // auto-ack irq
} }
} }
static void set_irq_line(hc11_state *cpustate, int irqline, int state) void mc68hc11_cpu_device::execute_set_input(int inputnum, int state)
{ {
cpustate->irq_state[irqline] = state; m_irq_state[inputnum] = state;
if (state == CLEAR_LINE) return; if (state == CLEAR_LINE) return;
check_irq_lines(cpustate); check_irq_lines();
} }
static CPU_EXECUTE( hc11 ) void mc68hc11_cpu_device::execute_run()
{ {
hc11_state *cpustate = get_safe_token(device); while(m_icount > 0)
while(cpustate->icount > 0)
{ {
UINT8 op; UINT8 op;
check_irq_lines(cpustate); check_irq_lines();
cpustate->ppc = cpustate->pc; m_ppc = m_pc;
debugger_instruction_hook(device, cpustate->pc); debugger_instruction_hook(this, m_pc);
op = FETCH(cpustate); op = FETCH();
hc11_optable[op](cpustate); (this->*hc11_optable[op])();
} }
} }
/*****************************************************************************/
static CPU_SET_INFO( mc68hc11 )
{
hc11_state *cpustate = get_safe_token(device);
switch (state)
{
case CPUINFO_INT_INPUT_STATE + MC68HC11_IRQ_LINE: set_irq_line(cpustate, MC68HC11_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + MC68HC11_TOC1_LINE: set_irq_line(cpustate, MC68HC11_TOC1_LINE, info->i); break;
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_PC: cpustate->pc = info->i; break;
case CPUINFO_INT_REGISTER + HC11_PC: cpustate->pc = info->i; break;
case CPUINFO_INT_REGISTER + HC11_SP: cpustate->sp = info->i; break;
case CPUINFO_INT_REGISTER + HC11_A: cpustate->d.d8.a = info->i; break;
case CPUINFO_INT_REGISTER + HC11_B: cpustate->d.d8.b = info->i; break;
case CPUINFO_INT_REGISTER + HC11_IX: cpustate->ix = info->i; break;
case CPUINFO_INT_REGISTER + HC11_IY: cpustate->iy = info->i; break;
}
}
CPU_GET_INFO( mc68hc11 )
{
hc11_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
switch(state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hc11_state); break;
case CPUINFO_INT_INPUT_LINES: info->i = 1; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 5; break;
case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
case CPUINFO_INT_MAX_CYCLES: info->i = 41; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + MC68HC11_IRQ_LINE: info->i = cpustate->irq_state[MC68HC11_IRQ_LINE]; break;
case CPUINFO_INT_INPUT_STATE + MC68HC11_TOC1_LINE: info->i = cpustate->irq_state[MC68HC11_TOC1_LINE]; break;
case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;
case CPUINFO_INT_PC: /* intentional fallthrough */
case CPUINFO_INT_REGISTER + HC11_PC: info->i = cpustate->pc; break;
case CPUINFO_INT_REGISTER + HC11_SP: info->i = cpustate->sp; break;
case CPUINFO_INT_REGISTER + HC11_A: info->i = cpustate->d.d8.a; break;
case CPUINFO_INT_REGISTER + HC11_B: info->i = cpustate->d.d8.b; break;
case CPUINFO_INT_REGISTER + HC11_IX: info->i = cpustate->ix; break;
case CPUINFO_INT_REGISTER + HC11_IY: info->i = cpustate->iy; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mc68hc11); break;
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(hc11); break;
case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(hc11); break;
case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(hc11); break;
case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(hc11); break;
case CPUINFO_FCT_BURN: info->burn = NULL; break;
case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(hc11); break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "MC68HC11"); break;
case CPUINFO_STR_SHORTNAME: strcpy(info->s, "mc68hc11"); break;
case CPUINFO_STR_FAMILY: strcpy(info->s, "Motorola MC68HC11"); break;
case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Ville Linde & Angelo Salese"); break;
case CPUINFO_STR_FLAGS:
sprintf(info->s, "%c%c%c%c%c%c%c%c",
(cpustate->ccr & CC_S) ? 'S' : '.',
(cpustate->ccr & CC_X) ? 'X' : '.',
(cpustate->ccr & CC_H) ? 'H' : '.',
(cpustate->ccr & CC_I) ? 'I' : '.',
(cpustate->ccr & CC_N) ? 'N' : '.',
(cpustate->ccr & CC_Z) ? 'Z' : '.',
(cpustate->ccr & CC_V) ? 'V' : '.',
(cpustate->ccr & CC_C) ? 'C' : '.');
break;
case CPUINFO_STR_REGISTER + HC11_PC: sprintf(info->s, "PC: %04X", cpustate->pc); break;
case CPUINFO_STR_REGISTER + HC11_SP: sprintf(info->s, "SP: %04X", cpustate->sp); break;
case CPUINFO_STR_REGISTER + HC11_A: sprintf(info->s, "A: %02X", cpustate->d.d8.a); break;
case CPUINFO_STR_REGISTER + HC11_B: sprintf(info->s, "B: %02X", cpustate->d.d8.b); break;
case CPUINFO_STR_REGISTER + HC11_IX: sprintf(info->s, "IX: %04X", cpustate->ix); break;
case CPUINFO_STR_REGISTER + HC11_IY: sprintf(info->s, "IY: %04X", cpustate->iy); break;
}
}
DEFINE_LEGACY_CPU_DEVICE(MC68HC11, mc68hc11);

417
src/emu/cpu/mc68hc11/mc68hc11.h
View File

@ -4,11 +4,6 @@
#define __MC68HC11_H__ #define __MC68HC11_H__
CPU_DISASSEMBLE( hc11 );
DECLARE_LEGACY_CPU_DEVICE(MC68HC11, mc68hc11);
#define MC68HC11_IO_PORTA 0x00 #define MC68HC11_IO_PORTA 0x00
#define MC68HC11_IO_PORTB 0x01 #define MC68HC11_IO_PORTB 0x01
#define MC68HC11_IO_PORTC 0x02 #define MC68HC11_IO_PORTC 0x02
@ -31,11 +26,415 @@ DECLARE_LEGACY_CPU_DEVICE(MC68HC11, mc68hc11);
#define MC68HC11_IRQ_LINE 0 #define MC68HC11_IRQ_LINE 0
#define MC68HC11_TOC1_LINE 1 #define MC68HC11_TOC1_LINE 1
struct hc11_config
extern const device_type MC68HC11;
#define MCFG_MC68HC11_CONFIG(_has_extended_io, _internal_ram_size, _init_value) \
mc68hc11_cpu_device::set_has_extended_io(*device, _has_extended_io); \
mc68hc11_cpu_device::set_internal_ram_size(*device, _internal_ram_size); \
mc68hc11_cpu_device::set_init_value(*device, _init_value);
class mc68hc11_cpu_device : public cpu_device
{ {
int has_extended_io; // I/O enable flag public:
int internal_ram_size; // construction/destruction
int init_value; // default value for INIT register mc68hc11_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// I/O enable flag
static void set_has_extended_io(device_t &device, int has_extended_io) { downcast<mc68hc11_cpu_device &>(device).m_has_extended_io = has_extended_io; }
static void set_internal_ram_size(device_t &device, int internal_ram_size) { downcast<mc68hc11_cpu_device &>(device).m_internal_ram_size = internal_ram_size; }
// default value for INIT register
static void set_init_value(device_t &device, int init_value) { downcast<mc68hc11_cpu_device &>(device).m_init_value = init_value; }
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
// device_execute_interface overrides
virtual UINT32 execute_min_cycles() const { return 1; }
virtual UINT32 execute_max_cycles() const { return 41; }
virtual UINT32 execute_input_lines() const { return 2; }
virtual UINT32 execute_default_irq_vector() const { return 0; }
virtual void execute_run();
virtual void execute_set_input(int inputnum, int state);
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
{
return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL );
}
// device_state_interface overrides
void state_string_export(const device_state_entry &entry, astring &string);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
virtual UINT32 disasm_max_opcode_bytes() const { return 5; }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
private:
address_space_config m_program_config;
address_space_config m_io_config;
union {
struct {
#ifdef LSB_FIRST
UINT8 b;
UINT8 a;
#else
UINT8 a;
UINT8 b;
#endif
} d8;
UINT16 d16;
} m_d;
UINT16 m_ix;
UINT16 m_iy;
UINT16 m_sp;
UINT16 m_pc;
UINT16 m_ppc;
UINT8 m_ccr;
UINT8 m_adctl;
int m_ad_channel;
UINT8 m_irq_state[2];
direct_read_data *m_direct;
address_space *m_program;
address_space *m_io;
int m_icount;
int m_ram_position;
int m_reg_position;
UINT8 *m_internal_ram;
int m_has_extended_io; // extended I/O enable flag
int m_internal_ram_size;
int m_init_value;
UINT8 m_wait_state;
UINT8 m_stop_state;
UINT8 m_tflg1;
UINT8 m_tmsk1;
UINT16 m_toc1;
UINT16 m_tcnt;
// UINT8 m_por;
UINT8 m_pr;
UINT64 m_frc_base;
typedef void (mc68hc11_cpu_device::*ophandler)();
struct hc11_opcode_list_struct
{
int page;
int opcode;
ophandler handler;
};
static const hc11_opcode_list_struct hc11_opcode_list[];
ophandler hc11_optable[256];
ophandler hc11_optable_page2[256];
ophandler hc11_optable_page3[256];
ophandler hc11_optable_page4[256];
UINT8 hc11_regs_r(UINT32 address);
void hc11_regs_w(UINT32 address, UINT8 value);
UINT8 FETCH();
UINT16 FETCH16();
UINT8 READ8(UINT32 address);
void WRITE8(UINT32 address, UINT8 value);
UINT16 READ16(UINT32 address);
void WRITE16(UINT32 address, UINT16 value);
void CYCLES(int cycles);
void SET_PC(int pc);
void PUSH8(UINT8 value);
void PUSH16(UINT16 value);
UINT8 POP8();
UINT16 POP16();
void hc11_aba();
void hc11_abx();
void hc11_aby();
void hc11_adca_imm();
void hc11_adca_dir();
void hc11_adca_ext();
void hc11_adca_indx();
void hc11_adca_indy();
void hc11_adcb_imm();
void hc11_adcb_dir();
void hc11_adcb_ext();
void hc11_adcb_indx();
void hc11_adcb_indy();
void hc11_adda_imm();
void hc11_adda_dir();
void hc11_adda_ext();
void hc11_adda_indx();
void hc11_adda_indy();
void hc11_addb_imm();
void hc11_addb_dir();
void hc11_addb_ext();
void hc11_addb_indx();
void hc11_addb_indy();
void hc11_addd_imm();
void hc11_addd_dir();
void hc11_addd_ext();
void hc11_addd_indx();
void hc11_addd_indy();
void hc11_anda_imm();
void hc11_anda_dir();
void hc11_anda_ext();
void hc11_anda_indx();
void hc11_anda_indy();
void hc11_andb_imm();
void hc11_andb_dir();
void hc11_andb_ext();
void hc11_andb_indx();
void hc11_andb_indy();
void hc11_asla();
void hc11_aslb();
void hc11_asl_ext();
void hc11_bita_imm();
void hc11_bita_dir();
void hc11_bita_ext();
void hc11_bita_indx();
void hc11_bita_indy();
void hc11_bitb_imm();
void hc11_bitb_dir();
void hc11_bitb_ext();
void hc11_bitb_indx();
void hc11_bitb_indy();
void hc11_bcc();
void hc11_bclr_dir();
void hc11_bclr_indx();
void hc11_bcs();
void hc11_beq();
void hc11_bhi();
void hc11_bne();
void hc11_ble();
void hc11_bls();
void hc11_bmi();
void hc11_bpl();
void hc11_bra();
void hc11_brclr_dir();
void hc11_brclr_indx();
void hc11_brset_dir();
void hc11_brset_indx();
void hc11_brn();
void hc11_bset_dir();
void hc11_bset_indx();
void hc11_bsr();
void hc11_bvc();
void hc11_bvs();
void hc11_cba();
void hc11_clc();
void hc11_cli();
void hc11_clra();
void hc11_clrb();
void hc11_clr_ext();
void hc11_clr_indx();
void hc11_clr_indy();
void hc11_clv();
void hc11_cmpa_imm();
void hc11_cmpa_dir();
void hc11_cmpa_ext();
void hc11_cmpa_indx();
void hc11_cmpa_indy();
void hc11_cmpb_imm();
void hc11_cmpb_dir();
void hc11_cmpb_ext();
void hc11_cmpb_indx();
void hc11_cmpb_indy();
void hc11_coma();
void hc11_comb();
void hc11_cpd_imm();
void hc11_cpd_dir();
void hc11_cpd_ext();
void hc11_cpd_indx();
void hc11_cpd_indy();
void hc11_cpx_imm();
void hc11_cpx_dir();
void hc11_cpx_ext();
void hc11_cpx_indx();
void hc11_cpx_indy();
void hc11_cpy_imm();
void hc11_cpy_dir();
void hc11_cpy_ext();
void hc11_cpy_indx();
void hc11_cpy_indy();
void hc11_deca();
void hc11_decb();
void hc11_dec_ext();
void hc11_dec_indx();
void hc11_dec_indy();
void hc11_dex();
void hc11_dey();
void hc11_eora_imm();
void hc11_eora_dir();
void hc11_eora_ext();
void hc11_eora_indx();
void hc11_eora_indy();
void hc11_eorb_imm();
void hc11_eorb_dir();
void hc11_eorb_ext();
void hc11_eorb_indx();
void hc11_eorb_indy();
void hc11_idiv();
void hc11_inca();
void hc11_incb();
void hc11_inc_ext();
void hc11_inc_indx();
void hc11_inc_indy();
void hc11_inx();
void hc11_iny();
void hc11_jmp_indx();
void hc11_jmp_indy();
void hc11_jmp_ext();
void hc11_jsr_dir();
void hc11_jsr_ext();
void hc11_jsr_indx();
void hc11_jsr_indy();
void hc11_ldaa_imm();
void hc11_ldaa_dir();
void hc11_ldaa_ext();
void hc11_ldaa_indx();
void hc11_ldaa_indy();
void hc11_ldab_imm();
void hc11_ldab_dir();
void hc11_ldab_ext();
void hc11_ldab_indx();
void hc11_ldab_indy();
void hc11_ldd_imm();
void hc11_ldd_dir();
void hc11_ldd_ext();
void hc11_ldd_indx();
void hc11_ldd_indy();
void hc11_lds_imm();
void hc11_lds_dir();
void hc11_lds_ext();
void hc11_lds_indx();
void hc11_lds_indy();
void hc11_ldx_imm();
void hc11_ldx_dir();
void hc11_ldx_ext();
void hc11_ldx_indx();
void hc11_ldx_indy();
void hc11_ldy_imm();
void hc11_ldy_dir();
void hc11_ldy_ext();
void hc11_ldy_indx();
void hc11_ldy_indy();
void hc11_lsld();
void hc11_lsra();
void hc11_lsrb();
void hc11_lsrd();
void hc11_mul();
void hc11_nega();
void hc11_negb();
void hc11_neg_ext();
void hc11_neg_indx();
void hc11_neg_indy();
void hc11_nop();
void hc11_psha();
void hc11_oraa_imm();
void hc11_oraa_dir();
void hc11_oraa_ext();
void hc11_oraa_indx();
void hc11_oraa_indy();
void hc11_orab_imm();
void hc11_orab_dir();
void hc11_orab_ext();
void hc11_orab_indx();
void hc11_orab_indy();
void hc11_pshb();
void hc11_pshx();
void hc11_pshy();
void hc11_pula();
void hc11_pulb();
void hc11_pulx();
void hc11_puly();
void hc11_rola();
void hc11_rolb();
void hc11_rol_ext();
void hc11_rol_indx();
void hc11_rol_indy();
void hc11_rora();
void hc11_rorb();
void hc11_rti();
void hc11_rts();
void hc11_sba();
void hc11_sbca_imm();
void hc11_sbca_indx();
void hc11_sbca_indy();
void hc11_sbcb_imm();
void hc11_sbcb_indx();
void hc11_sbcb_indy();
void hc11_sec();
void hc11_sei();
void hc11_sev();
void hc11_staa_dir();
void hc11_staa_ext();
void hc11_staa_indx();
void hc11_staa_indy();
void hc11_stab_dir();
void hc11_stab_ext();
void hc11_stab_indx();
void hc11_stab_indy();
void hc11_std_dir();
void hc11_std_ext();
void hc11_std_indx();
void hc11_std_indy();
void hc11_sts_dir();
void hc11_stx_dir();
void hc11_stx_ext();
void hc11_stx_indx();
void hc11_stx_indy();
void hc11_sty_dir();
void hc11_sty_ext();
void hc11_sty_indx();
void hc11_sty_indy();
void hc11_stop();
void hc11_suba_imm();
void hc11_suba_dir();
void hc11_suba_ext();
void hc11_suba_indx();
void hc11_suba_indy();
void hc11_subb_imm();
void hc11_subb_dir();
void hc11_subb_ext();
void hc11_subb_indx();
void hc11_subb_indy();
void hc11_subd_imm();
void hc11_subd_dir();
void hc11_subd_ext();
void hc11_subd_indx();
void hc11_subd_indy();
void hc11_swi();
void hc11_tab();
void hc11_tap();
void hc11_tba();
void hc11_test();
void hc11_tpa();
void hc11_tsta();
void hc11_tstb();
void hc11_tst_ext();
void hc11_tst_indx();
void hc11_tst_indy();
void hc11_tsx();
void hc11_tsy();
void hc11_txs();
void hc11_tys();
void hc11_wai();
void hc11_xgdx();
void hc11_xgdy();
void hc11_page2();
void hc11_page3();
void hc11_page4();
void hc11_invalid();
void check_irq_lines();
}; };

9
src/mame/drivers/30test.c
View File

@ -232,13 +232,6 @@ void namco_30test_state::machine_reset()
{ {
} }
static const hc11_config namco_30test_config =
{
0, //has extended internal I/O
768, //internal RAM size
0x00 //registers are at 0-0x100
};
static MACHINE_CONFIG_START( 30test, namco_30test_state ) static MACHINE_CONFIG_START( 30test, namco_30test_state )
@ -246,7 +239,7 @@ static MACHINE_CONFIG_START( 30test, namco_30test_state )
MCFG_CPU_ADD("maincpu", MC68HC11,MAIN_CLOCK/4) MCFG_CPU_ADD("maincpu", MC68HC11,MAIN_CLOCK/4)
MCFG_CPU_PROGRAM_MAP(namco_30test_map) MCFG_CPU_PROGRAM_MAP(namco_30test_map)
MCFG_CPU_IO_MAP(namco_30test_io) MCFG_CPU_IO_MAP(namco_30test_io)
MCFG_CPU_CONFIG(namco_30test_config) MCFG_MC68HC11_CONFIG( 0, 768, 0x00 )
/* no video! */ /* no video! */

8
src/mame/drivers/hitpoker.c
View File

@ -480,12 +480,6 @@ static const ay8910_interface ay8910_config =
DEVCB_NULL DEVCB_NULL
}; };
static const hc11_config hitpoker_config =
{
0, //has extended internal I/O
0x100, //internal RAM size
0x01 //INIT defaults to 0x01
};
INTERRUPT_GEN_MEMBER(hitpoker_state::hitpoker_irq) INTERRUPT_GEN_MEMBER(hitpoker_state::hitpoker_irq)
{ {
@ -496,7 +490,7 @@ static MACHINE_CONFIG_START( hitpoker, hitpoker_state )
MCFG_CPU_ADD("maincpu", MC68HC11,1000000) MCFG_CPU_ADD("maincpu", MC68HC11,1000000)
MCFG_CPU_PROGRAM_MAP(hitpoker_map) MCFG_CPU_PROGRAM_MAP(hitpoker_map)
MCFG_CPU_IO_MAP(hitpoker_io) MCFG_CPU_IO_MAP(hitpoker_io)
MCFG_CPU_CONFIG(hitpoker_config) MCFG_MC68HC11_CONFIG(0, 0x100, 0x01)
MCFG_CPU_VBLANK_INT_DRIVER("screen", hitpoker_state, hitpoker_irq) MCFG_CPU_VBLANK_INT_DRIVER("screen", hitpoker_state, hitpoker_irq)
MCFG_NVRAM_ADD_0FILL("nvram") MCFG_NVRAM_ADD_0FILL("nvram")

17
src/mame/drivers/skeetsht.c
View File

@ -213,21 +213,6 @@ static INPUT_PORTS_START( skeetsht )
INPUT_PORTS_END INPUT_PORTS_END
/*************************************
*
* 68HC11A1 configuration
*
*************************************/
static const hc11_config skeetsht_hc11_config =
{
0,
0x100, /* 256 bytes RAM */
0x01,
// 0x200, /* 512 bytes EEPROM */
};
/************************************* /*************************************
* *
* TMS34010 configuration * TMS34010 configuration
@ -260,7 +245,7 @@ static MACHINE_CONFIG_START( skeetsht, skeetsht_state )
MCFG_CPU_ADD("68hc11", MC68HC11, 4000000) // ? MCFG_CPU_ADD("68hc11", MC68HC11, 4000000) // ?
MCFG_CPU_PROGRAM_MAP(hc11_pgm_map) MCFG_CPU_PROGRAM_MAP(hc11_pgm_map)
MCFG_CPU_IO_MAP(hc11_io_map) MCFG_CPU_IO_MAP(hc11_io_map)
MCFG_CPU_CONFIG(skeetsht_hc11_config) MCFG_MC68HC11_CONFIG( 0, 0x100, 0x01 ) // And 512 bytes EEPROM? (68HC11A1)
MCFG_CPU_ADD("tms", TMS34010, 48000000) MCFG_CPU_ADD("tms", TMS34010, 48000000)
MCFG_CPU_CONFIG(tms_config) MCFG_CPU_CONFIG(tms_config)

8
src/mame/drivers/taitojc.c
View File

@ -1248,12 +1248,6 @@ static const tc0640fio_interface taitojc_io_intf =
DEVCB_INPUT_PORT("START"), DEVCB_INPUT_PORT("UNUSED"), DEVCB_INPUT_PORT("BUTTONS") DEVCB_INPUT_PORT("START"), DEVCB_INPUT_PORT("UNUSED"), DEVCB_INPUT_PORT("BUTTONS")
}; };
static const hc11_config taitojc_hc11_config =
{
1, // has extended I/O
1280, // internal RAM size
0x00 // INIT defaults to 0x00
};
static MACHINE_CONFIG_START( taitojc, taitojc_state ) static MACHINE_CONFIG_START( taitojc, taitojc_state )
@ -1265,7 +1259,7 @@ static MACHINE_CONFIG_START( taitojc, taitojc_state )
MCFG_CPU_ADD("sub", MC68HC11, XTAL_16MHz/2) // 8MHz, MC68HC11M0 MCFG_CPU_ADD("sub", MC68HC11, XTAL_16MHz/2) // 8MHz, MC68HC11M0
MCFG_CPU_PROGRAM_MAP(hc11_pgm_map) MCFG_CPU_PROGRAM_MAP(hc11_pgm_map)
MCFG_CPU_IO_MAP(hc11_io_map) MCFG_CPU_IO_MAP(hc11_io_map)
MCFG_CPU_CONFIG(taitojc_hc11_config) MCFG_MC68HC11_CONFIG( 1, 1280, 0x00 )
MCFG_CPU_ADD("dsp", TMS32051, XTAL_10MHz*4) // 40MHz, clock source = CY7C991 MCFG_CPU_ADD("dsp", TMS32051, XTAL_10MHz*4) // 40MHz, clock source = CY7C991
MCFG_CPU_PROGRAM_MAP(tms_program_map) MCFG_CPU_PROGRAM_MAP(tms_program_map)

9
src/mess/drivers/alphasma.c
View File

@ -368,19 +368,12 @@ void alphasmart_state::machine_reset()
m_port_d = 0; m_port_d = 0;
} }
static const hc11_config alphasmart_hc11_config =
{
0, // has extended internal I/O
0, // FIXME: should be 192, but the 68hc11 core doesn't handle internal RAM correctly
0x00 // registers are at 0-0x3f
};
static MACHINE_CONFIG_START( alphasmart, alphasmart_state ) static MACHINE_CONFIG_START( alphasmart, alphasmart_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", MC68HC11, XTAL_8MHz/2) // MC68HC11D0, XTAL is 8 Mhz, unknown divider MCFG_CPU_ADD("maincpu", MC68HC11, XTAL_8MHz/2) // MC68HC11D0, XTAL is 8 Mhz, unknown divider
MCFG_CPU_PROGRAM_MAP(alphasmart_mem) MCFG_CPU_PROGRAM_MAP(alphasmart_mem)
MCFG_CPU_IO_MAP(alphasmart_io) MCFG_CPU_IO_MAP(alphasmart_io)
MCFG_CPU_CONFIG(alphasmart_hc11_config) MCFG_MC68HC11_CONFIG(0, 0, 0x00) // FIXME: internal ram should be 192, but the 68hc11 core doesn't handle internal RAM correctly
MCFG_KS0066_F05_ADD("ks0066_0") MCFG_KS0066_F05_ADD("ks0066_0")
MCFG_HD44780_LCD_SIZE(2, 40) MCFG_HD44780_LCD_SIZE(2, 40)