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https://github.com/holub/mame
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hcd62121.c: Modernized cpu core. (nw)
This commit is contained in:
Wilbert Pol
parent
8dc0e74136
commit
f0219e2e5a
@ -15,28 +15,6 @@ Martin Poupe's site can be found at http://martin.poupe.org/casio/
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#include "hcd62121.h"
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struct hcd62121_state
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{
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UINT32 prev_pc;
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UINT16 sp;
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UINT16 ip;
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UINT8 dsize;
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UINT8 cseg;
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UINT8 dseg;
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UINT8 sseg;
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UINT8 f;
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UINT16 lar;
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UINT8 reg[0x80];
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UINT8 temp1[0x10];
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UINT8 temp2[0x10];
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device_irq_acknowledge_callback irq_callback;
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legacy_cpu_device *device;
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address_space *program;
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address_space *io;
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int icount;
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};
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/* From the battery check routine at 20:e874 it looks like
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bit 3 of the flag register should be the Zero flag. */
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#define _FLAG_Z 0x08
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@ -46,21 +24,26 @@ struct hcd62121_state
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#define _FLAG_ZH 0x10
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#define mem_readbyte(cs,A) ((UINT8)(cs)->program->read_byte(A))
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#define mem_writebyte(cs,A,V) ((cs)->program->write_byte(A,V))
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#define io_readbyte(cs,A) ((UINT8)(cs)->io->read_byte(A))
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#define io_writebyte(cs,A,V) ((cs)->io->write_byte(A,V))
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const device_type HCD62121 = &device_creator<hcd62121_cpu_device>;
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INLINE UINT8 read_op(hcd62121_state *cpustate)
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hcd62121_cpu_device::hcd62121_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: cpu_device(mconfig, HCD62121, "Hitachi HCD62121", tag, owner, clock)
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, m_program_config("program", ENDIANNESS_BIG, 8, 24, 0)
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, m_io_config("io", ENDIANNESS_BIG, 8, 8, 0)
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{
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UINT8 d = mem_readbyte(cpustate, ( cpustate->cseg << 16 ) | cpustate->ip );
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cpustate->ip++;
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}
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UINT8 hcd62121_cpu_device::read_op()
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{
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UINT8 d = m_program->read_byte( ( m_cseg << 16 ) | m_ip );
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m_ip++;
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return d;
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}
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INLINE UINT8 datasize( hcd62121_state *cpustate, UINT8 op )
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UINT8 hcd62121_cpu_device::datasize( UINT8 op )
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{
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switch( op & 0x03 )
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{
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@ -69,67 +52,67 @@ INLINE UINT8 datasize( hcd62121_state *cpustate, UINT8 op )
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case 1:
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return 2;
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case 2:
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return ( cpustate->dsize >> 4 ) + 1;
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return ( m_dsize >> 4 ) + 1;
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case 3:
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return ( cpustate->dsize & 0x0f ) + 1;
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return ( m_dsize & 0x0f ) + 1;
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}
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return 1;
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}
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INLINE void read_reg( hcd62121_state *cpustate, int size, UINT8 op1 )
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void hcd62121_cpu_device::read_reg( int size, UINT8 op1 )
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{
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int i;
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if ( op1 & 0x80 )
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{
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for ( i = 0; i < size; i++ )
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cpustate->temp1[i] = cpustate->reg[ ( op1 - i ) & 0x7f ];
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m_temp1[i] = m_reg[ ( op1 - i ) & 0x7f ];
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}
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else
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{
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for ( i = 0; i < size; i++ )
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cpustate->temp1[i] = cpustate->reg[ ( op1 + i ) & 0x7f ];
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m_temp1[i] = m_reg[ ( op1 + i ) & 0x7f ];
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}
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}
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INLINE void write_reg( hcd62121_state *cpustate, int size, UINT8 op1 )
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void hcd62121_cpu_device::write_reg( int size, UINT8 op1 )
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{
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int i;
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if ( op1 & 0x80 )
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{
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for ( i = 0; i < size; i++ )
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cpustate->reg[ ( op1 - i ) & 0x7f ] = cpustate->temp1[i];
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m_reg[ ( op1 - i ) & 0x7f ] = m_temp1[i];
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}
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else
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{
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for ( i = 0; i < size; i++ )
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cpustate->reg[ ( op1 + i ) & 0x7f ] = cpustate->temp1[i];
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m_reg[ ( op1 + i ) & 0x7f ] = m_temp1[i];
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}
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}
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INLINE void read_regreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2, bool op_is_logical )
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void hcd62121_cpu_device::read_regreg( int size, UINT8 op1, UINT8 op2, bool op_is_logical )
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{
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int i;
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for ( i = 0; i < size; i++ )
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cpustate->temp1[i] = cpustate->reg[ (op1 + i) & 0x7f];
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m_temp1[i] = m_reg[ (op1 + i) & 0x7f];
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if ( op1 & 0x80 )
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{
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/* Second operand is an immediate value */
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cpustate->temp2[0] = op2;
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m_temp2[0] = op2;
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for ( i = 1; i < size; i++ )
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cpustate->temp2[i] = op_is_logical ? op2 : 0;
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m_temp2[i] = op_is_logical ? op2 : 0;
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}
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else
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{
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/* Second operand is a register */
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for ( i = 0; i < size; i++ )
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cpustate->temp2[i] = cpustate->reg[ (op2 + i) & 0x7f ];
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m_temp2[i] = m_reg[ (op2 + i) & 0x7f ];
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}
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if ( ! ( op1 & 0x80 ) && ! ( op2 & 0x80 ) )
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@ -137,15 +120,15 @@ INLINE void read_regreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op
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/* We need to swap parameters */
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for ( i = 0; i < size; i++ )
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{
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UINT8 v = cpustate->temp1[i];
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cpustate->temp1[i] = cpustate->temp2[i];
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cpustate->temp2[i] = v;
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UINT8 v = m_temp1[i];
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m_temp1[i] = m_temp2[i];
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m_temp2[i] = v;
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}
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}
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}
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INLINE void write_regreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 )
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void hcd62121_cpu_device::write_regreg( int size, UINT8 op1, UINT8 op2 )
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{
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int i;
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@ -153,41 +136,41 @@ INLINE void write_regreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 o
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{
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/* store in reg1 */
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for ( i = 0; i < size; i++ )
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cpustate->reg[ (op1 + i) & 0x7f] = cpustate->temp1[i];
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m_reg[ (op1 + i) & 0x7f] = m_temp1[i];
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}
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else
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{
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/* store in reg2 */
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for ( i = 0; i < size; i++ )
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cpustate->reg[ (op2 + i) & 0x7f] = cpustate->temp1[i];
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m_reg[ (op2 + i) & 0x7f] = m_temp1[i];
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}
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}
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INLINE void read_iregreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 )
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void hcd62121_cpu_device::read_iregreg( int size, UINT8 op1, UINT8 op2 )
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{
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int i;
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UINT16 ad;
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ad = cpustate->reg[ ( 0x40 | op1 ) & 0x7f ] | ( cpustate->reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 );
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ad = m_reg[ ( 0x40 | op1 ) & 0x7f ] | ( m_reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 );
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for ( i = 0; i < size; i++ )
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{
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cpustate->temp1[i] = mem_readbyte( cpustate, ( cpustate->dseg << 16 ) | ad );
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m_temp1[i] = m_program->read_byte( ( m_dseg << 16 ) | ad );
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ad += ( op1 & 0x40 ) ? -1 : 1;
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}
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cpustate->lar = ad;
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m_lar = ad;
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if ( op1 & 0x80 )
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{
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cpustate->temp2[0] = op2;
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m_temp2[0] = op2;
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for ( i = 1; i < size; i++ )
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cpustate->temp2[i] = 0;
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m_temp2[i] = 0;
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}
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else
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{
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for ( i = 0; i < size; i++ )
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cpustate->temp2[i] = cpustate->reg[ (op2 + i) & 0x7f ];
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m_temp2[i] = m_reg[ (op2 + i) & 0x7f ];
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}
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if ( ! ( op1 & 0x80 ) && ! ( op2 & 0x80 ) )
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@ -195,40 +178,40 @@ INLINE void read_iregreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 o
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/* We need to swap parameters */
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for ( i = 0; i < size; i++ )
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{
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UINT8 v = cpustate->temp1[i];
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cpustate->temp1[i] = cpustate->temp2[i];
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cpustate->temp2[i] = v;
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UINT8 v = m_temp1[i];
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m_temp1[i] = m_temp2[i];
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m_temp2[i] = v;
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}
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}
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}
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INLINE void write_iregreg( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 )
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void hcd62121_cpu_device::write_iregreg( int size, UINT8 op1, UINT8 op2 )
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{
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int i;
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if ( ( op1 & 0x80 ) || ( op2 & 0x80 ) )
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{
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/* store in (reg1) */
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UINT16 ad = cpustate->reg[ ( 0x40 | op1 ) & 0x7f ] | ( cpustate->reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 );
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UINT16 ad = m_reg[ ( 0x40 | op1 ) & 0x7f ] | ( m_reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 );
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for ( i = 0; i < size; i++ )
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{
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mem_writebyte( cpustate, ( cpustate->dseg << 16 ) | ad, cpustate->temp1[i] );
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m_program->write_byte( ( m_dseg << 16 ) | ad, m_temp1[i] );
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ad += ( op1 & 0x40 ) ? -1 : 1;
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}
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cpustate->lar = ad;
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m_lar = ad;
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}
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else
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{
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/* store in reg2 */
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for ( i = 0; i < size; i++ )
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cpustate->reg[ (op2 + i) & 0x7f] = cpustate->temp1[i];
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m_reg[ (op2 + i) & 0x7f] = m_temp1[i];
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}
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}
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INLINE void write_iregreg2( hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 )
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void hcd62121_cpu_device::write_iregreg2( int size, UINT8 op1, UINT8 op2 )
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{
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int i;
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@ -236,64 +219,64 @@ INLINE void write_iregreg2( hcd62121_state *cpustate, int size, UINT8 op1, UINT8
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{
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/* store in reg2 */
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for ( i = 0; i < size; i++ )
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cpustate->reg[ (op2 + i) & 0x7f] = cpustate->temp2[i];
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m_reg[ (op2 + i) & 0x7f] = m_temp2[i];
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}
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else
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{
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/* store in (reg1) */
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UINT16 ad = cpustate->reg[ ( 0x40 | op1 ) & 0x7f ] | ( cpustate->reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 );
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UINT16 ad = m_reg[ ( 0x40 | op1 ) & 0x7f ] | ( m_reg[ ( 0x40 | ( op1 + 1 ) ) & 0x7f ] << 8 );
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for ( i = 0; i < size; i++ )
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{
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mem_writebyte( cpustate, ( cpustate->dseg << 16 ) | ad, cpustate->temp2[i] );
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m_program->write_byte( ( m_dseg << 16 ) | ad, m_temp2[i] );
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ad += ( op1 & 0x40 ) ? -1 : 1;
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}
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cpustate->lar = ad;
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m_lar = ad;
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}
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}
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INLINE int check_cond( hcd62121_state *cpustate, UINT8 op )
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int hcd62121_cpu_device::check_cond( UINT8 op )
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{
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switch ( op & 0x07 )
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{
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case 0x00: /* ZH set */
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if ( cpustate->f & _FLAG_ZH )
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if ( m_f & _FLAG_ZH )
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return 1;
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break;
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case 0x01: /* ZL set */
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if ( cpustate->f & _FLAG_ZL )
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if ( m_f & _FLAG_ZL )
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return 1;
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break;
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case 0x02: /* C set */
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if ( cpustate->f & _FLAG_C )
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if ( m_f & _FLAG_C )
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return 1;
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break;
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case 0x03: /* Z set */
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if ( cpustate->f & _FLAG_Z )
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if ( m_f & _FLAG_Z )
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return 1;
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break;
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case 0x04: /* Z or C set */
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if ( cpustate->f & ( _FLAG_Z | _FLAG_C ) )
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if ( m_f & ( _FLAG_Z | _FLAG_C ) )
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return 1;
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break;
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case 0x05: /* CL set */
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if ( cpustate->f & _FLAG_CL )
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if ( m_f & _FLAG_CL )
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return 1;
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break;
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case 0x06: /* C clear */
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if ( ! ( cpustate->f & _FLAG_C ) )
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if ( ! ( m_f & _FLAG_C ) )
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return 1;
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break;
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case 0x07: /* Z clear */
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if ( ! ( cpustate->f & _FLAG_Z ) )
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if ( ! ( m_f & _FLAG_Z ) )
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return 1;
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break;
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}
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@ -302,208 +285,238 @@ INLINE int check_cond( hcd62121_state *cpustate, UINT8 op )
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}
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INLINE hcd62121_state *get_safe_token(device_t *device)
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void hcd62121_cpu_device::device_start()
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{
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assert(device != NULL);
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assert(device->type() == HCD62121);
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return (hcd62121_state *)downcast<legacy_cpu_device *>(device)->token();
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// m_irq_callback = irqcallback;
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m_program = &space(AS_PROGRAM);
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m_io = &space(AS_IO);
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save_item( NAME(m_prev_pc) );
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save_item( NAME(m_sp) );
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save_item( NAME(m_ip) );
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save_item( NAME(m_dsize) );
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save_item( NAME(m_cseg) );
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save_item( NAME(m_dseg) );
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save_item( NAME(m_sseg) );
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save_item( NAME(m_f) );
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save_item( NAME(m_lar) );
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save_item( NAME(m_reg) );
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save_item( NAME(m_temp1) );
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save_item( NAME(m_temp2) );
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// Register state for debugger
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state_add( STATE_GENPC, "curpc", m_ip ).callimport().callexport().formatstr("%8s");
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state_add( STATE_GENFLAGS, "GENFLAGS", m_f ).callimport().callexport().formatstr("%12s").noshow();
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state_add( HCD62121_IP, "IP", m_ip ).callimport().callexport().formatstr("%04X");
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state_add( HCD62121_SP, "SP", m_sp ).callimport().callexport().formatstr("%04X");
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state_add( HCD62121_LAR, "LAR", m_lar ).callimport().callexport().formatstr("%04X");
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state_add( HCD62121_CS, "CS", m_cseg ).callimport().callexport().formatstr("%02X");
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state_add( HCD62121_DS, "DS", m_dseg ).callimport().callexport().formatstr("%02X");
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state_add( HCD62121_SS, "SS", m_sseg ).callimport().callexport().formatstr("%02X");
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state_add( HCD62121_DSIZE, "DSIZE", m_dsize ).callimport().callexport().formatstr("%02X");
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state_add( HCD62121_F, "F", m_f ).callimport().callexport().formatstr("%02X");
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state_add( HCD62121_R00, "R00", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
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state_add( HCD62121_R04, "R04", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
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state_add( HCD62121_R08, "R08", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
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state_add( HCD62121_R0C, "R0C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
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state_add( HCD62121_R10, "R10", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
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state_add( HCD62121_R14, "R14", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
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state_add( HCD62121_R18, "R18", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
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state_add( HCD62121_R1C, "R1C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
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state_add( HCD62121_R20, "R20", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
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state_add( HCD62121_R24, "R24", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
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state_add( HCD62121_R28, "R28", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
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state_add( HCD62121_R2C, "R2C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R30, "R30", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R34, "R34", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R38, "R38", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R3C, "R3C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R40, "R40", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R44, "R44", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R48, "R48", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R4C, "R4C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R50, "R50", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R54, "R54", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R58, "R58", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R5C, "R5C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R60, "R60", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R64, "R64", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R68, "R68", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R6C, "R6C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R70, "R70", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R74, "R74", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R78, "R78", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
state_add( HCD62121_R7C, "R7C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
|
||||
|
||||
m_icountptr = &m_icount;
|
||||
}
|
||||
|
||||
|
||||
static CPU_INIT( hcd62121 )
|
||||
void hcd62121_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
|
||||
{
|
||||
hcd62121_state *cpustate = get_safe_token(device);
|
||||
|
||||
cpustate->irq_callback = irqcallback;
|
||||
cpustate->device = device;
|
||||
cpustate->program = &device->space(AS_PROGRAM);
|
||||
cpustate->io = &device->space(AS_IO);
|
||||
}
|
||||
|
||||
|
||||
static CPU_RESET( hcd62121 )
|
||||
{
|
||||
hcd62121_state *cpustate = get_safe_token(device);
|
||||
|
||||
cpustate->sp = 0x0000;
|
||||
cpustate->ip = 0x0000;
|
||||
cpustate->cseg = 0;
|
||||
cpustate->dseg = 0;
|
||||
cpustate->sseg = 0;
|
||||
cpustate->lar = 0;
|
||||
cpustate->f = 0;
|
||||
cpustate->dsize = 0;
|
||||
|
||||
for( int i = 0; i < 0x80; i++ )
|
||||
switch (entry.index())
|
||||
{
|
||||
cpustate->reg[i] = 0;
|
||||
case STATE_GENPC:
|
||||
string.printf("%06X", ( m_cseg << 16 ) | m_ip);
|
||||
break;
|
||||
|
||||
case STATE_GENFLAGS:
|
||||
string.printf("%s-%s-%s-%c-%c",
|
||||
m_f & _FLAG_ZH ? "ZH":"__",
|
||||
m_f & _FLAG_CL ? "CL":"__",
|
||||
m_f & _FLAG_ZL ? "ZL":"__",
|
||||
m_f & _FLAG_C ? 'C':'_',
|
||||
m_f & _FLAG_Z ? 'Z':'_'
|
||||
);
|
||||
|
||||
break;
|
||||
|
||||
case HCD62121_R00:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x00], m_reg[0x01], m_reg[0x02], m_reg[0x03]);
|
||||
break;
|
||||
case HCD62121_R04:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x04], m_reg[0x05], m_reg[0x06], m_reg[0x07]);
|
||||
break;
|
||||
case HCD62121_R08:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x08], m_reg[0x09], m_reg[0x0A], m_reg[0x0B]);
|
||||
break;
|
||||
case HCD62121_R0C:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x0C], m_reg[0x0D], m_reg[0x0E], m_reg[0x0F]);
|
||||
break;
|
||||
case HCD62121_R10:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x10], m_reg[0x11], m_reg[0x12], m_reg[0x13]);
|
||||
break;
|
||||
case HCD62121_R14:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x14], m_reg[0x15], m_reg[0x16], m_reg[0x17]);
|
||||
break;
|
||||
case HCD62121_R18:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x18], m_reg[0x19], m_reg[0x1A], m_reg[0x1B]);
|
||||
break;
|
||||
case HCD62121_R1C:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x1C], m_reg[0x1D], m_reg[0x1E], m_reg[0x1F]);
|
||||
break;
|
||||
case HCD62121_R20:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x20], m_reg[0x21], m_reg[0x22], m_reg[0x23]);
|
||||
break;
|
||||
case HCD62121_R24:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x24], m_reg[0x25], m_reg[0x26], m_reg[0x27]);
|
||||
break;
|
||||
case HCD62121_R28:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x28], m_reg[0x29], m_reg[0x2A], m_reg[0x2B]);
|
||||
break;
|
||||
case HCD62121_R2C:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x2C], m_reg[0x2D], m_reg[0x2E], m_reg[0x2F]);
|
||||
break;
|
||||
case HCD62121_R30:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x30], m_reg[0x31], m_reg[0x32], m_reg[0x33]);
|
||||
break;
|
||||
case HCD62121_R34:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x34], m_reg[0x35], m_reg[0x36], m_reg[0x37]);
|
||||
break;
|
||||
case HCD62121_R38:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x38], m_reg[0x39], m_reg[0x3A], m_reg[0x3B]);
|
||||
break;
|
||||
case HCD62121_R3C:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x3C], m_reg[0x3D], m_reg[0x3E], m_reg[0x3F]);
|
||||
break;
|
||||
case HCD62121_R40:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x40], m_reg[0x41], m_reg[0x42], m_reg[0x43]);
|
||||
break;
|
||||
case HCD62121_R44:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x44], m_reg[0x45], m_reg[0x46], m_reg[0x47]);
|
||||
break;
|
||||
case HCD62121_R48:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x48], m_reg[0x49], m_reg[0x4A], m_reg[0x4B]);
|
||||
break;
|
||||
case HCD62121_R4C:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x4C], m_reg[0x4D], m_reg[0x4E], m_reg[0x4F]);
|
||||
break;
|
||||
case HCD62121_R50:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x50], m_reg[0x51], m_reg[0x52], m_reg[0x53]);
|
||||
break;
|
||||
case HCD62121_R54:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x54], m_reg[0x55], m_reg[0x56], m_reg[0x57]);
|
||||
break;
|
||||
case HCD62121_R58:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x58], m_reg[0x59], m_reg[0x5A], m_reg[0x5B]);
|
||||
break;
|
||||
case HCD62121_R5C:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x5C], m_reg[0x5D], m_reg[0x5E], m_reg[0x5F]);
|
||||
break;
|
||||
case HCD62121_R60:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x60], m_reg[0x61], m_reg[0x62], m_reg[0x63]);
|
||||
break;
|
||||
case HCD62121_R64:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x64], m_reg[0x65], m_reg[0x66], m_reg[0x67]);
|
||||
break;
|
||||
case HCD62121_R68:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x68], m_reg[0x69], m_reg[0x6A], m_reg[0x6B]);
|
||||
break;
|
||||
case HCD62121_R6C:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x6C], m_reg[0x6D], m_reg[0x6E], m_reg[0x6F]);
|
||||
break;
|
||||
case HCD62121_R70:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x70], m_reg[0x71], m_reg[0x72], m_reg[0x73]);
|
||||
break;
|
||||
case HCD62121_R74:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x74], m_reg[0x75], m_reg[0x76], m_reg[0x77]);
|
||||
break;
|
||||
case HCD62121_R78:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x78], m_reg[0x79], m_reg[0x7A], m_reg[0x7B]);
|
||||
break;
|
||||
case HCD62121_R7C:
|
||||
string.printf("%02X%02X%02X%02X", m_reg[0x7C], m_reg[0x7D], m_reg[0x7E], m_reg[0x7F]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static CPU_EXECUTE( hcd62121 )
|
||||
void hcd62121_cpu_device::device_reset()
|
||||
{
|
||||
hcd62121_state *cpustate = get_safe_token(device);
|
||||
m_sp = 0x0000;
|
||||
m_ip = 0x0000;
|
||||
m_cseg = 0;
|
||||
m_dseg = 0;
|
||||
m_sseg = 0;
|
||||
m_lar = 0;
|
||||
m_f = 0;
|
||||
m_dsize = 0;
|
||||
|
||||
for( int i = 0; i < 0x80; i++ )
|
||||
{
|
||||
m_reg[i] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void hcd62121_cpu_device::execute_run()
|
||||
{
|
||||
do
|
||||
{
|
||||
UINT32 pc = ( cpustate->cseg << 16 ) | cpustate->ip;
|
||||
UINT32 pc = ( m_cseg << 16 ) | m_ip;
|
||||
UINT8 op;
|
||||
|
||||
debugger_instruction_hook(device, pc);
|
||||
cpustate->prev_pc = pc;
|
||||
debugger_instruction_hook(this, pc);
|
||||
m_prev_pc = pc;
|
||||
|
||||
op = read_op( cpustate );
|
||||
op = read_op();
|
||||
|
||||
cpustate->icount -= 4;
|
||||
m_icount -= 4;
|
||||
|
||||
switch ( op )
|
||||
{
|
||||
#include "hcd62121_ops.h"
|
||||
};
|
||||
|
||||
} while (cpustate->icount > 0);
|
||||
} while (m_icount > 0);
|
||||
}
|
||||
|
||||
|
||||
static CPU_SET_INFO( hcd62121 )
|
||||
offs_t hcd62121_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
|
||||
{
|
||||
hcd62121_state *cpustate = get_safe_token(device);
|
||||
|
||||
switch (state)
|
||||
{
|
||||
/* --- the following bits of info are set as 64-bit signed integers --- */
|
||||
case CPUINFO_INT_INPUT_STATE + 0:
|
||||
case CPUINFO_INT_INPUT_STATE + 1:
|
||||
break;
|
||||
|
||||
case CPUINFO_INT_SP: cpustate->sp = info->i; break;
|
||||
case CPUINFO_INT_PC: cpustate->ip = info->i; break;
|
||||
|
||||
case CPUINFO_INT_REGISTER + HCD62121_IP: cpustate->ip = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + HCD62121_SP: cpustate->sp = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + HCD62121_LAR: cpustate->lar = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + HCD62121_CS: cpustate->cseg = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + HCD62121_DS: cpustate->dseg = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + HCD62121_SS: cpustate->sseg = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + HCD62121_DSIZE: cpustate->dsize = info->i; break;
|
||||
// case CPUINFO_INT_REGISTER + HCD62121_R00: break;
|
||||
// case CPUINFO_INT_REGISTER + HCD62121_R02: break;
|
||||
}
|
||||
extern CPU_DISASSEMBLE( hcd62121 );
|
||||
return CPU_DISASSEMBLE_NAME(hcd62121)(this, buffer, pc, oprom, opram, options);
|
||||
}
|
||||
|
||||
|
||||
CPU_GET_INFO( hcd62121 )
|
||||
{
|
||||
hcd62121_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
|
||||
|
||||
switch (state)
|
||||
{
|
||||
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
||||
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hcd62121_state); break;
|
||||
case CPUINFO_INT_INPUT_LINES: info->i = 2; break;
|
||||
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break;
|
||||
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
|
||||
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
|
||||
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
|
||||
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
|
||||
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 18; break;
|
||||
case CPUINFO_INT_MIN_CYCLES: info->i = 4; /* right? */ break;
|
||||
case CPUINFO_INT_MAX_CYCLES: info->i = 48; /* right? */ break;
|
||||
|
||||
case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
|
||||
case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break;
|
||||
case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
|
||||
case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
|
||||
case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
|
||||
case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
|
||||
case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break;
|
||||
case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break;
|
||||
case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
|
||||
|
||||
case CPUINFO_INT_SP: info->i = cpustate->sp; break;
|
||||
case CPUINFO_INT_PC: info->i = ( cpustate->cseg << 16 ) | cpustate->ip; break;
|
||||
case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->prev_pc; break;
|
||||
|
||||
case CPUINFO_INT_INPUT_STATE + 0:
|
||||
case CPUINFO_INT_INPUT_STATE + 1:
|
||||
/* TODO */ break;
|
||||
|
||||
case CPUINFO_INT_REGISTER + HCD62121_IP: info->i = cpustate->ip; break;
|
||||
case CPUINFO_INT_REGISTER + HCD62121_SP: info->i = cpustate->sp; break;
|
||||
case CPUINFO_INT_REGISTER + HCD62121_LAR: info->i = cpustate->lar; break;
|
||||
case CPUINFO_INT_REGISTER + HCD62121_CS: info->i = cpustate->cseg; break;
|
||||
case CPUINFO_INT_REGISTER + HCD62121_DS: info->i = cpustate->dseg; break;
|
||||
case CPUINFO_INT_REGISTER + HCD62121_SS: info->i = cpustate->sseg; break;
|
||||
case CPUINFO_INT_REGISTER + HCD62121_DSIZE: info->i = cpustate->dsize; break;
|
||||
case CPUINFO_INT_REGISTER + HCD62121_R00: info->i = ( cpustate->reg[0x00] << 24 ) | ( cpustate->reg[0x01] << 16 ) | ( cpustate->reg[0x02] << 8 ) | cpustate->reg[0x03]; break;
|
||||
// case CPUINFO_INT_REGISTER + HCD62121_R02: info->i = cpustate->; break;
|
||||
|
||||
/* --- the following bits of info are returned as pointers to data or functions --- */
|
||||
case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(hcd62121); break;
|
||||
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(hcd62121); break;
|
||||
case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(hcd62121); break;
|
||||
case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(hcd62121); break;
|
||||
case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(hcd62121); break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
|
||||
|
||||
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "HCD62121"); break;
|
||||
case CPUINFO_STR_FAMILY: strcpy(info->s, "Hitachi HCD62121"); break;
|
||||
case CPUINFO_STR_VERSION: strcpy(info->s, "0.1"); break;
|
||||
case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
|
||||
case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright The MESS Team."); break;
|
||||
|
||||
case CPUINFO_STR_FLAGS:
|
||||
sprintf(info->s, "%s-%s-%s-%c-%c",
|
||||
cpustate->f & _FLAG_ZH ? "ZH":"__",
|
||||
cpustate->f & _FLAG_CL ? "CL":"__",
|
||||
cpustate->f & _FLAG_ZL ? "ZL":"__",
|
||||
cpustate->f & _FLAG_C ? 'C':'_',
|
||||
cpustate->f & _FLAG_Z ? 'Z':'_'
|
||||
);
|
||||
break;
|
||||
|
||||
case CPUINFO_STR_REGISTER + HCD62121_IP: sprintf(info->s, "IP:%04X", cpustate->ip); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_SP: sprintf(info->s, "SP:%04X", cpustate->sp); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_LAR: sprintf(info->s, "LAR:%04X", cpustate->lar); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_CS: sprintf(info->s, "CS:%02X", cpustate->cseg); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_DS: sprintf(info->s, "DS:%02X", cpustate->dseg); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_SS: sprintf(info->s, "SS:%02X", cpustate->sseg); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_DSIZE: sprintf(info->s, "DSIZE:%02X", cpustate->dsize); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R00: sprintf(info->s, "R00:%02X%02X%02X%02X", cpustate->reg[0x00], cpustate->reg[0x01], cpustate->reg[0x02], cpustate->reg[0x03]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R04: sprintf(info->s, "R04:%02X%02X%02X%02X", cpustate->reg[0x04], cpustate->reg[0x05], cpustate->reg[0x06], cpustate->reg[0x07]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R08: sprintf(info->s, "R08:%02X%02X%02X%02X", cpustate->reg[0x08], cpustate->reg[0x09], cpustate->reg[0x0a], cpustate->reg[0x0b]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R0C: sprintf(info->s, "R0C:%02X%02X%02X%02X", cpustate->reg[0x0c], cpustate->reg[0x0d], cpustate->reg[0x0e], cpustate->reg[0x0f]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R10: sprintf(info->s, "R10:%02X%02X%02X%02X", cpustate->reg[0x10], cpustate->reg[0x11], cpustate->reg[0x12], cpustate->reg[0x13]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R14: sprintf(info->s, "R14:%02X%02X%02X%02X", cpustate->reg[0x14], cpustate->reg[0x15], cpustate->reg[0x16], cpustate->reg[0x17]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R18: sprintf(info->s, "R18:%02X%02X%02X%02X", cpustate->reg[0x18], cpustate->reg[0x19], cpustate->reg[0x1a], cpustate->reg[0x1b]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R1C: sprintf(info->s, "R1C:%02X%02X%02X%02X", cpustate->reg[0x1c], cpustate->reg[0x1d], cpustate->reg[0x1e], cpustate->reg[0x1f]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R20: sprintf(info->s, "R20:%02X%02X%02X%02X", cpustate->reg[0x20], cpustate->reg[0x21], cpustate->reg[0x22], cpustate->reg[0x23]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R24: sprintf(info->s, "R24:%02X%02X%02X%02X", cpustate->reg[0x24], cpustate->reg[0x25], cpustate->reg[0x26], cpustate->reg[0x27]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R28: sprintf(info->s, "R28:%02X%02X%02X%02X", cpustate->reg[0x28], cpustate->reg[0x29], cpustate->reg[0x2a], cpustate->reg[0x2b]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R2C: sprintf(info->s, "R2C:%02X%02X%02X%02X", cpustate->reg[0x2c], cpustate->reg[0x2d], cpustate->reg[0x2e], cpustate->reg[0x2f]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R30: sprintf(info->s, "R30:%02X%02X%02X%02X", cpustate->reg[0x30], cpustate->reg[0x31], cpustate->reg[0x32], cpustate->reg[0x33]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R34: sprintf(info->s, "R34:%02X%02X%02X%02X", cpustate->reg[0x34], cpustate->reg[0x35], cpustate->reg[0x36], cpustate->reg[0x37]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R38: sprintf(info->s, "R38:%02X%02X%02X%02X", cpustate->reg[0x38], cpustate->reg[0x39], cpustate->reg[0x3a], cpustate->reg[0x3b]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R3C: sprintf(info->s, "R3C:%02X%02X%02X%02X", cpustate->reg[0x3c], cpustate->reg[0x3d], cpustate->reg[0x3e], cpustate->reg[0x3f]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R40: sprintf(info->s, "R40:%02X%02X%02X%02X", cpustate->reg[0x40], cpustate->reg[0x41], cpustate->reg[0x42], cpustate->reg[0x43]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R44: sprintf(info->s, "R44:%02X%02X%02X%02X", cpustate->reg[0x44], cpustate->reg[0x45], cpustate->reg[0x46], cpustate->reg[0x47]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R48: sprintf(info->s, "R48:%02X%02X%02X%02X", cpustate->reg[0x48], cpustate->reg[0x49], cpustate->reg[0x4a], cpustate->reg[0x4b]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R4C: sprintf(info->s, "R4C:%02X%02X%02X%02X", cpustate->reg[0x4c], cpustate->reg[0x4d], cpustate->reg[0x4e], cpustate->reg[0x4f]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R50: sprintf(info->s, "R50:%02X%02X%02X%02X", cpustate->reg[0x50], cpustate->reg[0x51], cpustate->reg[0x52], cpustate->reg[0x53]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R54: sprintf(info->s, "R54:%02X%02X%02X%02X", cpustate->reg[0x54], cpustate->reg[0x55], cpustate->reg[0x56], cpustate->reg[0x57]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R58: sprintf(info->s, "R58:%02X%02X%02X%02X", cpustate->reg[0x58], cpustate->reg[0x59], cpustate->reg[0x5a], cpustate->reg[0x5b]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R5C: sprintf(info->s, "R5C:%02X%02X%02X%02X", cpustate->reg[0x5c], cpustate->reg[0x5d], cpustate->reg[0x5e], cpustate->reg[0x5f]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R60: sprintf(info->s, "R60:%02X%02X%02X%02X", cpustate->reg[0x60], cpustate->reg[0x61], cpustate->reg[0x62], cpustate->reg[0x63]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R64: sprintf(info->s, "R64:%02X%02X%02X%02X", cpustate->reg[0x64], cpustate->reg[0x65], cpustate->reg[0x66], cpustate->reg[0x67]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R68: sprintf(info->s, "R68:%02X%02X%02X%02X", cpustate->reg[0x68], cpustate->reg[0x69], cpustate->reg[0x6a], cpustate->reg[0x6b]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R6C: sprintf(info->s, "R6C:%02X%02X%02X%02X", cpustate->reg[0x6c], cpustate->reg[0x6d], cpustate->reg[0x6e], cpustate->reg[0x6f]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R70: sprintf(info->s, "R70:%02X%02X%02X%02X", cpustate->reg[0x70], cpustate->reg[0x71], cpustate->reg[0x72], cpustate->reg[0x73]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R74: sprintf(info->s, "R74:%02X%02X%02X%02X", cpustate->reg[0x74], cpustate->reg[0x75], cpustate->reg[0x76], cpustate->reg[0x77]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R78: sprintf(info->s, "R78:%02X%02X%02X%02X", cpustate->reg[0x78], cpustate->reg[0x79], cpustate->reg[0x7a], cpustate->reg[0x7b]); break;
|
||||
case CPUINFO_STR_REGISTER + HCD62121_R7C: sprintf(info->s, "R7C:%02X%02X%02X%02X", cpustate->reg[0x7c], cpustate->reg[0x7d], cpustate->reg[0x7e], cpustate->reg[0x7f]); break;
|
||||
}
|
||||
}
|
||||
|
||||
DEFINE_LEGACY_CPU_DEVICE(HCD62121, hcd62121);
|
||||
|
||||
@ -31,9 +31,68 @@ enum
|
||||
};
|
||||
|
||||
|
||||
DECLARE_LEGACY_CPU_DEVICE(HCD62121, hcd62121);
|
||||
class hcd62121_cpu_device : public cpu_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
hcd62121_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
|
||||
// device_execute_interface overrides
|
||||
virtual UINT32 execute_min_cycles() const { return 4; }
|
||||
virtual UINT32 execute_max_cycles() const { return 48; }
|
||||
virtual UINT32 execute_input_lines() const { return 2; }
|
||||
virtual void execute_run();
|
||||
|
||||
// device_memory_interface overrides
|
||||
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); }
|
||||
|
||||
// device_state_interface overrides
|
||||
void state_string_export(const device_state_entry &entry, astring &string);
|
||||
|
||||
// device_disasm_interface overrides
|
||||
virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
|
||||
virtual UINT32 disasm_max_opcode_bytes() const { return 18; }
|
||||
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
|
||||
|
||||
UINT8 read_op();
|
||||
UINT8 datasize( UINT8 op );
|
||||
void read_reg( int size, UINT8 op1 );
|
||||
void write_reg( int size, UINT8 op1 );
|
||||
void read_regreg( int size, UINT8 op1, UINT8 op2, bool op_is_logical );
|
||||
void write_regreg( int size, UINT8 op1, UINT8 op2 );
|
||||
void read_iregreg( int size, UINT8 op1, UINT8 op2 );
|
||||
void write_iregreg( int size, UINT8 op1, UINT8 op2 );
|
||||
void write_iregreg2( int size, UINT8 op1, UINT8 op2 );
|
||||
int check_cond( UINT8 op );
|
||||
|
||||
address_space_config m_program_config;
|
||||
address_space_config m_io_config;
|
||||
|
||||
UINT32 m_prev_pc;
|
||||
UINT16 m_sp;
|
||||
UINT16 m_ip;
|
||||
UINT8 m_dsize;
|
||||
UINT8 m_cseg;
|
||||
UINT8 m_dseg;
|
||||
UINT8 m_sseg;
|
||||
UINT8 m_f;
|
||||
UINT16 m_lar;
|
||||
UINT8 m_reg[0x80];
|
||||
UINT8 m_temp1[0x10];
|
||||
UINT8 m_temp2[0x10];
|
||||
|
||||
address_space *m_program;
|
||||
address_space *m_io;
|
||||
int m_icount;
|
||||
};
|
||||
|
||||
|
||||
extern CPU_DISASSEMBLE( hcd62121 );
|
||||
extern const device_type HCD62121;
|
||||
|
||||
|
||||
#endif /* __HCD62121_H__ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user