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From: Atari Ace [mailto:atari_ace@verizon.net]

Browse Source 
Sent: Sunday, December 07, 2008 1:48 PM
To: submit@mamedev.org
Cc: atariace@hotmail.com
Subject: [patch] Pointerify sharc core

Hi mamedev,

The attached patch pointerifies the sharc core.  If this has already
been done, no great loss, it only took about an hour and a half to do
this.

~aa
This commit is contained in:
Aaron Giles 2008-12-08 05:07:54 +00:00
parent 65f9ee3d3a
commit f0849513d0
11 changed files with 1791 additions and 1852 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

498
src/emu/cpu/sharc/compute.c
View File

File diff suppressed because it is too large Load Diff

1147
src/emu/cpu/sharc/sharc.c
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File diff suppressed because it is too large Load Diff

6
src/emu/cpu/sharc/sharc.h
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@ -22,10 +22,10 @@ typedef struct {
SHARC_BOOT_MODE boot_mode;
} sharc_config;
extern void sharc_set_flag_input(int flag_num, int state);
extern void sharc_set_flag_input(const device_config *device, int flag_num, int state);
extern void sharc_external_iop_write(UINT32 address, UINT32 data);
extern void sharc_external_dma_write(UINT32 address, UINT64 data);
extern void sharc_external_iop_write(const device_config *device, UINT32 address, UINT32 data);
extern void sharc_external_dma_write(const device_config *device, UINT32 address, UINT64 data);
#if (HAS_ADSP21062)
CPU_GET_INFO( adsp21062 );

166
src/emu/cpu/sharc/sharcdma.c
View File

@ -6,70 +6,70 @@
#define DMA_PMODE_32_48 3
#define DMA_PMODE_8_48 4
static void schedule_chained_dma_op(int channel, UINT32 dma_chain_ptr, int chained_direction)
static void schedule_chained_dma_op(SHARC_REGS *cpustate, int channel, UINT32 dma_chain_ptr, int chained_direction)
{
UINT32 op_ptr = 0x20000 + dma_chain_ptr;
UINT32 int_index = dm_read32(op_ptr - 0);
UINT32 int_modifier = dm_read32(op_ptr - 1);
UINT32 int_count = dm_read32(op_ptr - 2);
UINT32 chain_ptr = dm_read32(op_ptr - 3);
//UINT32 gen_purpose = dm_read32(op_ptr - 4);
UINT32 ext_index = dm_read32(op_ptr - 5);
UINT32 ext_modifier = dm_read32(op_ptr - 6);
UINT32 ext_count = dm_read32(op_ptr - 7);
UINT32 int_index = dm_read32(cpustate, op_ptr - 0);
UINT32 int_modifier = dm_read32(cpustate, op_ptr - 1);
UINT32 int_count = dm_read32(cpustate, op_ptr - 2);
UINT32 chain_ptr = dm_read32(cpustate, op_ptr - 3);
//UINT32 gen_purpose = dm_read32(cpustate, op_ptr - 4);
UINT32 ext_index = dm_read32(cpustate, op_ptr - 5);
UINT32 ext_modifier = dm_read32(cpustate, op_ptr - 6);
UINT32 ext_count = dm_read32(cpustate, op_ptr - 7);
if (sharc.dmaop_cycles > 0)
if (cpustate->dmaop_cycles > 0)
{
fatalerror("schedule_chained_dma_op: DMA operation already scheduled at %08X!", sharc.pc);
fatalerror("schedule_chained_dma_op: DMA operation already scheduled at %08X!", cpustate->pc);
}
if (chained_direction) // Transmit to external
{
sharc.dmaop_dst = ext_index;
sharc.dmaop_dst_modifier = ext_modifier;
sharc.dmaop_dst_count = ext_count;
sharc.dmaop_src = int_index;
sharc.dmaop_src_modifier = int_modifier;
sharc.dmaop_src_count = int_count;
cpustate->dmaop_dst = ext_index;
cpustate->dmaop_dst_modifier = ext_modifier;
cpustate->dmaop_dst_count = ext_count;
cpustate->dmaop_src = int_index;
cpustate->dmaop_src_modifier = int_modifier;
cpustate->dmaop_src_count = int_count;
}
else // Receive from external
{
sharc.dmaop_src = ext_index;
sharc.dmaop_src_modifier = ext_modifier;
sharc.dmaop_src_count = ext_count;
sharc.dmaop_dst = int_index;
sharc.dmaop_dst_modifier = int_modifier;
sharc.dmaop_dst_count = int_count;
cpustate->dmaop_src = ext_index;
cpustate->dmaop_src_modifier = ext_modifier;
cpustate->dmaop_src_count = ext_count;
cpustate->dmaop_dst = int_index;
cpustate->dmaop_dst_modifier = int_modifier;
cpustate->dmaop_dst_count = int_count;
}
sharc.dmaop_pmode = 0;
sharc.dmaop_channel = channel;
sharc.dmaop_cycles = sharc.dmaop_src_count / 4;
sharc.dmaop_chain_ptr = chain_ptr;
sharc.dmaop_chained_direction = chained_direction;
cpustate->dmaop_pmode = 0;
cpustate->dmaop_channel = channel;
cpustate->dmaop_cycles = cpustate->dmaop_src_count / 4;
cpustate->dmaop_chain_ptr = chain_ptr;
cpustate->dmaop_chained_direction = chained_direction;
}
static void schedule_dma_op(int channel, UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, int src_count, int dst_count, int pmode)
static void schedule_dma_op(SHARC_REGS *cpustate, int channel, UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, int src_count, int dst_count, int pmode)
{
if (sharc.dmaop_cycles > 0)
if (cpustate->dmaop_cycles > 0)
{
fatalerror("schedule_dma_op: DMA operation already scheduled at %08X!", sharc.pc);
fatalerror("schedule_dma_op: DMA operation already scheduled at %08X!", cpustate->pc);
}
sharc.dmaop_channel = channel;
sharc.dmaop_src = src;
sharc.dmaop_dst = dst;
sharc.dmaop_src_modifier = src_modifier;
sharc.dmaop_dst_modifier = dst_modifier;
sharc.dmaop_src_count = src_count;
sharc.dmaop_dst_count = dst_count;
sharc.dmaop_pmode = pmode;
sharc.dmaop_chain_ptr = 0;
sharc.dmaop_cycles = src_count / 4;
cpustate->dmaop_channel = channel;
cpustate->dmaop_src = src;
cpustate->dmaop_dst = dst;
cpustate->dmaop_src_modifier = src_modifier;
cpustate->dmaop_dst_modifier = dst_modifier;
cpustate->dmaop_src_count = src_count;
cpustate->dmaop_dst_count = dst_count;
cpustate->dmaop_pmode = pmode;
cpustate->dmaop_chain_ptr = 0;
cpustate->dmaop_cycles = src_count / 4;
}
static void dma_op(UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, int src_count, int dst_count, int pmode)
static void dma_op(SHARC_REGS *cpustate, UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, int src_count, int dst_count, int pmode)
{
int i;
//printf("dma_op: %08X, %08X, %08X, %08X, %08X, %08X, %d\n", src, dst, src_modifier, dst_modifier, src_count, dst_count, pmode);
@ -80,8 +80,8 @@ static void dma_op(UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, i
{
for (i=0; i < src_count; i++)
{
UINT32 data = dm_read32(src);
dm_write32(dst, data);
UINT32 data = dm_read32(cpustate, src);
dm_write32(cpustate, dst, data);
src += src_modifier;
dst += dst_modifier;
}
@ -92,9 +92,9 @@ static void dma_op(UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, i
int length = src_count/2;
for (i=0; i < length; i++)
{
UINT32 data = ((dm_read32(src+0) & 0xffff) << 16) | (dm_read32(src+1) & 0xffff);
UINT32 data = ((dm_read32(cpustate, src+0) & 0xffff) << 16) | (dm_read32(cpustate, src+1) & 0xffff);
dm_write32(dst, data);
dm_write32(cpustate, dst, data);
src += src_modifier * 2;
dst += dst_modifier;
}
@ -105,14 +105,14 @@ static void dma_op(UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, i
int length = src_count/6;
for (i=0; i < length; i++)
{
UINT64 data = ((UINT64)(dm_read32(src+0) & 0xff) << 0) |
((UINT64)(dm_read32(src+1) & 0xff) << 8) |
((UINT64)(dm_read32(src+2) & 0xff) << 16) |
((UINT64)(dm_read32(src+3) & 0xff) << 24) |
((UINT64)(dm_read32(src+4) & 0xff) << 32) |
((UINT64)(dm_read32(src+5) & 0xff) << 40);
UINT64 data = ((UINT64)(dm_read32(cpustate, src+0) & 0xff) << 0) |
((UINT64)(dm_read32(cpustate, src+1) & 0xff) << 8) |
((UINT64)(dm_read32(cpustate, src+2) & 0xff) << 16) |
((UINT64)(dm_read32(cpustate, src+3) & 0xff) << 24) |
((UINT64)(dm_read32(cpustate, src+4) & 0xff) << 32) |
((UINT64)(dm_read32(cpustate, src+5) & 0xff) << 40);
pm_write48(dst, data);
pm_write48(cpustate, dst, data);
src += src_modifier * 6;
dst += dst_modifier;
}
@ -124,35 +124,35 @@ static void dma_op(UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, i
}
}
if (sharc.dmaop_channel == 6)
if (cpustate->dmaop_channel == 6)
{
sharc.irptl |= (1 << (sharc.dmaop_channel+10));
cpustate->irptl |= (1 << (cpustate->dmaop_channel+10));
/* DMA interrupt */
if (sharc.imask & (1 << (sharc.dmaop_channel+10)))
if (cpustate->imask & (1 << (cpustate->dmaop_channel+10)))
{
sharc.irq_active |= 1 << (sharc.dmaop_channel+10);
cpustate->irq_active |= 1 << (cpustate->dmaop_channel+10);
}
}
}
static void sharc_dma_exec(int channel)
static void sharc_dma_exec(SHARC_REGS *cpustate, int channel)
{
UINT32 src, dst;
UINT32 src_count, dst_count;
UINT32 src_modifier, dst_modifier;
int chen, tran, dtype, pmode, mswf, master, ishake, intio, ext, flsh;
chen = (sharc.dma[channel].control >> 1) & 0x1;
tran = (sharc.dma[channel].control >> 2) & 0x1;
dtype = (sharc.dma[channel].control >> 5) & 0x1;
pmode = (sharc.dma[channel].control >> 6) & 0x3;
mswf = (sharc.dma[channel].control >> 8) & 0x1;
master = (sharc.dma[channel].control >> 9) & 0x1;
ishake = (sharc.dma[channel].control >> 10) & 0x1;
intio = (sharc.dma[channel].control >> 11) & 0x1;
ext = (sharc.dma[channel].control >> 12) & 0x1;
flsh = (sharc.dma[channel].control >> 13) & 0x1;
chen = (cpustate->dma[channel].control >> 1) & 0x1;
tran = (cpustate->dma[channel].control >> 2) & 0x1;
dtype = (cpustate->dma[channel].control >> 5) & 0x1;
pmode = (cpustate->dma[channel].control >> 6) & 0x3;
mswf = (cpustate->dma[channel].control >> 8) & 0x1;
master = (cpustate->dma[channel].control >> 9) & 0x1;
ishake = (cpustate->dma[channel].control >> 10) & 0x1;
intio = (cpustate->dma[channel].control >> 11) & 0x1;
ext = (cpustate->dma[channel].control >> 12) & 0x1;
flsh = (cpustate->dma[channel].control >> 13) & 0x1;
if (ishake)
fatalerror("SHARC: dma_exec: handshake not supported");
@ -163,29 +163,29 @@ static void sharc_dma_exec(int channel)
if (chen) // Chained DMA
{
UINT32 dma_chain_ptr = sharc.dma[channel].chain_ptr & 0x1ffff;
UINT32 dma_chain_ptr = cpustate->dma[channel].chain_ptr & 0x1ffff;
schedule_chained_dma_op(channel, dma_chain_ptr, tran);
schedule_chained_dma_op(cpustate, channel, dma_chain_ptr, tran);
}
else
{
if (tran) // Transmit to external
{
dst = sharc.dma[channel].ext_index;
dst_modifier = sharc.dma[channel].ext_modifier;
dst_count = sharc.dma[channel].ext_count;
src = sharc.dma[channel].int_index;
src_modifier = sharc.dma[channel].int_modifier;
src_count = sharc.dma[channel].int_count;
dst = cpustate->dma[channel].ext_index;
dst_modifier = cpustate->dma[channel].ext_modifier;
dst_count = cpustate->dma[channel].ext_count;
src = cpustate->dma[channel].int_index;
src_modifier = cpustate->dma[channel].int_modifier;
src_count = cpustate->dma[channel].int_count;
}
else // Receive from external
{
src = sharc.dma[channel].ext_index;
src_modifier = sharc.dma[channel].ext_modifier;
src_count = sharc.dma[channel].ext_count;
dst = sharc.dma[channel].int_index;
dst_modifier = sharc.dma[channel].int_modifier;
dst_count = sharc.dma[channel].int_count;
src = cpustate->dma[channel].ext_index;
src_modifier = cpustate->dma[channel].ext_modifier;
src_count = cpustate->dma[channel].ext_count;
dst = cpustate->dma[channel].int_index;
dst_modifier = cpustate->dma[channel].int_modifier;
dst_count = cpustate->dma[channel].int_count;
if (dst < 0x20000)
{
@ -199,6 +199,6 @@ static void sharc_dma_exec(int channel)
pmode = DMA_PMODE_8_48;
}
schedule_dma_op(channel, src, dst, src_modifier, dst_modifier, src_count, dst_count, pmode);
schedule_dma_op(cpustate, channel, src, dst, src_modifier, dst_modifier, src_count, dst_count, pmode);
}
}

96
src/emu/cpu/sharc/sharcmem.c
View File

@ -1,35 +1,35 @@
/* SHARC memory operations */
static UINT32 pm_read32(UINT32 address)
static UINT32 pm_read32(SHARC_REGS *cpustate, UINT32 address)
{
if (address >= 0x20000 && address < 0x28000)
{
UINT32 addr = (address & 0x7fff) * 3;
return (UINT32)(sharc.internal_ram_block0[addr + 0] << 16) |
(sharc.internal_ram_block0[addr + 1]);
return (UINT32)(cpustate->internal_ram_block0[addr + 0] << 16) |
(cpustate->internal_ram_block0[addr + 1]);
}
else if (address >= 0x28000 && address < 0x40000)
{
// block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff
UINT32 addr = (address & 0x7fff) * 3;
return (UINT32)(sharc.internal_ram_block1[addr + 0] << 16) |
(sharc.internal_ram_block1[addr + 1]);
return (UINT32)(cpustate->internal_ram_block1[addr + 0] << 16) |
(cpustate->internal_ram_block1[addr + 1]);
}
else {
fatalerror("SHARC: PM Bus Read %08X at %08X", address, sharc.pc);
fatalerror("SHARC: PM Bus Read %08X at %08X", address, cpustate->pc);
}
}
static void pm_write32(UINT32 address, UINT32 data)
static void pm_write32(SHARC_REGS *cpustate, UINT32 address, UINT32 data)
{
if (address >= 0x20000 && address < 0x28000)
{
UINT32 addr = (address & 0x7fff) * 3;
sharc.internal_ram_block0[addr + 0] = (UINT16)(data >> 16);
sharc.internal_ram_block0[addr + 1] = (UINT16)(data);
cpustate->internal_ram_block0[addr + 0] = (UINT16)(data >> 16);
cpustate->internal_ram_block0[addr + 1] = (UINT16)(data);
return;
}
else if (address >= 0x28000 && address < 0x40000)
@ -37,50 +37,50 @@ static void pm_write32(UINT32 address, UINT32 data)
// block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff
UINT32 addr = (address & 0x7fff) * 3;
sharc.internal_ram_block1[addr + 0] = (UINT16)(data >> 16);
sharc.internal_ram_block1[addr + 1] = (UINT16)(data);
cpustate->internal_ram_block1[addr + 0] = (UINT16)(data >> 16);
cpustate->internal_ram_block1[addr + 1] = (UINT16)(data);
return;
}
else {
fatalerror("SHARC: PM Bus Write %08X, %08X at %08X", address, data, sharc.pc);
fatalerror("SHARC: PM Bus Write %08X, %08X at %08X", address, data, cpustate->pc);
}
}
static UINT64 pm_read48(UINT32 address)
static UINT64 pm_read48(SHARC_REGS *cpustate, UINT32 address)
{
if (address >= 0x20000 && address < 0x28000)
{
UINT32 addr = (address & 0x7fff) * 3;
return ((UINT64)(sharc.internal_ram_block0[addr + 0]) << 32) |
((UINT64)(sharc.internal_ram_block0[addr + 1]) << 16) |
((UINT64)(sharc.internal_ram_block0[addr + 2]) << 0);
return ((UINT64)(cpustate->internal_ram_block0[addr + 0]) << 32) |
((UINT64)(cpustate->internal_ram_block0[addr + 1]) << 16) |
((UINT64)(cpustate->internal_ram_block0[addr + 2]) << 0);
}
else if (address >= 0x28000 && address < 0x40000)
{
// block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff
UINT32 addr = (address & 0x7fff) * 3;
return ((UINT64)(sharc.internal_ram_block1[addr + 0]) << 32) |
((UINT64)(sharc.internal_ram_block1[addr + 1]) << 16) |
((UINT64)(sharc.internal_ram_block1[addr + 2]) << 0);
return ((UINT64)(cpustate->internal_ram_block1[addr + 0]) << 32) |
((UINT64)(cpustate->internal_ram_block1[addr + 1]) << 16) |
((UINT64)(cpustate->internal_ram_block1[addr + 2]) << 0);
}
else {
fatalerror("SHARC: PM Bus Read %08X at %08X", address, sharc.pc);
fatalerror("SHARC: PM Bus Read %08X at %08X", address, cpustate->pc);
}
return 0;
}
static void pm_write48(UINT32 address, UINT64 data)
static void pm_write48(SHARC_REGS *cpustate, UINT32 address, UINT64 data)
{
if (address >= 0x20000 && address < 0x28000)
{
UINT32 addr = (address & 0x7fff) * 3;
sharc.internal_ram_block0[addr + 0] = (UINT16)(data >> 32);
sharc.internal_ram_block0[addr + 1] = (UINT16)(data >> 16);
sharc.internal_ram_block0[addr + 2] = (UINT16)(data);
cpustate->internal_ram_block0[addr + 0] = (UINT16)(data >> 32);
cpustate->internal_ram_block0[addr + 1] = (UINT16)(data >> 16);
cpustate->internal_ram_block0[addr + 2] = (UINT16)(data);
return;
}
else if (address >= 0x28000 && address < 0x40000)
@ -88,36 +88,36 @@ static void pm_write48(UINT32 address, UINT64 data)
// block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff
UINT32 addr = (address & 0x7fff) * 3;
sharc.internal_ram_block1[addr + 0] = (UINT16)(data >> 32);
sharc.internal_ram_block1[addr + 1] = (UINT16)(data >> 16);
sharc.internal_ram_block1[addr + 2] = (UINT16)(data);
cpustate->internal_ram_block1[addr + 0] = (UINT16)(data >> 32);
cpustate->internal_ram_block1[addr + 1] = (UINT16)(data >> 16);
cpustate->internal_ram_block1[addr + 2] = (UINT16)(data);
return;
}
else {
fatalerror("SHARC: PM Bus Write %08X, %04X%08X at %08X", address, (UINT16)(data >> 32),(UINT32)data, sharc.pc);
fatalerror("SHARC: PM Bus Write %08X, %04X%08X at %08X", address, (UINT16)(data >> 32),(UINT32)data, cpustate->pc);
}
}
static UINT32 dm_read32(UINT32 address)
static UINT32 dm_read32(SHARC_REGS *cpustate, UINT32 address)
{
if (address < 0x100)
{
return sharc_iop_r(address);
return sharc_iop_r(cpustate, address);
}
else if (address >= 0x20000 && address < 0x28000)
{
UINT32 addr = (address & 0x7fff) * 2;
return (UINT32)(sharc.internal_ram_block0[addr + 0] << 16) |
(sharc.internal_ram_block0[addr + 1]);
return (UINT32)(cpustate->internal_ram_block0[addr + 0] << 16) |
(cpustate->internal_ram_block0[addr + 1]);
}
else if (address >= 0x28000 && address < 0x40000)
{
// block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff
UINT32 addr = (address & 0x7fff) * 2;
return (UINT32)(sharc.internal_ram_block1[addr + 0] << 16) |
(sharc.internal_ram_block1[addr + 1]);
return (UINT32)(cpustate->internal_ram_block1[addr + 0] << 16) |
(cpustate->internal_ram_block1[addr + 1]);
}
// short word addressing
@ -125,8 +125,8 @@ static UINT32 dm_read32(UINT32 address)
{
UINT32 addr = address & 0xffff;
UINT16 r = sharc.internal_ram_block0[addr ^ 1];
if (sharc.mode1 & 0x4000)
UINT16 r = cpustate->internal_ram_block0[addr ^ 1];
if (cpustate->mode1 & 0x4000)
{
// sign-extend
return (INT32)(INT16)(r);
@ -141,8 +141,8 @@ static UINT32 dm_read32(UINT32 address)
// block 1 is mirrored in 0x50000...5ffff, 0x60000...0x6ffff and 0x70000...7ffff
UINT32 addr = address & 0xffff;
UINT16 r = sharc.internal_ram_block1[addr ^ 1];
if (sharc.mode1 & 0x4000)
UINT16 r = cpustate->internal_ram_block1[addr ^ 1];
if (cpustate->mode1 & 0x4000)
{
// sign-extend
return (INT32)(INT16)(r);
@ -153,22 +153,22 @@ static UINT32 dm_read32(UINT32 address)
}
}
return memory_read_dword_32le(sharc.data, address << 2);
return memory_read_dword_32le(cpustate->data, address << 2);
}
static void dm_write32(UINT32 address, UINT32 data)
static void dm_write32(SHARC_REGS *cpustate, UINT32 address, UINT32 data)
{
if (address < 0x100)
{
sharc_iop_w(address, data);
sharc_iop_w(cpustate, address, data);
return;
}
else if (address >= 0x20000 && address < 0x28000)
{
UINT32 addr = (address & 0x7fff) * 2;
sharc.internal_ram_block0[addr + 0] = (UINT16)(data >> 16);
sharc.internal_ram_block0[addr + 1] = (UINT16)(data);
cpustate->internal_ram_block0[addr + 0] = (UINT16)(data >> 16);
cpustate->internal_ram_block0[addr + 1] = (UINT16)(data);
return;
}
else if (address >= 0x28000 && address < 0x40000)
@ -176,8 +176,8 @@ static void dm_write32(UINT32 address, UINT32 data)
// block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff
UINT32 addr = (address & 0x7fff) * 2;
sharc.internal_ram_block1[addr + 0] = (UINT16)(data >> 16);
sharc.internal_ram_block1[addr + 1] = (UINT16)(data);
cpustate->internal_ram_block1[addr + 0] = (UINT16)(data >> 16);
cpustate->internal_ram_block1[addr + 1] = (UINT16)(data);
return;
}
@ -186,7 +186,7 @@ static void dm_write32(UINT32 address, UINT32 data)
{
UINT32 addr = address & 0xffff;
sharc.internal_ram_block0[addr ^ 1] = data;
cpustate->internal_ram_block0[addr ^ 1] = data;
return;
}
else if (address >= 0x50000 && address < 0x80000)
@ -194,9 +194,9 @@ static void dm_write32(UINT32 address, UINT32 data)
// block 1 is mirrored in 0x50000...5ffff, 0x60000...0x6ffff and 0x70000...7ffff
UINT32 addr = address & 0xffff;
sharc.internal_ram_block1[addr ^ 1] = data;
cpustate->internal_ram_block1[addr ^ 1] = data;
return;
}
memory_write_dword_32le(sharc.data, address << 2, data);
memory_write_dword_32le(cpustate->data, address << 2, data);
}

1602
src/emu/cpu/sharc/sharcops.c
View File

File diff suppressed because it is too large Load Diff

2
src/emu/cpu/sharc/sharcops.h
View File

@ -2,7 +2,7 @@ typedef struct
{
UINT32 op_mask;
UINT32 op_bits;
void (* handler)(void);
void (*handler)(SHARC_REGS *cpustate);
} SHARC_OP;
static const SHARC_OP sharc_opcode_table[] =

54
src/mame/drivers/model2.c
View File

@ -116,15 +116,11 @@ static int copro_fifoin_pop(const device_config *device, UINT32 *result)
{
if (copro_fifoin_num == 0)
{
cpu_push_context(device);
sharc_set_flag_input(0, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(device, 0, ASSERT_LINE);
}
else
{
cpu_push_context(device);
sharc_set_flag_input(0, CLEAR_LINE);
cpu_pop_context();
sharc_set_flag_input(device, 0, CLEAR_LINE);
}
}
@ -154,9 +150,7 @@ static void copro_fifoin_push(const device_config *device, UINT32 data)
// clear FIFO empty flag on SHARC
if (dsp_type == DSP_TYPE_SHARC)
{
cpu_push_context(device);
sharc_set_flag_input(0, CLEAR_LINE);
cpu_pop_context();
sharc_set_flag_input(device, 0, CLEAR_LINE);
}
}
@ -196,15 +190,11 @@ static UINT32 copro_fifoout_pop(const address_space *space)
{
if (copro_fifoout_num == COPRO_FIFOOUT_SIZE)
{
cpu_push_context(Machine->cpu[2]);
sharc_set_flag_input(1, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(space->machine->cpu[2], 1, ASSERT_LINE);
}
else
{
cpu_push_context(Machine->cpu[2]);
sharc_set_flag_input(1, CLEAR_LINE);
cpu_pop_context();
sharc_set_flag_input(space->machine->cpu[2], 1, CLEAR_LINE);
}
}
@ -235,17 +225,13 @@ static void copro_fifoout_push(const device_config *device, UINT32 data)
{
if (copro_fifoout_num == COPRO_FIFOOUT_SIZE)
{
cpu_push_context(device);
sharc_set_flag_input(1, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(device, 1, ASSERT_LINE);
//cpu_set_input_line(device, SHARC_INPUT_FLAG1, ASSERT_LINE);
}
else
{
cpu_push_context(device);
sharc_set_flag_input(1, CLEAR_LINE);
cpu_pop_context();
sharc_set_flag_input(device, 1, CLEAR_LINE);
//cpu_set_input_line(device, SHARC_INPUT_FLAG1, CLEAR_LINE);
}
@ -571,9 +557,7 @@ static WRITE32_HANDLER(copro_fifo_w)
{
if (dsp_type == DSP_TYPE_SHARC)
{
cpu_push_context(space->machine->cpu[2]);
sharc_external_dma_write(model2_coprocnt, data & 0xffff);
cpu_pop_context();
sharc_external_dma_write(space->machine->cpu[2], model2_coprocnt, data & 0xffff);
}
else if (dsp_type == DSP_TYPE_TGP)
{
@ -598,9 +582,7 @@ static WRITE32_HANDLER(copro_sharc_iop_w)
(strcmp(space->machine->gamedrv->name, "vstriker" ) == 0) ||
(strcmp(space->machine->gamedrv->name, "gunblade" ) == 0))
{
cpu_push_context(space->machine->cpu[2]);
sharc_external_iop_write(offset, data);
cpu_pop_context();
sharc_external_iop_write(space->machine->cpu[2], offset, data);
}
else
{
@ -611,9 +593,7 @@ static WRITE32_HANDLER(copro_sharc_iop_w)
else
{
iop_data |= (data & 0xffff) << 16;
cpu_push_context(space->machine->cpu[2]);
sharc_external_iop_write(offset, iop_data);
cpu_pop_context();
sharc_external_iop_write(space->machine->cpu[2], offset, iop_data);
}
iop_write_num++;
}
@ -688,9 +668,7 @@ static WRITE32_HANDLER(geo_sharc_fifo_w)
{
if (model2_geoctl & 0x80000000)
{
cpu_push_context(space->machine->cpu[3]);
sharc_external_dma_write(model2_geocnt, data & 0xffff);
cpu_pop_context();
sharc_external_dma_write(space->machine->cpu[3], model2_geocnt, data & 0xffff);
model2_geocnt++;
}
@ -706,9 +684,7 @@ static WRITE32_HANDLER(geo_sharc_iop_w)
{
if ((strcmp(space->machine->gamedrv->name, "schamp" ) == 0))
{
cpu_push_context(space->machine->cpu[3]);
sharc_external_iop_write(offset, data);
cpu_pop_context();
sharc_external_iop_write(space->machine->cpu[3], offset, data);
}
else
{
@ -719,9 +695,7 @@ static WRITE32_HANDLER(geo_sharc_iop_w)
else
{
geo_iop_data |= (data & 0xffff) << 16;
cpu_push_context(space->machine->cpu[3]);
sharc_external_iop_write(offset, geo_iop_data);
cpu_pop_context();
sharc_external_iop_write(space->machine->cpu[3], offset, geo_iop_data);
}
geo_iop_write_num++;
}
@ -1744,7 +1718,7 @@ static const scsp_interface scsp_config =
static READ32_HANDLER(copro_sharc_input_fifo_r)
{
UINT32 result;
UINT32 result = 0;
//mame_printf_debug("SHARC FIFOIN pop at %08X\n", cpu_get_pc(space->cpu));
copro_fifoin_pop(space->machine->cpu[2], &result);

8
src/mame/drivers/zr107.c
View File

@ -237,9 +237,7 @@ static VIDEO_UPDATE( jetwave )
draw_7segment_led(bitmap, 3, 3, led_reg0);
draw_7segment_led(bitmap, 9, 3, led_reg1);
cpu_push_context(screen->machine->cpu[2]);
sharc_set_flag_input(1, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(screen->machine->cpu[2], 1, ASSERT_LINE);
return 0;
}
@ -293,9 +291,7 @@ static VIDEO_UPDATE( zr107 )
draw_7segment_led(bitmap, 3, 3, led_reg0);
draw_7segment_led(bitmap, 9, 3, led_reg1);
cpu_push_context(screen->machine->cpu[2]);
sharc_set_flag_input(1, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(screen->machine->cpu[2], 1, ASSERT_LINE);
return 0;
}

36
src/mame/machine/konppc.c
View File

@ -225,9 +225,7 @@ static void dsp_comm_sharc_w(const address_space *space, int board, int offset,
case CGBOARD_TYPE_GTICLUB:
{
//cpu_set_input_line(machine->cpu[2], SHARC_INPUT_FLAG0, ASSERT_LINE);
cpu_push_context(space->machine->cpu[2]);
sharc_set_flag_input(0, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(space->machine->cpu[2], 0, ASSERT_LINE);
if (offset == 1)
{
@ -246,9 +244,7 @@ static void dsp_comm_sharc_w(const address_space *space, int board, int offset,
if (data & 0x01 || data & 0x10)
{
cpu_push_context(space->machine->cpu[board == 0 ? 2 : 3]);
sharc_set_flag_input(1, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(space->machine->cpu[board == 0 ? 2 : 3], 1, ASSERT_LINE);
}
if (texture_bank[board] != -1)
@ -359,28 +355,20 @@ static UINT32 nwk_fifo_r(int board)
if (nwk_fifo_read_ptr[board] < nwk_fifo_half_full_r)
{
cpu_push_context(Machine->cpu[cpu]);
sharc_set_flag_input(1, CLEAR_LINE);
cpu_pop_context();
sharc_set_flag_input(Machine->cpu[cpu], 1, CLEAR_LINE);
}
else
{
cpu_push_context(Machine->cpu[cpu]);
sharc_set_flag_input(1, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(Machine->cpu[cpu], 1, ASSERT_LINE);
}
if (nwk_fifo_read_ptr[board] < nwk_fifo_full)
{
cpu_push_context(Machine->cpu[cpu]);
sharc_set_flag_input(2, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(Machine->cpu[cpu], 2, ASSERT_LINE);
}
else
{
cpu_push_context(Machine->cpu[cpu]);
sharc_set_flag_input(2, CLEAR_LINE);
cpu_pop_context();
sharc_set_flag_input(Machine->cpu[cpu], 2, CLEAR_LINE);
}
data = nwk_fifo[board][nwk_fifo_read_ptr[board]];
@ -396,20 +384,14 @@ static void nwk_fifo_w(int board, UINT32 data)
if (nwk_fifo_write_ptr[board] < nwk_fifo_half_full_w)
{
cpu_push_context(Machine->cpu[cpu]);
sharc_set_flag_input(1, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(Machine->cpu[cpu], 1, ASSERT_LINE);
}
else
{
cpu_push_context(Machine->cpu[cpu]);
sharc_set_flag_input(1, CLEAR_LINE);
cpu_pop_context();
sharc_set_flag_input(Machine->cpu[cpu], 1, CLEAR_LINE);
}
cpu_push_context(Machine->cpu[cpu]);
sharc_set_flag_input(2, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(Machine->cpu[cpu], 2, ASSERT_LINE);
nwk_fifo[board][nwk_fifo_write_ptr[board]] = data;
nwk_fifo_write_ptr[board]++;

28
src/mame/video/gticlub.c
View File

@ -317,24 +317,18 @@ READ32_HANDLER( K001005_r )
if (K001005_fifo_read_ptr < 0x3ff)
{
//cpu_set_input_line(space->machine->cpu[2], SHARC_INPUT_FLAG1, CLEAR_LINE);
cpu_push_context(space->machine->cpu[2]);
sharc_set_flag_input(1, CLEAR_LINE);
cpu_pop_context();
sharc_set_flag_input(space->machine->cpu[2], 1, CLEAR_LINE);
}
else
{
//cpu_set_input_line(space->machine->cpu[2], SHARC_INPUT_FLAG1, ASSERT_LINE);
cpu_push_context(space->machine->cpu[2]);
sharc_set_flag_input(1, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(space->machine->cpu[2], 1, ASSERT_LINE);
}
}
else
{
//cpu_set_input_line(space->machine->cpu[2], SHARC_INPUT_FLAG1, ASSERT_LINE);
cpu_push_context(space->machine->cpu[2]);
sharc_set_flag_input(1, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(space->machine->cpu[2], 1, ASSERT_LINE);
}
K001005_fifo_read_ptr++;
@ -376,24 +370,18 @@ WRITE32_HANDLER( K001005_w )
if (K001005_fifo_write_ptr < 0x400)
{
//cpu_set_input_line(space->machine->cpu[2], SHARC_INPUT_FLAG1, ASSERT_LINE);
cpu_push_context(space->machine->cpu[2]);
sharc_set_flag_input(1, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(space->machine->cpu[2], 1, ASSERT_LINE);
}
else
{
//cpu_set_input_line(space->machine->cpu[2], SHARC_INPUT_FLAG1, CLEAR_LINE);
cpu_push_context(space->machine->cpu[2]);
sharc_set_flag_input(1, CLEAR_LINE);
cpu_pop_context();
sharc_set_flag_input(space->machine->cpu[2], 1, CLEAR_LINE);
}
}
else
{
//cpu_set_input_line(space->machine->cpu[2], SHARC_INPUT_FLAG1, ASSERT_LINE);
cpu_push_context(space->machine->cpu[2]);
sharc_set_flag_input(1, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(space->machine->cpu[2], 1, ASSERT_LINE);
}
// mame_printf_debug("K001005 FIFO write: %08X at %08X\n", data, cpu_get_pc(space->cpu));
@ -1059,9 +1047,7 @@ VIDEO_UPDATE( gticlub )
draw_7segment_led(bitmap, 9, 3, gticlub_led_reg1);
//cpu_set_input_line(screen->machine->cpu[2], SHARC_INPUT_FLAG1, ASSERT_LINE);
cpu_push_context(screen->machine->cpu[2]);
sharc_set_flag_input(1, ASSERT_LINE);
cpu_pop_context();
sharc_set_flag_input(screen->machine->cpu[2], 1, ASSERT_LINE);
return 0;
}