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m680x0: Rely on the opcode tables for cpu filtering, ban "return" from opcode handlers, restyle [O. Galibert]
This commit is contained in:
Olivier Galibert
parent
132e64cfd9
commit
f759f41db9
@ -107,7 +107,7 @@ public:
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void autovectors_map(address_map &map);
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protected:
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static constexpr int NUM_CPU_TYPES = 7;
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static constexpr int NUM_CPU_TYPES = 8;
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typedef void (m68000_base_device::*opcode_handler_ptr)();
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static u16 m68ki_instruction_state_table[NUM_CPU_TYPES][0x10000]; /* opcode handler state numbers */
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File diff suppressed because it is too large
Load Diff
@ -78,7 +78,7 @@ const u32 m68000_base_device::m68ki_shift_32_table[65] =
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/* Number of clock cycles to use for exception processing.
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* I used 4 for any vectors that are undocumented for processing times.
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*/
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const u8 m68000_base_device::m68ki_exception_cycle_table[7][256] =
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const u8 m68000_base_device::m68ki_exception_cycle_table[NUM_CPU_TYPES][256] =
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{
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{ /* 000 */
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40, /* 0: Reset - Initial Stack Pointer */
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@ -153,6 +153,79 @@ const u8 m68000_base_device::m68ki_exception_cycle_table[7][256] =
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4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
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4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4
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},
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{ /* 070 - not even pretending to be correct */
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40, /* 0: Reset - Initial Stack Pointer */
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4, /* 1: Reset - Initial Program Counter */
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126, /* 2: Bus Error (unemulated) */
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126, /* 3: Address Error (unemulated) */
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38, /* 4: Illegal Instruction */
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44, /* 5: Divide by Zero */
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44, /* 6: CHK */
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34, /* 7: TRAPV */
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38, /* 8: Privilege Violation */
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38, /* 9: Trace */
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4, /* 10: 1010 */
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4, /* 11: 1111 */
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4, /* 12: RESERVED */
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4, /* 13: Coprocessor Protocol Violation (unemulated) */
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4, /* 14: Format Error */
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44, /* 15: Uninitialized Interrupt */
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4, /* 16: RESERVED */
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4, /* 17: RESERVED */
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4, /* 18: RESERVED */
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4, /* 19: RESERVED */
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4, /* 20: RESERVED */
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4, /* 21: RESERVED */
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4, /* 22: RESERVED */
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4, /* 23: RESERVED */
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46, /* 24: Spurious Interrupt */
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46, /* 25: Level 1 Interrupt Autovector */
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46, /* 26: Level 2 Interrupt Autovector */
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46, /* 27: Level 3 Interrupt Autovector */
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46, /* 28: Level 4 Interrupt Autovector */
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46, /* 29: Level 5 Interrupt Autovector */
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46, /* 30: Level 6 Interrupt Autovector */
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46, /* 31: Level 7 Interrupt Autovector */
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38, /* 32: TRAP #0 */
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38, /* 33: TRAP #1 */
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38, /* 34: TRAP #2 */
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38, /* 35: TRAP #3 */
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38, /* 36: TRAP #4 */
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38, /* 37: TRAP #5 */
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38, /* 38: TRAP #6 */
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38, /* 39: TRAP #7 */
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38, /* 40: TRAP #8 */
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38, /* 41: TRAP #9 */
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38, /* 42: TRAP #10 */
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38, /* 43: TRAP #11 */
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38, /* 44: TRAP #12 */
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38, /* 45: TRAP #13 */
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38, /* 46: TRAP #14 */
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38, /* 47: TRAP #15 */
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4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */
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4, /* 49: FP Inexact Result (unemulated) */
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4, /* 50: FP Divide by Zero (unemulated) */
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4, /* 51: FP Underflow (unemulated) */
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4, /* 52: FP Operand Error (unemulated) */
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4, /* 53: FP Overflow (unemulated) */
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4, /* 54: FP Signaling NAN (unemulated) */
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4, /* 55: FP Unimplemented Data Type (unemulated) */
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4, /* 56: MMU Configuration Error (unemulated) */
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4, /* 57: MMU Illegal Operation Error (unemulated) */
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4, /* 58: MMU Access Level Violation Error (unemulated) */
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4, /* 59: RESERVED */
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4, /* 60: RESERVED */
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4, /* 61: RESERVED */
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4, /* 62: RESERVED */
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4, /* 63: RESERVED */
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/* 64-255: User Defined */
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4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
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4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
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4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
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4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
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4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
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4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4
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},
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{ /* 010 */
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40, /* 0: Reset - Initial Stack Pointer */
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4, /* 1: Reset - Initial Program Counter */
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@ -1722,9 +1795,9 @@ void m68000_base_device::init_cpu_m68010(void)
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init16(*m_program, *m_oprogram);
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m_sr_mask = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */
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m_state_table = m68ki_instruction_state_table[1];
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m_cyc_instruction = m68ki_cycles[1];
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m_cyc_exception = m68ki_exception_cycle_table[1];
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m_state_table = m68ki_instruction_state_table[2];
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m_cyc_instruction = m68ki_cycles[2];
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m_cyc_exception = m68ki_exception_cycle_table[2];
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m_cyc_bcc_notake_b = -4;
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m_cyc_bcc_notake_w = 0;
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m_cyc_dbcc_f_noexp = 0;
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@ -1748,9 +1821,9 @@ void m68000_base_device::init_cpu_m68020(void)
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init32(*m_program, *m_oprogram);
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m_sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
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m_state_table = m68ki_instruction_state_table[2];
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m_cyc_instruction = m68ki_cycles[2];
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m_cyc_exception = m68ki_exception_cycle_table[2];
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m_state_table = m68ki_instruction_state_table[3];
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m_cyc_instruction = m68ki_cycles[3];
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m_cyc_exception = m68ki_exception_cycle_table[3];
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m_cyc_bcc_notake_b = -2;
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m_cyc_bcc_notake_w = 0;
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m_cyc_dbcc_f_noexp = 0;
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@ -1804,9 +1877,9 @@ void m68000_base_device::init_cpu_m68ec020(void)
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init32(*m_program, *m_oprogram);
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m_sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
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m_state_table = m68ki_instruction_state_table[2];
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m_cyc_instruction = m68ki_cycles[2];
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m_cyc_exception = m68ki_exception_cycle_table[2];
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m_state_table = m68ki_instruction_state_table[3];
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m_cyc_instruction = m68ki_cycles[3];
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m_cyc_exception = m68ki_exception_cycle_table[3];
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m_cyc_bcc_notake_b = -2;
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m_cyc_bcc_notake_w = 0;
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m_cyc_dbcc_f_noexp = 0;
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@ -1832,9 +1905,9 @@ void m68000_base_device::init_cpu_m68030(void)
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init32mmu(*m_program, *m_oprogram);
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m_sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
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m_state_table = m68ki_instruction_state_table[3];
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m_cyc_instruction = m68ki_cycles[3];
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m_cyc_exception = m68ki_exception_cycle_table[3];
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m_state_table = m68ki_instruction_state_table[4];
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m_cyc_instruction = m68ki_cycles[4];
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m_cyc_exception = m68ki_exception_cycle_table[4];
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m_cyc_bcc_notake_b = -2;
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m_cyc_bcc_notake_w = 0;
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m_cyc_dbcc_f_noexp = 0;
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@ -1861,9 +1934,9 @@ void m68000_base_device::init_cpu_m68ec030(void)
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init32(*m_program, *m_oprogram);
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m_sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
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m_state_table = m68ki_instruction_state_table[3];
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m_cyc_instruction = m68ki_cycles[3];
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m_cyc_exception = m68ki_exception_cycle_table[3];
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m_state_table = m68ki_instruction_state_table[4];
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m_cyc_instruction = m68ki_cycles[4];
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m_cyc_exception = m68ki_exception_cycle_table[4];
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m_cyc_bcc_notake_b = -2;
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m_cyc_bcc_notake_w = 0;
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m_cyc_dbcc_f_noexp = 0;
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@ -1890,9 +1963,9 @@ void m68000_base_device::init_cpu_m68040(void)
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init32mmu(*m_program, *m_oprogram);
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m_sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
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m_state_table = m68ki_instruction_state_table[4];
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m_cyc_instruction = m68ki_cycles[4];
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m_cyc_exception = m68ki_exception_cycle_table[4];
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m_state_table = m68ki_instruction_state_table[5];
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m_cyc_instruction = m68ki_cycles[5];
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m_cyc_exception = m68ki_exception_cycle_table[5];
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m_cyc_bcc_notake_b = -2;
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m_cyc_bcc_notake_w = 0;
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m_cyc_dbcc_f_noexp = 0;
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@ -1918,9 +1991,9 @@ void m68000_base_device::init_cpu_m68ec040(void)
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init32(*m_program, *m_oprogram);
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m_sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
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m_state_table = m68ki_instruction_state_table[4];
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m_cyc_instruction = m68ki_cycles[4];
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m_cyc_exception = m68ki_exception_cycle_table[4];
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m_state_table = m68ki_instruction_state_table[5];
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m_cyc_instruction = m68ki_cycles[5];
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m_cyc_exception = m68ki_exception_cycle_table[5];
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m_cyc_bcc_notake_b = -2;
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m_cyc_bcc_notake_w = 0;
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m_cyc_dbcc_f_noexp = 0;
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@ -1946,9 +2019,9 @@ void m68000_base_device::init_cpu_m68lc040(void)
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init32mmu(*m_program, *m_oprogram);
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m_sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
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m_state_table = m68ki_instruction_state_table[4];
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m_cyc_instruction = m68ki_cycles[4];
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m_cyc_exception = m68ki_exception_cycle_table[4];
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m_state_table = m68ki_instruction_state_table[5];
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m_cyc_instruction = m68ki_cycles[5];
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m_cyc_exception = m68ki_exception_cycle_table[5];
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m_cyc_bcc_notake_b = -2;
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m_cyc_bcc_notake_w = 0;
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m_cyc_dbcc_f_noexp = 0;
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@ -1973,7 +2046,7 @@ void m68000_base_device::init_cpu_scc68070(void)
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// TODO: most of this is subtly different
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init16(*m_program, *m_oprogram);
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m_sr_mask = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */
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m_jump_table = m68ki_instruction_jump_table[1];
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m_state_table = m68ki_instruction_state_table[1];
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m_cyc_instruction = m68ki_cycles[1];
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m_cyc_exception = m68ki_exception_cycle_table[1];
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m_cyc_bcc_notake_b = -4;
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@ -2001,9 +2074,9 @@ void m68000_base_device::init_cpu_fscpu32(void)
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init32(*m_program, *m_oprogram);
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m_sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
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m_state_table = m68ki_instruction_state_table[5];
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m_cyc_instruction = m68ki_cycles[5];
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m_cyc_exception = m68ki_exception_cycle_table[5];
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m_state_table = m68ki_instruction_state_table[6];
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m_cyc_instruction = m68ki_cycles[6];
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m_cyc_exception = m68ki_exception_cycle_table[6];
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m_cyc_bcc_notake_b = -2;
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m_cyc_bcc_notake_w = 0;
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m_cyc_dbcc_f_noexp = 0;
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@ -2028,9 +2101,9 @@ void m68000_base_device::init_cpu_coldfire(void)
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init32(*m_program, *m_oprogram);
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m_sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
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m_state_table = m68ki_instruction_state_table[6];
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m_cyc_instruction = m68ki_cycles[6];
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m_cyc_exception = m68ki_exception_cycle_table[6];
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m_state_table = m68ki_instruction_state_table[7];
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m_cyc_instruction = m68ki_cycles[7];
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m_cyc_exception = m68ki_exception_cycle_table[7];
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m_cyc_bcc_notake_b = -2;
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m_cyc_bcc_notake_w = 0;
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m_cyc_dbcc_f_noexp = 0;
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@ -467,7 +467,7 @@ void m68k_cause_bus_error();
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static const u8 m68ki_shift_8_table[65];
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static const u16 m68ki_shift_16_table[65];
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static const u32 m68ki_shift_32_table[65];
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static const u8 m68ki_exception_cycle_table[7][256];
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static const u8 m68ki_exception_cycle_table[8][256];
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static const u8 m68ki_ea_idx_cycle_table[64];
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/* ======================================================================== */
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@ -9,15 +9,16 @@ import sys
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import copy
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CPU_000 = 0
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CPU_010 = 1
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CPU_020 = 2
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CPU_030 = 3
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CPU_040 = 4
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CPU_FSCPU32 = 5
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CPU_COLDFIRE = 6
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CPU_COUNT = 7
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CPU_070 = 1
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CPU_010 = 2
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CPU_020 = 3
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CPU_030 = 4
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CPU_040 = 5
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CPU_FSCPU32 = 6
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CPU_COLDFIRE = 7
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CPU_COUNT = 8
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cpu_names = '01234fc'
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cpu_names = '071234fc'
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cc_table_up = [ "T", "F", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" ]
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cc_table_dn = [ "t", "f", "hi", "ls", "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi", "ge", "lt", "gt", "le" ]
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@ -31,19 +32,19 @@ cc_table_dn = [ "t", "f", "hi", "ls", "cc", "cs", "ne", "eq", "vc", "vs", "pl",
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#
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# 000 010 020 030 040 FSCPU32 Coldfire
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ea_cycle_table = {
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'none' : [[ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0]],
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'ai' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]],
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'pi' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]],
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'pi7' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]],
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'pd' : [[ 0, 6, 10], [ 0, 6, 10], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]],
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'pd7' : [[ 0, 6, 10], [ 0, 6, 10], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]],
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'di' : [[ 0, 8, 12], [ 0, 8, 12], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]],
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'ix' : [[ 0, 10, 14], [ 0, 10, 14], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 0, 0]],
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'aw' : [[ 0, 8, 12], [ 0, 8, 12], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]],
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'al' : [[ 0, 12, 16], [ 0, 12, 16], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]],
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'pcdi' : [[ 0, 8, 12], [ 0, 8, 12], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]],
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'pcix' : [[ 0, 10, 14], [ 0, 10, 14], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 0, 0]],
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'i' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 2, 4], [ 0, 2, 4], [ 0, 2, 4], [ 0, 2, 4], [ 0, 0, 0]],
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'none' : [[ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0]],
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'ai' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]],
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'pi' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]],
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'pi7' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]],
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'pd' : [[ 0, 6, 10], [ 0, 6, 10], [ 0, 6, 10], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]],
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'pd7' : [[ 0, 6, 10], [ 0, 6, 10], [ 0, 6, 10], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]],
|
||||
'di' : [[ 0, 8, 12], [ 0, 8, 12], [ 0, 8, 12], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]],
|
||||
'ix' : [[ 0, 10, 14], [ 0, 10, 14], [ 0, 10, 14], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 0, 0]],
|
||||
'aw' : [[ 0, 8, 12], [ 0, 8, 12], [ 0, 8, 12], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]],
|
||||
'al' : [[ 0, 12, 16], [ 0, 12, 16], [ 0, 12, 16], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]],
|
||||
'pcdi' : [[ 0, 8, 12], [ 0, 8, 12], [ 0, 8, 12], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]],
|
||||
'pcix' : [[ 0, 10, 14], [ 0, 10, 14], [ 0, 10, 14], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 0, 0]],
|
||||
'i' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 8], [ 0, 2, 4], [ 0, 2, 4], [ 0, 2, 4], [ 0, 2, 4], [ 0, 0, 0]],
|
||||
}
|
||||
|
||||
jmp_jsr_cycle_table = { 'none': 0, 'ai': 4, 'pi': 0, 'pi7': 0, 'pd': 0, 'pd7': 0, 'di': 6, 'ix': 10, 'aw': 6, 'al': 8, 'pcdi': 6, 'pcix': 10, 'i': 0 }
|
||||
@ -184,7 +185,7 @@ class OpcodeHandler:
|
||||
self.cycles[i] = op.cycles[i] + moves_cycle_table[ea_mode][size_order]
|
||||
elif i == CPU_010 and op.name == 'clr':
|
||||
self.cycles[i] = op.cycles[i] + clr_cycle_table[ea_mode][size_order]
|
||||
elif i == CPU_000 and (ea_mode == 'i' or ea_mode == 'none') and op.size == 'l' and ((op.cycles[i] == 6 and (op.name == 'add' or op.name == 'and' or op.name == 'or' or op.name == 'sub')) or op.name == 'adda' or op.name == 'suba'):
|
||||
elif (i == CPU_000 or i == CPU_070) and (ea_mode == 'i' or ea_mode == 'none') and op.size == 'l' and ((op.cycles[i] == 6 and (op.name == 'add' or op.name == 'and' or op.name == 'or' or op.name == 'sub')) or op.name == 'adda' or op.name == 'suba'):
|
||||
self.cycles[i] = op.cycles[i] + ea_cycle_table[ea_mode][i][size_order] + 2
|
||||
elif i < CPU_020 and (op.name == 'jmp' or op.name == 'jsr'):
|
||||
self.cycles[i] = op.cycles[i] + jmp_jsr_cycle_table[ea_mode]
|
||||
@ -267,7 +268,7 @@ class Info:
|
||||
for id in order:
|
||||
oh = self.opcode_handlers[id]
|
||||
f.write("\t&m68000_base_device::%s,\n" % oh.function_name)
|
||||
if oh.function_name == 'm68k_op_illegal_0':
|
||||
if oh.function_name == 'x4afc_illegal_' + cpu_names:
|
||||
illegal_id = nid
|
||||
nid += 1
|
||||
f.write("};\n\n")
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user