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Merge pull request #601 from bmunger/r9751

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r9751: Added more dma registers for serial and floppy
This commit is contained in:
Vas Crabb 2016-02-03 15:15:36 +11:00
commit f80737595e
1 changed files with 115 additions and 65 deletions
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174
src/mame/drivers/r9751.cpp
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@ -67,6 +67,8 @@ public:
DECLARE_READ32_MEMBER(r9751_mmio_5ff_r); DECLARE_READ32_MEMBER(r9751_mmio_5ff_r);
DECLARE_WRITE32_MEMBER(r9751_mmio_5ff_w); DECLARE_WRITE32_MEMBER(r9751_mmio_5ff_w);
DECLARE_READ32_MEMBER(r9751_mmio_ff01_r);
DECLARE_WRITE32_MEMBER(r9751_mmio_ff01_w);
DECLARE_READ32_MEMBER(r9751_mmio_ff05_r); DECLARE_READ32_MEMBER(r9751_mmio_ff05_r);
DECLARE_WRITE32_MEMBER(r9751_mmio_ff05_w); DECLARE_WRITE32_MEMBER(r9751_mmio_ff05_w);
DECLARE_READ32_MEMBER(r9751_mmio_fff8_r); DECLARE_READ32_MEMBER(r9751_mmio_fff8_r);
@ -90,6 +92,8 @@ private:
UINT32 fdd_dest_address; // 5FF080B0 UINT32 fdd_dest_address; // 5FF080B0
UINT32 fdd_cmd_complete; UINT32 fdd_cmd_complete;
UINT32 smioc_out_addr; UINT32 smioc_out_addr;
UINT32 smioc_dma_bank;
UINT32 fdd_dma_bank;
attotime timer_32khz_last; attotime timer_32khz_last;
// End registers // End registers
@ -110,12 +114,16 @@ UINT32 r9751_state::swap_uint32( UINT32 val )
READ8_MEMBER(r9751_state::pdc_dma_r) READ8_MEMBER(r9751_state::pdc_dma_r)
{ {
return m_maincpu->space(AS_PROGRAM).read_byte(offset); /* This callback function takes the value written to 0xFF01000C as the bank offset */
UINT32 address = (fdd_dma_bank & 0x7FFFF800) + (offset&0xFFFF);
return m_maincpu->space(AS_PROGRAM).read_byte(address);
} }
WRITE8_MEMBER(r9751_state::pdc_dma_w) WRITE8_MEMBER(r9751_state::pdc_dma_w)
{ {
m_maincpu->space(AS_PROGRAM).write_byte(m_pdc->fdd_68k_dma_address,data); /* This callback function takes the value written to 0xFF01000C as the bank offset */
UINT32 address = (fdd_dma_bank & 0x7FFFF800) + (data&0xFFFF);
m_maincpu->space(AS_PROGRAM).write_byte(m_pdc->fdd_68k_dma_address,address);
} }
DRIVER_INIT_MEMBER(r9751_state,r9751) DRIVER_INIT_MEMBER(r9751_state,r9751)
@ -123,9 +131,10 @@ DRIVER_INIT_MEMBER(r9751_state,r9751)
reg_ff050004 = 0; reg_ff050004 = 0;
reg_fff80040 = 0; reg_fff80040 = 0;
fdd_dest_address = 0; fdd_dest_address = 0;
// fdd_scsi_command = 0;
fdd_cmd_complete = 0; fdd_cmd_complete = 0;
fdd_dma_bank = 0;
smioc_out_addr = 0; smioc_out_addr = 0;
smioc_dma_bank = 0;
m_mem = &m_maincpu->space(AS_PROGRAM); m_mem = &m_maincpu->space(AS_PROGRAM);
} }
@ -147,32 +156,31 @@ void r9751_state::machine_reset()
READ32_MEMBER( r9751_state::r9751_mmio_5ff_r ) READ32_MEMBER( r9751_state::r9751_mmio_5ff_r )
{ {
UINT32 data; UINT32 data;
UINT32 address = offset * 4 + 0x5FF00000;
switch(address) switch(offset << 2)
{ {
/* PDC HDD region (0x24, device 9) */ /* PDC HDD region (0x24, device 9) */
case 0x5FF00824: /* HDD Command result code */ case 0x0824: /* HDD Command result code */
return 0x10; return 0x10;
case 0x5FF03024: /* HDD SCSI command completed successfully */ case 0x3024: /* HDD SCSI command completed successfully */
data = 0x1; data = 0x1;
if(TRACE_HDC) logerror("SCSI HDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address); if(TRACE_HDC) logerror("SCSI HDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
return data; return data;
/* SMIOC region (0x98, device 26) */ /* SMIOC region (0x98, device 26) */
case 0x5FF00898: /* Serial status or DMA status */ case 0x0898: /* Serial status or DMA status */
return 0x40; return 0x40;
/* PDC FDD region (0xB0, device 44 */ /* PDC FDD region (0xB0, device 44 */
case 0x5FF008B0: /* FDD Command result code */ case 0x08B0: /* FDD Command result code */
return 0x10; return 0x10;
case 0x5FF010B0: /* Clear 5FF030B0 ?? */ case 0x10B0: /* Clear 5FF030B0 ?? */
if(TRACE_FDC) logerror("--- FDD 0x5FF010B0 READ (0)\n"); if(TRACE_FDC) logerror("--- FDD 0x5FF010B0 READ (0)\n");
return 0; return 0;
case 0x5FF030B0: /* FDD command completion status */ case 0x30B0: /* FDD command completion status */
data = (m_pdc->reg_p5 << 8) + m_pdc->reg_p4; data = (m_pdc->reg_p5 << 8) + m_pdc->reg_p4;
if(TRACE_FDC) logerror("--- SCSI FDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address); if(TRACE_FDC) logerror("--- SCSI FDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
return data; return data;
default: default:
if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, 0, mem_mask); if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000, 0, mem_mask);
return 0; return 0;
} }
} }
@ -180,47 +188,55 @@ READ32_MEMBER( r9751_state::r9751_mmio_5ff_r )
WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w ) WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
{ {
UINT8 data_b0, data_b1; UINT8 data_b0, data_b1;
UINT32 address = offset * 4 + 0x5FF00000; /* Unknown mask */
if (mem_mask != 0xFFFFFFFF)
logerror("Mask found: %08X Register: %08X PC: %08X\n", mem_mask, offset << 2 | 0x5FF00000, space.machine().firstcpu->pc());
switch(address) switch(offset << 2)
{ {
/* PDC HDD region (0x24, device 9 */ /* PDC HDD region (0x24, device 9 */
case 0x5FF00224: /* HDD SCSI read command */ case 0x0224: /* HDD SCSI read command */
if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address); if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
break; break;
case 0x5FF08024: /* HDD SCSI read command */ case 0x8024: /* HDD SCSI read command */
if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address); if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
break; break;
case 0x5FF0C024: /* HDD SCSI read command */ case 0xC024: /* HDD SCSI read command */
if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address); if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
break; break;
/* SMIOC region (0x98, device 26) */ /* SMIOC region (0x98, device 26) */
case 0x5FF04098: /* Serial DMA Command */ case 0x4098: /* Serial DMA Command */
switch(data) switch(data)
{ {
case 0x4100: /* Send byte to serial */ case 0x4100: /* Send byte to serial */
if(TRACE_SMIOC) logerror("Serial byte: %02X\n", m_mem->read_dword(smioc_out_addr)); if(TRACE_SMIOC) logerror("Serial byte: %02X PC: %08X\n", m_mem->read_dword(smioc_out_addr), space.machine().firstcpu->pc());
m_terminal->write(space,0,m_mem->read_dword(smioc_out_addr)); m_terminal->write(space,0,m_mem->read_dword(smioc_out_addr));
break; break;
default: default:
if(TRACE_SMIOC) logerror("Uknown serial DMA command: %X\n", data); if(TRACE_SMIOC) logerror("Uknown serial DMA command: %X\n", data);
} }
break; break;
case 0x5FF0C098: /* Serial DMA output address */ case 0xC098: /* Serial DMA output address */
smioc_out_addr = data * 2; //smioc_out_addr = data * 2;
smioc_out_addr = (smioc_dma_bank & 0x7FFFF800) | ((data&0x3FF)<<1);
if(TRACE_SMIOC) logerror("Serial output address: %08X PC: %08X\n", smioc_out_addr, space.machine().firstcpu->pc());
break; break;
/* PDC FDD region (0xB0, device 44 */ /* PDC FDD region (0xB0, device 44 */
case 0x5FF001B0: /* FDD SCSI read command */ case 0x01B0: /* FDD SCSI read command */
if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address); if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
break; break;
case 0x5FF002B0: /* FDD SCSI read command */ case 0x02B0: /* FDD SCSI read command */
if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address); if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
break; break;
case 0x5FF008B0: /* FDD SCSI read command */ case 0x04B0: /* FDD RESET PDC */
if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address); if(TRACE_FDC) logerror("PDC RESET, PC: %08X\n", space.machine().firstcpu->pc());
m_pdc->reset();
break; break;
case 0x5FF041B0: /* Unknown - Probably old style commands */ case 0x08B0: /* FDD SCSI read command */
if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address); if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
break;
case 0x41B0: /* Unknown - Probably old style commands */
if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
/* Clear FDD Command completion status 0x5FF030B0 (PDC 0x4, 0x5) */ /* Clear FDD Command completion status 0x5FF030B0 (PDC 0x4, 0x5) */
m_pdc->reg_p4 = 0; m_pdc->reg_p4 = 0;
@ -233,7 +249,7 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
m_pdc->reg_p38 |= 0x2; /* Set bit 1 on port 38 register, PDC polls this port looking for a command */ m_pdc->reg_p38 |= 0x2; /* Set bit 1 on port 38 register, PDC polls this port looking for a command */
if(TRACE_FDC) logerror("--- FDD Old Command: %02X and %02X\n", data_b0, data_b1); if(TRACE_FDC) logerror("--- FDD Old Command: %02X and %02X\n", data_b0, data_b1);
break; break;
case 0x5FF080B0: /* fdd_dest_address register */ case 0x80B0: /* fdd_dest_address register */
fdd_dest_address = data << 1; fdd_dest_address = data << 1;
if(TRACE_FDC) logerror("--- FDD destination address: %08X\n", fdd_dest_address); if(TRACE_FDC) logerror("--- FDD destination address: %08X\n", fdd_dest_address);
data_b0 = data & 0xFF; data_b0 = data & 0xFF;
@ -241,8 +257,8 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
m_pdc->reg_p6 = data_b0; m_pdc->reg_p6 = data_b0;
m_pdc->reg_p7 = data_b1; m_pdc->reg_p7 = data_b1;
break; break;
case 0x5FF0C0B0: case 0xC0B0:
case 0x5FF0C1B0: /* FDD command address register */ case 0xC1B0: /* FDD command address register */
UINT32 fdd_scsi_command; UINT32 fdd_scsi_command;
UINT32 fdd_scsi_command2; UINT32 fdd_scsi_command2;
unsigned char c_fdd_scsi_command[8]; // Array for SCSI command unsigned char c_fdd_scsi_command[8]; // Array for SCSI command
@ -281,55 +297,87 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
break; break;
default: default:
if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask); if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000, data, mem_mask);
} }
} }
/****************************************************************************** /******************************************************************************
CPU board registers [0xFF050000 - 0xFF06FFFF] CPU board registers [0xFF010000 - 0xFF06FFFF]
******************************************************************************/ ******************************************************************************/
READ32_MEMBER( r9751_state::r9751_mmio_ff01_r )
{
//UINT32 data;
switch(offset << 2)
{
default:
//return data;
return 0;
}
}
WRITE32_MEMBER( r9751_state::r9751_mmio_ff01_w )
{
/* Unknown mask */
if (mem_mask != 0xFFFFFFFF)
logerror("Mask found: %08X Register: %08X PC: %08X\n", mem_mask, offset << 2 | 0xFF010000, space.machine().firstcpu->pc());
switch(offset << 2)
{
case 0x000C: /* FDD DMA Offset */
fdd_dma_bank = data;
return;
case 0x0010: /* SMIOC DMA Offset */
smioc_dma_bank = data;
return;
default:
return;
}
}
READ32_MEMBER( r9751_state::r9751_mmio_ff05_r ) READ32_MEMBER( r9751_state::r9751_mmio_ff05_r )
{ {
UINT32 data; UINT32 data;
UINT32 address = offset * 4 + 0xFF050000;
switch(address) switch(offset << 2)
{ {
case 0xFF050004: case 0x0004:
return reg_ff050004; return reg_ff050004;
case 0xFF050300: case 0x0300:
return 0x1B | (1<<0x14); return 0x1B | (1<<0x14);
case 0xFF050320: /* Some type of counter */ case 0x0320: /* Some type of counter */
return (machine().time() - timer_32khz_last).as_ticks(32768) & 0xFFFF; return (machine().time() - timer_32khz_last).as_ticks(32768) & 0xFFFF;
case 0xFF050584: case 0x0584:
return 0; return 0;
case 0xFF050610: case 0x0610:
return 0xabacabac; return 0xabacabac;
case 0xFF060014: case 0x0014:
return 0x80; return 0x80;
default: default:
data = 0; data = 0;
if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask); if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0xFF050000, data, mem_mask);
return data; return data;
} }
} }
WRITE32_MEMBER( r9751_state::r9751_mmio_ff05_w ) WRITE32_MEMBER( r9751_state::r9751_mmio_ff05_w )
{ {
UINT32 address = offset * 4 + 0xFF050000; /* Unknown mask */
if (mem_mask != 0xFFFFFFFF)
logerror("Mask found: %08X Register: %08X PC: %08X\n", mem_mask, offset << 2 | 0xFF050000, space.machine().firstcpu->pc());
switch(address) switch(offset << 2)
{ {
case 0xFF050004: case 0x0004:
reg_ff050004 = data; reg_ff050004 = data;
return; return;
case 0xFF05000C: /* CPU LED hex display indicator */ case 0x000C: /* CPU LED hex display indicator */
if(TRACE_LED) logerror("\n*** LED: %02x, Instruction: %08x ***\n\n", data, space.machine().firstcpu->pc()); if(TRACE_LED) logerror("\n*** LED: %02x, Instruction: %08x ***\n\n", data, space.machine().firstcpu->pc());
return; return;
case 0xFF050320: case 0x0320:
timer_32khz_last = machine().time(); timer_32khz_last = machine().time();
default: default:
if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask); if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0xFF050000, data, mem_mask);
return; return;
} }
} }
@ -337,30 +385,31 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_ff05_w )
READ32_MEMBER( r9751_state::r9751_mmio_fff8_r ) READ32_MEMBER( r9751_state::r9751_mmio_fff8_r )
{ {
UINT32 data; UINT32 data;
UINT32 address = offset * 4 + 0xFFF80000;
switch(address) switch(offset << 2)
{ {
case 0xFFF80040: case 0x0040:
return reg_fff80040; return reg_fff80040;
default: default:
data = 0; data = 0;
if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask); if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0xFFF80000, data, mem_mask);
return data; return data;
} }
} }
WRITE32_MEMBER( r9751_state::r9751_mmio_fff8_w ) WRITE32_MEMBER( r9751_state::r9751_mmio_fff8_w )
{ {
UINT32 address = offset * 4 + 0xFFF80000; /* Unknown mask */
if (mem_mask != 0xFFFFFFFF)
logerror("Mask found: %08X Register: %08X PC: %08X\n", mem_mask, offset << 2 | 0xFFF80000, space.machine().firstcpu->pc());
switch(address) switch(offset << 2)
{ {
case 0xFFF80040: case 0x0040:
reg_fff80040 = data; reg_fff80040 = data;
return; return;
default: default:
if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask); if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0xFFF80000, data, mem_mask);
} }
} }
@ -373,6 +422,7 @@ static ADDRESS_MAP_START(r9751_mem, AS_PROGRAM, 32, r9751_state)
AM_RANGE(0x00000000,0x00ffffff) AM_RAM AM_SHARE("main_ram") // 16MB AM_RANGE(0x00000000,0x00ffffff) AM_RAM AM_SHARE("main_ram") // 16MB
AM_RANGE(0x08000000,0x0800ffff) AM_ROM AM_REGION("prom", 0) AM_RANGE(0x08000000,0x0800ffff) AM_ROM AM_REGION("prom", 0)
AM_RANGE(0x5FF00000,0x5FFFFFFF) AM_READWRITE(r9751_mmio_5ff_r, r9751_mmio_5ff_w) AM_RANGE(0x5FF00000,0x5FFFFFFF) AM_READWRITE(r9751_mmio_5ff_r, r9751_mmio_5ff_w)
AM_RANGE(0xFF010000,0xFF01FFFF) AM_READWRITE(r9751_mmio_ff01_r, r9751_mmio_ff01_w)
AM_RANGE(0xFF050000,0xFF06FFFF) AM_READWRITE(r9751_mmio_ff05_r, r9751_mmio_ff05_w) AM_RANGE(0xFF050000,0xFF06FFFF) AM_READWRITE(r9751_mmio_ff05_r, r9751_mmio_ff05_w)
AM_RANGE(0xFFF80000,0xFFF8FFFF) AM_READWRITE(r9751_mmio_fff8_r, r9751_mmio_fff8_w) AM_RANGE(0xFFF80000,0xFFF8FFFF) AM_READWRITE(r9751_mmio_fff8_r, r9751_mmio_fff8_w)
//AM_RANGE(0xffffff00,0xffffffff) AM_RAM // Unknown area //AM_RANGE(0xffffff00,0xffffffff) AM_RAM // Unknown area