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28fxxx: initial commit for new flash memory device (#2805)
Implementation of 28F010 and family flash memory devices. These are not compatible with the JEDEC-standard flash command protocol implemented in intelfsh.
This commit is contained in:
Patrick Mackinlay
Vas Crabb
parent
62c9bcc660
commit
f87cc5c671
@ -3301,3 +3301,15 @@ if (MACHINES["ADC0844"]~=null) then
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MAME_DIR .. "src/devices/machine/adc0844.h",
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}
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end
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---------------------------------------------------
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--
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--@src/devices/machine/28fxxx.h,MACHINES["28FXXX"] = true
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---------------------------------------------------
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if (MACHINES["28FXXX"]~=null) then
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files {
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MAME_DIR .. "src/devices/machine/28fxxx.cpp",
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MAME_DIR .. "src/devices/machine/28fxxx.h",
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}
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end
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@ -619,6 +619,7 @@ MACHINES["I82586"] = true
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MACHINES["INPUT_MERGER"] = true
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-- MACHINES["K054321"] = true
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MACHINES["ADC0844"] = true
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MACHINES["28FXXX"] = true
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--------------------------------------------------
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-- specify available bus cores
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236
src/devices/machine/28fxxx.cpp
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236
src/devices/machine/28fxxx.cpp
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@ -0,0 +1,236 @@
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// license:BSD-3-Clause
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// copyright-holders:Patrick Mackinlay
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/*
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* An implementation of the 28Fxxx flash memory devices, fabricated by many
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* suppliers including Intel, Atmel, AMD, SGS, TI and Toshiba. Range includes:
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*
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* Part Bits Org.
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* ------ ----- ------
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* 28F256 256K 32Kx8
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* 28F512 512K 64Kx8
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* 28F010 1024K 128Kx8
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* 28F020 2048K 256Kx8
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* 28F040 4096K 512Kx8
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*
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* These devices use a JEDEC-standard pinout allowing them to be fitted to a
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* standard EPROM socket, but have their own command set which is not
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* compatible with the set implemented by the intelfsh devices. It appears the
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* command set used here is a variation on the one defined by JEDEC standard
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* 21-C, as "dual power supply eeprom command set", in figure 3.5.1-11 on page
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* 23, here: https://www.jedec.org/system/files/docs/3_05_01R14.pdf
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*
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* This implementation has been developed primarily against Intel's datasheet,
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* with some minor adjustments to match details in the AMD equivalent.
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*
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* TODO
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* - implement more variants
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* - testing in systems other than InterPro
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*
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*/
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#include "emu.h"
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#include "28fxxx.h"
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#define VERBOSE 0
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#include "logmacro.h"
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// manufacturer codes defined by JEDEC: https://www.jedec.org/system/files/docs/JEP106AV.pdf
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enum manufacturer_codes
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{
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MFG_AMD = 0x01,
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MFG_INTEL = 0x89,
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};
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DEFINE_DEVICE_TYPE(INTEL_28F010, intel_28f010_device, "intel_28f010", "Intel 28F010 1024K (128K x 8) CMOS Flash Memory")
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DEFINE_DEVICE_TYPE(AMD_28F010, amd_28f010_device, "amd_28f010", "Am28F010 1 Megabit (128K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory")
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ALLOW_SAVE_TYPE(base_28fxxx_device::state);
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base_28fxxx_device::base_28fxxx_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u32 size, u8 manufacturer_code, u8 device_code)
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: device_t(mconfig, type, tag, owner, clock)
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, device_nvram_interface(mconfig, *this)
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, m_region(*this, DEVICE_SELF)
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, m_size(size)
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, m_manufacturer_code(manufacturer_code)
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, m_device_code(device_code)
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, m_program_power(CLEAR_LINE)
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, m_state(STATE_READ_MEMORY)
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{
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assert_always((m_size & (m_size - 1)) == 0, "memory size must be an exact power of two");
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}
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intel_28f010_device::intel_28f010_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: base_28fxxx_device(mconfig, INTEL_28F010, tag, owner, clock, 0x20000, MFG_INTEL, 0xb4)
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{
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}
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amd_28f010_device::amd_28f010_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: base_28fxxx_device(mconfig, AMD_28F010, tag, owner, clock, 0x20000, MFG_AMD, 0xa7)
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{
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}
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void base_28fxxx_device::device_start()
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{
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m_data = std::make_unique<u8[]>(m_size);
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save_item(NAME(m_program_power));
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save_pointer(NAME(m_data.get()), m_size);
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save_item(NAME(m_state));
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save_item(NAME(m_address_latch));
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}
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void base_28fxxx_device::nvram_default()
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{
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if (m_region.found())
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{
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u32 bytes = m_region->bytes();
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if (bytes > m_size)
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bytes = m_size;
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for (offs_t offs = 0; offs < bytes; offs++)
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m_data[offs] = m_region->as_u8(offs);
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}
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else
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erase();
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}
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void base_28fxxx_device::nvram_read(emu_file &file)
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{
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file.read(m_data.get(), m_size);
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}
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void base_28fxxx_device::nvram_write(emu_file &file)
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{
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file.write(m_data.get(), m_size);
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}
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void base_28fxxx_device::erase()
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{
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memset(m_data.get(), 0xff, m_size);
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}
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READ8_MEMBER(base_28fxxx_device::read)
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{
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switch (m_state)
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{
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case STATE_READ_MEMORY:
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return m_data.get()[offset & (m_size - 1)];
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case STATE_READ_IDENTIFIER:
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switch (offset)
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{
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case 0: return m_manufacturer_code;
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case 1: return m_device_code;
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}
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LOG("unknown read identifier offset 0x%08x (%s)\n", offset, machine().describe_context());
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return space.unmap();
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case STATE_ERASE_VERIFY:
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return m_data.get()[m_address_latch];
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case STATE_PROGRAM_VERIFY:
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return m_data.get()[m_address_latch];
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default:
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LOG("unexpected read offset 0x%08x mask 0x%08x state %d (%s)\n", offset, mem_mask, m_state, machine().describe_context());
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return space.unmap();
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}
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}
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WRITE8_MEMBER(base_28fxxx_device::write)
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{
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// writes are ignored unless Vpp is asserted
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if (!m_program_power)
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return;
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switch (m_state)
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{
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case STATE_ERASE_SETUP:
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if (data == ERASE)
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{
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LOG("erase command initiated (%s)\n", machine().describe_context());
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erase();
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m_state = STATE_ERASE;
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}
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else if (data == RESET)
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{
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LOG("erase command reset (%s)\n", machine().describe_context());
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m_state = STATE_READ_MEMORY;
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}
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else
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LOG("unexpected command 0x%02x in erase setup state (%s)\n", data, machine().describe_context());
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break;
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case STATE_ERASE:
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if (data == ERASE_VERIFY)
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{
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m_address_latch = offset & (m_size - 1);
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m_state = STATE_ERASE_VERIFY;
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}
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else
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LOG("unexpected command 0x%02x in erase state (%s)\n", data, machine().describe_context());
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break;
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case STATE_PROGRAM_SETUP:
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m_address_latch = offset & (m_size - 1);
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LOG("programming address 0x%08x data 0x%02x\n", m_address_latch, data);
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// bits can only be written from uncharged (logical 1) to charged (logical 0) state
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m_data.get()[m_address_latch] &= data;
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m_state = STATE_PROGRAM;
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break;
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case STATE_PROGRAM:
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if (data == PROGRAM_VERIFY)
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m_state = STATE_PROGRAM_VERIFY;
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else if (data == RESET)
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{
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LOG("program command reset (%s)\n", machine().describe_context());
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m_state = STATE_READ_MEMORY;
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}
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else
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LOG("unexpected command 0x%02x in program state (%s)\n", data, machine().describe_context());
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break;
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default:
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// start a new command
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switch (data)
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{
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case READ_MEMORY:
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m_state = STATE_READ_MEMORY;
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break;
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case READ_IDENTIFIER:
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case READ_IDENTIFIER_ALT:
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m_state = STATE_READ_IDENTIFIER;
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break;
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case ERASE:
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m_state = STATE_ERASE_SETUP;
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break;
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case ERASE_VERIFY:
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m_address_latch = offset & (m_size - 1);
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m_state = STATE_ERASE_VERIFY;
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break;
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case PROGRAM:
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m_state = STATE_PROGRAM_SETUP;
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break;
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case RESET:
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m_state = STATE_READ_MEMORY;
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break;
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default:
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LOG("unexpected command 0x%02x in state %d (%s)\n", data, m_state, machine().describe_context());
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break;
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}
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break;
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}
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}
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84
src/devices/machine/28fxxx.h
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84
src/devices/machine/28fxxx.h
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@ -0,0 +1,84 @@
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// license:BSD-3-Clause
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// copyright-holders:Patrick Mackinlay
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#ifndef MAME_MACHINE_28FXXX_H
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#define MAME_MACHINE_28FXXX_H
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#pragma once
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class base_28fxxx_device : public device_t, public device_nvram_interface
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{
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public:
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enum commands
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{
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READ_MEMORY = 0x00,
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ERASE = 0x20,
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PROGRAM = 0x40,
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READ_IDENTIFIER_ALT = 0x80, // defined in AMD datasheet, but not Intel
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READ_IDENTIFIER = 0x90,
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ERASE_VERIFY = 0xa0,
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PROGRAM_VERIFY = 0xc0,
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RESET = 0xff
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};
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DECLARE_WRITE_LINE_MEMBER(vpp) { m_program_power = state; }
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DECLARE_READ8_MEMBER(read);
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DECLARE_WRITE8_MEMBER(write);
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protected:
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base_28fxxx_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u32 size, u8 manufacturer_code, u8 device_code);
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virtual void device_start() override;
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virtual void nvram_default() override;
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virtual void nvram_read(emu_file &file) override;
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virtual void nvram_write(emu_file &file) override;
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optional_memory_region m_region;
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private:
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void erase();
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// device specific parameters
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const u32 m_size;
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const u8 m_manufacturer_code;
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const u8 m_device_code;
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// accessible device state
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int m_program_power;
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std::unique_ptr<u8[]> m_data;
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// internal state
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enum state : u8
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{
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STATE_READ_MEMORY,
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STATE_READ_IDENTIFIER,
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STATE_ERASE_SETUP,
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STATE_ERASE,
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STATE_ERASE_RESET,
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STATE_ERASE_VERIFY,
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STATE_PROGRAM_SETUP,
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STATE_PROGRAM,
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STATE_PROGRAM_VERIFY
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};
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state m_state;
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u32 m_address_latch;
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};
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class intel_28f010_device : public base_28fxxx_device
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{
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public:
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intel_28f010_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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};
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class amd_28f010_device : public base_28fxxx_device
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{
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public:
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amd_28f010_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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};
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DECLARE_DEVICE_TYPE(INTEL_28F010, intel_28f010_device)
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DECLARE_DEVICE_TYPE(AMD_28F010, amd_28f010_device)
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#endif // MAME_MACHINE_28FXXX_H
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