mirror of
https://github.com/holub/mame
synced 2025-05-25 15:25:33 +03:00
Replaced simulation of Namco 53xx with emulation. Both
Pole Position and Dig Dug are now properly hooked up.
This commit is contained in:
Aaron Giles
parent
1fe720014c
commit
f9f03182fb
@ -713,6 +713,7 @@ TODO:
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static emu_timer *cpu3_interrupt_timer;
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static UINT8 custom_mod;
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@ -768,8 +769,15 @@ static WRITE8_HANDLER( bosco_latch_w )
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break;
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case 0x05: /* MOD 0 (xevious: n.c.) */
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custom_mod = (custom_mod & ~0x01) | (bit << 0);
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break;
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case 0x06: /* MOD 1 (xevious: n.c.) */
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custom_mod = (custom_mod & ~0x02) | (bit << 1);
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break;
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case 0x07: /* MOD 2 (xevious: n.c.) */
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custom_mod = (custom_mod & ~0x04) | (bit << 2);
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break;
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}
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}
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@ -803,18 +811,23 @@ static const namco_51xx_interface namco_51xx_intf =
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}
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};
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static READ8_DEVICE_HANDLER( custom_mod_r )
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{
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/* MOD0-2 is connected to K1-3; K0 is left unconnected */
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return custom_mod << 1;
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}
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static const namco_53xx_interface namco_53xx_intf =
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{
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{ /* port read handlers */
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DEVCB_INPUT_PORT("DSWA"),
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DEVCB_INPUT_PORT("DSWA_HI"),
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DEVCB_INPUT_PORT("DSWB"),
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DEVCB_INPUT_PORT("DSWB_HI")
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DEVCB_HANDLER(custom_mod_r), /* K port */
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{
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DEVCB_INPUT_PORT("DSWA"), /* R0 port */
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DEVCB_INPUT_PORT("DSWA_HI"), /* R1 port */
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DEVCB_INPUT_PORT("DSWB"), /* R2 port */
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DEVCB_INPUT_PORT("DSWB_HI") /* R3 port */
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},
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{ /* port write handlers */
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DEVCB_NULL,
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DEVCB_NULL
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}
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DEVCB_NULL /* P port */
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};
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@ -229,6 +229,12 @@ Notes:
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#define POLEPOS_TOGGLE PORT_TOGGLE
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static UINT8 steer_last;
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static UINT8 steer_delta;
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static INT16 steer_accum;
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/*************************************************************************************/
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/* Pole Position II protection */
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/*************************************************************************************/
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@ -372,18 +378,52 @@ static const namco_51xx_interface namco_51xx_intf =
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}
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};
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static READ8_DEVICE_HANDLER( namco_53xx_k_r )
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{
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/* hardwired to 0 */
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return 0;
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}
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static READ8_DEVICE_HANDLER( steering_changed_r )
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{
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/* read the current steering value and update our delta */
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UINT8 steer_new = input_port_read(device->machine, "STEER");
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steer_accum += (INT8)(steer_new - steer_last);
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steer_last = steer_new;
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/* if we have delta, clock things */
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if (steer_accum < 0)
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{
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steer_delta = 1;
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steer_accum++;
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}
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else if (steer_accum > 0)
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{
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steer_delta = 0;
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steer_accum--;
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}
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else
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steer_delta ^= 1;
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return steer_accum & 1;
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}
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static READ8_DEVICE_HANDLER( steering_delta_r )
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{
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return steer_delta;
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}
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static const namco_53xx_interface namco_53xx_intf =
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{
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{ /* port read handlers */
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DEVCB_INPUT_PORT("STEER"),
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DEVCB_INPUT_PORT("STEER_HI"),
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DEVCB_INPUT_PORT("DSWA"),
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DEVCB_INPUT_PORT("DSWA_HI")
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DEVCB_HANDLER(namco_53xx_k_r), /* K port */
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{
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DEVCB_HANDLER(steering_changed_r), /* R0 port */
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DEVCB_HANDLER(steering_delta_r), /* R1 port */
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DEVCB_INPUT_PORT("DSWA"), /* R2 port */
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DEVCB_INPUT_PORT("DSWA_HI") /* R3 port */
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},
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{ /* port write handlers */
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DEVCB_NULL,
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DEVCB_NULL
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}
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DEVCB_NULL /* P port (connected to test socket) */
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};
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@ -529,9 +569,6 @@ static INPUT_PORTS_START( polepos )
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PORT_START("STEER")
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PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(30) PORT_KEYDELTA(4)
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PORT_START("STEER_HI")
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PORT_BIT( 0x0f, 0x00, IPT_SPECIAL ) PORT_CUSTOM(shifted_port_r, "STEER")
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INPUT_PORTS_END
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@ -612,9 +649,6 @@ static INPUT_PORTS_START( poleposa )
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PORT_START("STEER")
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PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(30) PORT_KEYDELTA(4)
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PORT_START("STEER_HI")
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PORT_BIT( 0x0f, 0x00, IPT_SPECIAL ) PORT_CUSTOM(shifted_port_r, "STEER")
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INPUT_PORTS_END
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@ -693,9 +727,6 @@ static INPUT_PORTS_START( topracra )
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PORT_START("STEER")
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PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(30) PORT_KEYDELTA(4)
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PORT_START("STEER_HI")
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PORT_BIT( 0x0f, 0x00, IPT_SPECIAL ) PORT_CUSTOM(shifted_port_r, "STEER")
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INPUT_PORTS_END
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@ -774,9 +805,6 @@ static INPUT_PORTS_START( polepos2 )
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PORT_START("STEER")
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PORT_BIT ( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(30) PORT_KEYDELTA(4)
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PORT_START("STEER_HI")
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PORT_BIT( 0x0f, 0x00, IPT_SPECIAL ) PORT_CUSTOM(shifted_port_r, "STEER")
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INPUT_PORTS_END
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@ -262,7 +262,10 @@ static DEVICE_START( namco_06xx )
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state->write[devnum] = namco_51xx_write;
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}
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else if (type == NAMCO_53XX)
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{
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state->read[devnum] = namco_53xx_read;
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state->readreq[devnum] = namco_53xx_read_request;
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}
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else if (type == NAMCO_54XX)
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state->write[devnum] = namco_54xx_write;
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else if (type == SOUND && sound_get_type(state->device[devnum]) == SOUND_NAMCO_52XX)
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@ -4,9 +4,6 @@ Namco 53XX
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This custom chip is a Fujitsu MB8843 MCU programmed to act as an I/O device.
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The chip reads/writes the I/O ports when the /IRQ is pulled down. Pin 21
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determines whether a read or write should happen (1=R, 0=W).
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MB8843
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+------+
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EXTAL|1 42|Vcc
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@ -32,16 +29,13 @@ determines whether a read or write should happen (1=R, 0=W).
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GND|21 22|R0
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+------+
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Bits K1-K3 select one of 8 modes in which the input data is interpreted.
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commands:
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00: nop
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01 + 4 arguments: set coinage (xevious, possibly because of a bug, is different)
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02: go in "credit" mode and enable start buttons
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03: disable joystick remapping
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04: enable joystick remapping
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05: go in "switch" mode
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06: nop
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07: nop
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Pole Position is hard-wired to use mode 0, which reads 4 steering inputs
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and 4 DIP switches (only 1 of each is used).
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Dig Dug can control which mode to use via the MOD bit latches. It sets
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these values to mode 7 when running.
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***************************************************************************/
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@ -54,17 +48,14 @@ commands:
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#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
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#define READ_PORT(st,num) devcb_call_read8(&(st)->in[num], 0)
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#define WRITE_PORT(st,num,data) devcb_call_write8(&(st)->out[num], 0, data)
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typedef struct _namco_53xx_state namco_53xx_state;
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struct _namco_53xx_state
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{
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const device_config * cpu;
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int in_count;
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devcb_resolved_read8 in[4];
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devcb_resolved_write8 out[2];
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UINT8 portO;
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devcb_resolved_read8 k;
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devcb_resolved_read8 in[4];
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devcb_resolved_write8 p;
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};
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INLINE namco_53xx_state *get_safe_token(const device_config *device)
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@ -78,23 +69,63 @@ INLINE namco_53xx_state *get_safe_token(const device_config *device)
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READ8_DEVICE_HANDLER( namco_53xx_read )
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static READ8_HANDLER( namco_53xx_K_r )
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{
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namco_53xx_state *state = get_safe_token(device);
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namco_53xx_state *state = get_safe_token(space->cpu->owner);
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return devcb_call_read8(&state->k, 0);
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}
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LOG(("%s: custom 53XX read\n",cpuexec_describe_context(device->machine)));
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static READ8_HANDLER( namco_53xx_Rx_r )
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{
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namco_53xx_state *state = get_safe_token(space->cpu->owner);
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return devcb_call_read8(&state->in[offset], 0);
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}
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// digdug: ((state->in_count++) % 2)
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switch ((state->in_count++) % 8)
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{
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case 0: return READ_PORT(state,0) | (READ_PORT(state,1) << 4); // steering
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// digdug: case 1:
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case 4: return READ_PORT(state,2) | (READ_PORT(state,3) << 4); // dip switches
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default: return 0xff; // polepos2 hangs if 0 is returned
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}
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static WRITE8_HANDLER( namco_53xx_O_w )
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{
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namco_53xx_state *state = get_safe_token(space->cpu->owner);
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UINT8 out = (data & 0x0f);
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if (data & 0x10)
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state->portO = (state->portO & 0x0f) | (out << 4);
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else
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state->portO = (state->portO & 0xf0) | (out);
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}
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static WRITE8_HANDLER( namco_53xx_P_w )
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{
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namco_53xx_state *state = get_safe_token(space->cpu->owner);
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devcb_call_write8(&state->p, 0, data);
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}
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static TIMER_CALLBACK( namco_53xx_irq_clear )
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{
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namco_53xx_state *state = get_safe_token((const device_config *)ptr);
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cpu_set_input_line(state->cpu, 0, CLEAR_LINE);
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}
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void namco_53xx_read_request(const device_config *device)
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{
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namco_53xx_state *state = get_safe_token(device);
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cpu_set_input_line(state->cpu, 0, ASSERT_LINE);
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// The execution time of one instruction is ~4us, so we must make sure to
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// give the cpu time to poll the /IRQ input before we clear it.
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// The input clock to the 06XX interface chip is 64H, that is
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// 18432000/6/64 = 48kHz, so it makes sense for the irq line to be
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// asserted for one clock cycle ~= 21us.
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timer_set(device->machine, ATTOTIME_IN_USEC(21), (void *)device, 0, namco_53xx_irq_clear);
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}
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READ8_DEVICE_HANDLER( namco_53xx_read )
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{
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namco_53xx_state *state = get_safe_token(device);
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UINT8 res = state->portO;
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namco_53xx_read_request(device);
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return res;
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}
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/***************************************************************************
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@ -102,17 +133,16 @@ READ8_DEVICE_HANDLER( namco_53xx_read )
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***************************************************************************/
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ADDRESS_MAP_START( namco_53xx_map_io, ADDRESS_SPACE_IO, 8 )
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// AM_RANGE(MB88_PORTK, MB88_PORTK) AM_READ(namco_53xx_K_r)
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// AM_RANGE(MB88_PORTO, MB88_PORTO) AM_WRITE(namco_53xx_O_w)
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// AM_RANGE(MB88_PORTR0, MB88_PORTR0) AM_READ(namco_53xx_R0_r)
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// AM_RANGE(MB88_PORTR2, MB88_PORTR2) AM_READ(namco_53xx_R2_r)
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AM_RANGE(MB88_PORTK, MB88_PORTK) AM_READ(namco_53xx_K_r)
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AM_RANGE(MB88_PORTO, MB88_PORTO) AM_WRITE(namco_53xx_O_w)
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AM_RANGE(MB88_PORTP, MB88_PORTP) AM_WRITE(namco_53xx_P_w)
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AM_RANGE(MB88_PORTR0, MB88_PORTR3) AM_READ(namco_53xx_Rx_r)
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ADDRESS_MAP_END
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static MACHINE_DRIVER_START( namco_53xx )
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MDRV_CPU_ADD("mcu", MB8843, DERIVED_CLOCK(1,1)) /* parent clock, internally divided by 6 */
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MDRV_CPU_IO_MAP(namco_53xx_map_io)
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MDRV_CPU_FLAGS(CPU_DISABLE)
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MACHINE_DRIVER_END
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@ -139,17 +169,13 @@ static DEVICE_START( namco_53xx )
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assert(state->cpu != NULL);
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astring_free(tempstring);
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/* resolve our read callbacks */
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/* resolve our read/write callbacks */
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devcb_resolve_read8(&state->k, &config->k, device);
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devcb_resolve_read8(&state->in[0], &config->in[0], device);
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devcb_resolve_read8(&state->in[1], &config->in[1], device);
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devcb_resolve_read8(&state->in[2], &config->in[2], device);
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devcb_resolve_read8(&state->in[3], &config->in[3], device);
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/* resolve our write callbacks */
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devcb_resolve_write8(&state->out[0], &config->out[0], device);
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devcb_resolve_write8(&state->out[1], &config->out[1], device);
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state_save_register_device_item(device, 0, state->in_count);
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devcb_resolve_write8(&state->p, &config->p, device);
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}
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@ -159,8 +185,7 @@ static DEVICE_START( namco_53xx )
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static DEVICE_RESET( namco_53xx )
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{
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namco_53xx_state *state = get_safe_token(device);
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state->in_count = 0;
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// namco_53xx_state *state = get_safe_token(device);
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}
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@ -7,8 +7,9 @@
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typedef struct _namco_53xx_interface namco_53xx_interface;
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struct _namco_53xx_interface
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{
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devcb_read8 k; /* read handlers for K port */
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devcb_read8 in[4]; /* read handlers for ports A-D */
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devcb_write8 out[2]; /* write handlers for ports A-B */
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devcb_write8 p; /* write handler for P port */
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};
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@ -20,6 +21,7 @@ struct _namco_53xx_interface
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MDRV_DEVICE_REMOVE(_tag)
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void namco_53xx_read_request(const device_config *device);
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READ8_DEVICE_HANDLER( namco_53xx_read );
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