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@ -216,9 +216,6 @@ static void scu_dma_indirect(address_space *space, UINT8 dma_ch); /*DMA level 0
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//static int scanline;
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static emu_timer *stv_rtc_timer;
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/*A-Bus IRQ checks,where they could be located these?*/
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#define ABUSIRQ(_irq_,_vector_) \
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{ cputag_set_input_line_and_vector(device->machine(), "maincpu", _irq_, HOLD_LINE , _vector_); }
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@ -2627,7 +2624,7 @@ static MACHINE_START( stv )
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state->m_smpc_ram[0x2d] = DectoBCD(systime.local_time.minute);
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state->m_smpc_ram[0x2f] = DectoBCD(systime.local_time.second);
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stv_rtc_timer = machine.scheduler().timer_alloc(FUNC(stv_rtc_increment));
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state->m_stv_rtc_timer = machine.scheduler().timer_alloc(FUNC(stv_rtc_increment));
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}
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@ -2915,7 +2912,7 @@ static MACHINE_RESET( stv )
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vblank_out_timer->adjust(machine.primary_screen->time_until_pos(0));
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scan_timer->adjust(machine.primary_screen->time_until_pos(224, 352));
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stv_rtc_timer->adjust(attotime::zero, 0, attotime::from_seconds(1));
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state->m_stv_rtc_timer->adjust(attotime::zero, 0, attotime::from_seconds(1));
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state->m_prev_bankswitch = 0xff;
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}
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@ -6,27 +6,31 @@ public:
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saturn_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag) { }
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UINT32 *m_workram_l;
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UINT32 *m_workram_h;
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UINT8 *m_smpc_ram;
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UINT32 *m_backupram;
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UINT32 *m_scu_regs;
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UINT8 m_NMI_reset;
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UINT8 m_en_68k;
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UINT16 *m_sound_ram;
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UINT32 *m_workram_l;
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UINT32 *m_workram_h;
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UINT8 *m_smpc_ram;
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UINT32 *m_backupram;
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UINT32 *m_scu_regs;
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UINT16 *m_sound_ram;
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UINT8 m_NMI_reset;
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UINT8 m_en_68k;
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UINT32 m_scu_src[3]; /* Source DMA lv n address*/
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UINT32 m_scu_dst[3]; /* Destination DMA lv n address*/
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UINT32 m_scu_src_add[3]; /* Source Addition for DMA lv n*/
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UINT32 m_scu_dst_add[3]; /* Destination Addition for DMA lv n*/
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INT32 m_scu_size[3]; /* Transfer DMA size lv n*/
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UINT32 m_scu_index[3];
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UINT8 m_stv_multi_bank;
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UINT8 m_prev_bankswitch;
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int m_minit_boost;
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int m_sinit_boost;
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attotime m_minit_boost_timeslice;
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attotime m_sinit_boost_timeslice;
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UINT32 m_scu_src[3]; /* Source DMA lv n address*/
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UINT32 m_scu_dst[3]; /* Destination DMA lv n address*/
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UINT32 m_scu_src_add[3]; /* Source Addition for DMA lv n*/
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UINT32 m_scu_dst_add[3]; /* Destination Addition for DMA lv n*/
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INT32 m_scu_size[3]; /* Transfer DMA size lv n*/
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UINT32 m_scu_index[3];
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int m_minit_boost;
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int m_sinit_boost;
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attotime m_minit_boost_timeslice;
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attotime m_sinit_boost_timeslice;
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/* ST-V specific */
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UINT8 m_stv_multi_bank;
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UINT8 m_prev_bankswitch;
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emu_timer *m_stv_rtc_timer;
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legacy_cpu_device* m_maincpu;
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legacy_cpu_device* m_slave;
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