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https://github.com/holub/mame
synced 2025-05-23 06:08:48 +03:00
SNES updates: [R. Belmont, Harmony]
- Corrected ROM loading behavior for SuperFX games - Added more ROM mirroring needed by certain SuperFX 2 games - Corrected the behavior of certain bit-restricted SuperFX registers. Doom, Yoshi's Island, Dirt Trax FX and Voxel Demo show things now. - Improved S-DD1 emulation, neither game using S-DD1 boots yet
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@ -530,6 +530,8 @@ void superfx_mmio_write(const device_config *cpu, UINT32 addr, UINT8 data)
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addr &= 0xffff;
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//printf( "superfx_mmio_write: %08x = %02x\n", addr, data );
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if(addr >= 0x3100 && addr <= 0x32ff)
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{
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return superfx_cache_mmio_write(cpustate, addr - 0x3100, data);
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@ -573,11 +575,11 @@ void superfx_mmio_write(const device_config *cpu, UINT32 addr, UINT8 data)
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break;
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case 0x3033:
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cpustate->bramr = data;
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cpustate->bramr = data & 1;
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break;
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case 0x3034:
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cpustate->pbr = data;
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cpustate->pbr = data & 0x7f;
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superfx_cache_flush(cpustate);
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break;
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@ -591,7 +593,7 @@ void superfx_mmio_write(const device_config *cpu, UINT32 addr, UINT8 data)
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break;
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case 0x3039:
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cpustate->clsr = data;
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cpustate->clsr = data & 1;
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superfx_update_speed(cpustate);
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break;
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@ -1169,7 +1171,7 @@ static CPU_EXECUTE( superfx )
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{ // DIV2
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cpustate->sfr &= ~SUPERFX_SFR_CY;
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cpustate->sfr |= (*(cpustate->sreg) & 1) ? SUPERFX_SFR_CY : 0;
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superfx_gpr_write(cpustate, cpustate->dreg_idx, ((INT16)(*(cpustate->sreg)) >> 1) + ((*(cpustate->sreg) + 1) >> 16));
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superfx_gpr_write(cpustate, cpustate->dreg_idx, ((INT16)(*(cpustate->sreg)) >> 1) + ((UINT32)(*(cpustate->sreg) + 1) >> 16));
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superfx_dreg_sfr_sz_update(cpustate);
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superfx_regs_reset(cpustate);
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}
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@ -1194,7 +1196,7 @@ static CPU_EXECUTE( superfx )
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}
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else
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{ // LJMP
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cpustate->pbr = cpustate->r[op & 0xf];
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cpustate->pbr = cpustate->r[op & 0xf] & 0x7f;
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superfx_gpr_write(cpustate, 15, *(cpustate->sreg));
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cpustate->cbr = cpustate->r[15] & 0xfff0;
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superfx_cache_flush(cpustate);
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@ -1319,12 +1321,12 @@ static CPU_EXECUTE( superfx )
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break;
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case SUPERFX_SFR_ALT2: // RAMB
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superfx_rambuffer_sync(cpustate);
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cpustate->rambr = *(cpustate->sreg);
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cpustate->rambr = ((*(cpustate->sreg)) & 1) ? 1 : 0;
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superfx_regs_reset(cpustate);
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break;
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case SUPERFX_SFR_ALT3: // ROMB
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superfx_rombuffer_sync(cpustate);
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cpustate->rombr = *(cpustate->sreg);
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cpustate->rombr = *(cpustate->sreg) & 0x7f;
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superfx_regs_reset(cpustate);
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break;
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}
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@ -1354,8 +1354,6 @@ WRITE8_HANDLER( snes_w_io )
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break;
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}
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logerror("Unsupported MMIO write: offset %08x = %02x\n", offset, data);
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snes_ram[offset] = data;
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}
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@ -1520,7 +1518,12 @@ READ8_HANDLER( snes_r_bank3 )
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UINT8 value;
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UINT16 address = offset & 0xffff;
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if (snes_cart.mode & 5) /* Mode 20 & 22 */
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if (snes_has_addon_chip == HAS_SUPERFX)
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{
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//printf( "snes_r_bank3: %08x\n", offset );
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return snes_ram[0x400000 + offset];
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}
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else if (snes_cart.mode & 5) /* Mode 20 & 22 */
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{
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if ((address < 0x8000) && (snes_cart.mode == SNES_MODE_20)) //FIXME: check this
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value = snes_ram[0x200000 + ((offset & ~0x8000) | 0x8000)]; /* Reserved */
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@ -1669,7 +1672,9 @@ WRITE8_HANDLER( snes_w_bank1 )
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snes_w_io(space, address, data);
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else if (address < 0x8000)
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{
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if (snes_has_addon_chip == HAS_OBC1)
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if (snes_has_addon_chip == HAS_SUPERFX)
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snes_ram[0x700000 + (address & 0x1fff)] = data;
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else if (snes_has_addon_chip == HAS_OBC1)
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obc1_write(space, offset, data);
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else if ((snes_has_addon_chip == HAS_DSP2) && (offset >= 0x200000))
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DSP2_write(data);
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@ -2478,5 +2483,6 @@ WRITE8_HANDLER( superfx_w_bank2 )
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WRITE8_HANDLER( superfx_w_bank3 )
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{
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//printf( "superfx_w_bank3: %08x = %02x\n", 0x600000 + offset, data );
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snes_ram[0x600000 + offset] = data;
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}
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