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Merge pull request #917 from JoakimLarsson/sun380_z8530

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Bugfixes in baudrate calculation to make Sun3-80 work
This commit is contained in:
etabeta78 2016-06-02 12:23:56 +02:00
commit fbd8879395
3 changed files with 28 additions and 26 deletions
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25
src/devices/machine/z80scc.cpp
View File

@ -1657,6 +1657,7 @@ void z80scc_channel::do_sccreg_wr9(UINT8 data)
if (data & (WR9_BIT_MIE | WR9_BIT_IACK | WR9_BIT_SHSL | WR9_BIT_DLC | WR9_BIT_NV))
logerror(" SCC Interrupt system not yet implemented, please be patient.\n");
m_uart->device_reset();
break;
default:
logerror("Code is broken in WR9, please report!\n");
}
@ -1676,7 +1677,7 @@ receive and transmit clocks, the type of signal on the /SYNC and /RTxC pins, and
the /TRxC pin.*/
void z80scc_channel::do_sccreg_wr11(UINT8 data)
{
LOG(("\"%s\": %c : %s Clock Mode Control %02x - not implemented \n", m_owner->tag(), 'A' + m_index, FUNCNAME, data));
LOG(("\"%s\": %c : %s Clock Mode Control %02x\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data));
m_wr11 = data;
/*Bit 7: This bit controls the type of input signal the SCC expects to see on the /RTxC pin. If this bit is set
to 0, the SCC expects a TTL-compatible signal as an input to this pin. If this bit is set to 1, the SCC
@ -1695,10 +1696,10 @@ void z80scc_channel::do_sccreg_wr11(UINT8 data)
LOG((" Receive clock source is: "));
switch (data & WR11_RCVCLK_SRC_MASK)
{
case WR11_RCVCLK_SRC_RTXC: LOG(("RTxC\n")); break;
case WR11_RCVCLK_SRC_TRXC: LOG(("TRxC\n")); break;
case WR11_RCVCLK_SRC_RTXC: LOG(("RTxC - not implemented\n")); break;
case WR11_RCVCLK_SRC_TRXC: LOG(("TRxC - not implemented\n")); break;
case WR11_RCVCLK_SRC_BR: LOG(("Baudrate Generator\n")); break;
case WR11_RCVCLK_SRC_DPLL: LOG(("DPLL\n")); break;
case WR11_RCVCLK_SRC_DPLL: LOG(("DPLL - not implemented\n")); break;
default: logerror("Wrong!\n");/* Will not happen unless someone messes with the mask */
}
/*Bits 4 and 3: Transmit Clock select bits 1 and 0.
@ -1711,10 +1712,10 @@ void z80scc_channel::do_sccreg_wr11(UINT8 data)
LOG((" Transmit clock source is: "));
switch (data & WR11_TRACLK_SRC_MASK)
{
case WR11_TRACLK_SRC_RTXC: LOG(("RTxC\n")); break;
case WR11_TRACLK_SRC_TRXC: LOG(("TRxC\n")); break;
case WR11_TRACLK_SRC_RTXC: LOG(("RTxC - not implemented\n")); break;
case WR11_TRACLK_SRC_TRXC: LOG(("TRxC - not implemented\n")); break;
case WR11_TRACLK_SRC_BR: LOG(("Baudrate Generator\n")); break;
case WR11_TRACLK_SRC_DPLL: LOG(("DPLL\n")); break;
case WR11_TRACLK_SRC_DPLL: LOG(("DPLL - not implemented\n")); break;
default: logerror("Wrong!\n");/* Will not happen unless someone messes with the mask */
}
/* Bit 2: TRxC Pin I/O control bit
@ -1734,10 +1735,10 @@ void z80scc_channel::do_sccreg_wr11(UINT8 data)
LOG((" TRxC clock source is: "));
switch (data & WR11_TRXSRC_SRC_MASK)
{
case WR11_TRXSRC_SRC_XTAL: LOG(("the Oscillator\n")); break;
case WR11_TRXSRC_SRC_TRA: LOG(("Transmit clock\n")); break;
case WR11_TRXSRC_SRC_XTAL: LOG(("the Oscillator - not implemented\n")); break;
case WR11_TRXSRC_SRC_TRA: LOG(("Transmit clock - not_implemented\n")); break;
case WR11_TRXSRC_SRC_BR: LOG(("Baudrate Generator\n")); break;
case WR11_TRXSRC_SRC_DPLL: LOG(("DPLL\n")); break;
case WR11_TRXSRC_SRC_DPLL: LOG(("DPLL - not implemented\n")); break;
default: logerror("Wrong!\n");/* Will not happen unless someone messes with the mask */
}
}
@ -1848,7 +1849,7 @@ void z80scc_channel::do_sccreg_wr14(UINT8 data)
m_rcv_mode = RCV_SEEKING;
#endif
#else
m_brg_rate = rate / 2 * get_clock_mode();
m_brg_rate = rate / (2 * get_clock_mode());
update_serial();
#endif
}
@ -2205,7 +2206,7 @@ WRITE_LINE_MEMBER( z80scc_channel::dcd_w )
#endif
}
// set data carrier detect
// set data carrier detect
m_dcd = state;
if (!m_rx_rr0_latch)

26
src/devices/machine/z80scc.h
View File

@ -521,9 +521,9 @@ protected:
emu_timer *baudtimer;
UINT16 m_brg_counter;
#else
UINT16 m_brg_rate;
unsigned int m_brg_rate;
#endif
UINT16 m_brg_const;
unsigned int m_brg_const;
void update_serial();
void set_dtr(int state);
@ -536,18 +536,18 @@ protected:
int get_tx_word_length();
// receiver state
UINT8 m_rx_data_fifo[8]; // receive data FIFO
UINT8 m_rx_error_fifo[8]; // receive error FIFO
UINT8 m_rx_error; // current receive error
//int m_rx_fifo // receive FIFO pointer
int m_rx_fifo_rp; // receive FIFO read pointer
int m_rx_fifo_wp; // receive FIFO write pointer
int m_rx_fifo_sz; // receive FIFO size
UINT8 m_rx_data_fifo[8]; // receive data FIFO
UINT8 m_rx_error_fifo[8]; // receive error FIFO
UINT8 m_rx_error; // current receive error
//int m_rx_fifo // receive FIFO pointer
int m_rx_fifo_rp; // receive FIFO read pointer
int m_rx_fifo_wp; // receive FIFO write pointer
int m_rx_fifo_sz; // receive FIFO size
int m_rx_clock; // receive clock pulse count
int m_rx_first; // first character received
int m_rx_break; // receive break condition
UINT8 m_rx_rr0_latch; // read register 0 latched
int m_rx_clock; // receive clock pulse count
int m_rx_first; // first character received
int m_rx_break; // receive break condition
UINT8 m_rx_rr0_latch; // read register 0 latched
int m_rxd;
int m_ri; // ring indicator latch

3
src/mame/drivers/hk68v10.cpp
View File

@ -184,7 +184,8 @@
#endif
#define BAUDGEN_CLOCK XTAL_19_6608MHz /* Raltron */
#define SCC_CLOCK (BAUDGEN_CLOCK / 4) /* Giving 4.9152MHz as documentation says */
// TODO: figure out the correct divider circuit
#define SCC_CLOCK (BAUDGEN_CLOCK / 5) /* Giving 9600 but not the 4.9152MHz the documentation says... */
class hk68v10_state : public driver_device
{
public: