mirror of
https://github.com/holub/mame
synced 2025-04-24 09:20:02 +03:00
- m6805.c: Modernized M6805 CPU core. [MooglyGuy]
This commit is contained in:
Ryan Holtz
parent
13d9f05bab
commit
fc6ff102b1
@ -13,9 +13,10 @@ HNZC
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*/
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#define OP_HANDLER(_name) INLINE void _name (m6805_Regs* cpustate)
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#define OP_HANDLER(_name) void m6805_base_device::_name()
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#define DERIVED_OP_HANDLER(_arch,_name) void _arch##_device::_name()
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#define OP_HANDLER_BIT(_name) INLINE void _name (m6805_Regs* cpustate, UINT8 bit)
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#define OP_HANDLER_BIT(_name) void m6805_base_device::_name(UINT8 bit)
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OP_HANDLER( illegal )
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{
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@ -158,27 +159,23 @@ OP_HANDLER( bms )
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/* $2e BIL relative ---- */
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OP_HANDLER( bil )
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{
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if(SUBTYPE==SUBTYPE_HD63705)
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{
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BRANCH( cpustate->nmi_state!=CLEAR_LINE );
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}
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else
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{
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BRANCH( cpustate->irq_state[0]!=CLEAR_LINE );
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}
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BRANCH(m_irq_state[0] != CLEAR_LINE);
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}
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DERIVED_OP_HANDLER( hd63705, bil )
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{
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BRANCH(m_nmi_state != CLEAR_LINE);
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}
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/* $2f BIH relative ---- */
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OP_HANDLER( bih )
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{
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if(SUBTYPE==SUBTYPE_HD63705)
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{
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BRANCH( cpustate->nmi_state==CLEAR_LINE );
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}
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else
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{
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BRANCH( cpustate->irq_state[0]==CLEAR_LINE );
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}
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BRANCH(m_irq_state[0] == CLEAR_LINE);
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}
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DERIVED_OP_HANDLER( hd63705, bih )
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{
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BRANCH(m_nmi_state == CLEAR_LINE);
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}
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/* $30 NEG direct -*** */
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@ -789,17 +786,19 @@ OP_HANDLER( rti )
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PULLBYTE(CC);
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PULLBYTE(A);
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PULLBYTE(X);
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PULLWORD(pPC);
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PULLWORD(m_pc);
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#if IRQ_LEVEL_DETECT
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if( m6805.irq_state != CLEAR_LINE && (CC & IFLAG) == 0 )
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m6805.pending_interrupts |= M6805_INT_IRQ;
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if( m_irq_state != CLEAR_LINE && (CC & IFLAG) == 0 )
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{
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m_pending_interrupts |= M6805_INT_IRQ;
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}
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#endif
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}
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/* $81 RTS inherent ---- */
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OP_HANDLER( rts )
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{
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PULLWORD(pPC);
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PULLWORD(m_pc);
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}
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/* $82 ILLEGAL */
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@ -807,14 +806,23 @@ OP_HANDLER( rts )
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/* $83 SWI absolute indirect ---- */
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OP_HANDLER( swi )
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{
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PUSHWORD(cpustate->pc);
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PUSHBYTE(cpustate->x);
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PUSHBYTE(cpustate->a);
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PUSHBYTE(cpustate->cc);
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PUSHWORD(m_pc);
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PUSHBYTE(m_x);
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PUSHBYTE(m_a);
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PUSHBYTE(m_cc);
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SEI;
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if(SUBTYPE==SUBTYPE_HD63705) RM16( cpustate, 0x1ffa, &pPC ); else RM16( cpustate, 0xfffc, &pPC );
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RM16(0xfffc, &m_pc);
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}
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DERIVED_OP_HANDLER( hd63705, swi )
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{
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PUSHWORD(m_pc);
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PUSHBYTE(m_x);
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PUSHBYTE(m_a);
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PUSHBYTE(m_cc);
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SEI;
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RM16(0x1ffa, &m_pc);
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}
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/* $84 ILLEGAL */
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/* $85 ILLEGAL */
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@ -1009,7 +1017,7 @@ OP_HANDLER( bsr )
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{
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UINT8 t;
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IMMBYTE(t);
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PUSHWORD(cpustate->pc);
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PUSHWORD(m_pc);
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PC += SIGNED(t);
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}
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@ -1157,7 +1165,7 @@ OP_HANDLER( jmp_di )
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OP_HANDLER( jsr_di )
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{
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DIRECT;
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PUSHWORD(cpustate->pc);
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PUSHWORD(m_pc);
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PC = EA;
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}
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@ -1312,7 +1320,7 @@ OP_HANDLER( jmp_ex )
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OP_HANDLER( jsr_ex )
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{
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EXTENDED;
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PUSHWORD(cpustate->pc);
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PUSHWORD(m_pc);
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PC = EA;
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}
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@ -1467,7 +1475,7 @@ OP_HANDLER( jmp_ix2 )
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OP_HANDLER( jsr_ix2 )
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{
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INDEXED2;
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PUSHWORD(cpustate->pc);
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PUSHWORD(m_pc);
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PC = EA;
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}
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@ -1622,7 +1630,7 @@ OP_HANDLER( jmp_ix1 )
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OP_HANDLER( jsr_ix1 )
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{
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INDEXED1;
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PUSHWORD(cpustate->pc);
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PUSHWORD(m_pc);
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PC = EA;
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}
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@ -1777,7 +1785,7 @@ OP_HANDLER( jmp_ix )
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OP_HANDLER( jsr_ix )
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{
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INDEXED;
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PUSHWORD(cpustate->pc);
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PUSHWORD(m_pc);
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PC = EA;
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}
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File diff suppressed because it is too large
Load Diff
@ -5,13 +5,363 @@
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#ifndef __M6805_H__
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#define __M6805_H__
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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class m6805_device;
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// device type definition
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extern const device_type M6805;
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extern const device_type M68HC05EG;
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extern const device_type M68705;
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extern const device_type HD63705;
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// ======================> m6805_base_device
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// Used by core CPU interface
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class m6805_base_device : public cpu_device
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{
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public:
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// construction/destruction
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m6805_base_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock, const device_type type, const char *name, UINT32 addr_width);
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protected:
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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// device_execute_interface overrides
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virtual UINT32 execute_min_cycles() const;
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virtual UINT32 execute_max_cycles() const;
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virtual UINT32 execute_input_lines() const;
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virtual void execute_run();
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virtual void execute_set_input(int inputnum, int state) = 0;
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virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const;
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virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const;
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// device_memory_interface overrides
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
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// device_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const;
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virtual UINT32 disasm_max_opcode_bytes() const;
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
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// device_state_interface overrides
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virtual void state_string_export(const device_state_entry &entry, astring &string);
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private:
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// opcode/condition tables
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static const UINT8 m_flags8i[256];
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static const UINT8 m_flags8d[256];
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static const UINT8 m_cycles1[256];
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protected:
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void rd_s_handler_b(UINT8 *b);
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void rd_s_handler_w(PAIR *p);
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void wr_s_handler_b(UINT8 *b);
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void wr_s_handler_w(PAIR *p);
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void RM16(UINT32 addr, PAIR *p);
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void brset(UINT8 bit);
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void brclr(UINT8 bit);
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void bset(UINT8 bit);
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void bclr(UINT8 bit);
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void bra();
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void brn();
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void bhi();
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void bls();
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void bcc();
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void bcs();
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void bne();
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void beq();
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void bhcc();
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void bhcs();
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void bpl();
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void bmi();
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void bmc();
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void bms();
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virtual void bil();
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virtual void bih();
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void bsr();
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void neg_di();
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void com_di();
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void lsr_di();
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void ror_di();
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void asr_di();
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void lsl_di();
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void rol_di();
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void dec_di();
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void inc_di();
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void tst_di();
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void clr_di();
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void nega();
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void coma();
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void lsra();
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void rora();
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void asra();
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void lsla();
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void rola();
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void deca();
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void inca();
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void tsta();
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void clra();
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void negx();
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void comx();
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void lsrx();
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void rorx();
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void asrx();
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void aslx();
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void lslx();
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void rolx();
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void decx();
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void incx();
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void tstx();
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void clrx();
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void neg_ix1();
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void com_ix1();
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void lsr_ix1();
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void ror_ix1();
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void asr_ix1();
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void lsl_ix1();
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void rol_ix1();
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void dec_ix1();
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void inc_ix1();
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void tst_ix1();
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void clr_ix1();
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void neg_ix();
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void com_ix();
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void lsr_ix();
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void ror_ix();
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void asr_ix();
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void lsl_ix();
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void rol_ix();
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void dec_ix();
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void inc_ix();
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void tst_ix();
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void clr_ix();
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void rti();
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void rts();
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virtual void swi();
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void tax();
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void txa();
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void rsp();
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void nop();
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void suba_im();
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void cmpa_im();
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void sbca_im();
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void cpx_im();
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void anda_im();
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void bita_im();
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void lda_im();
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void eora_im();
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void adca_im();
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void ora_im();
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void adda_im();
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void ldx_im();
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void suba_di();
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void cmpa_di();
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void sbca_di();
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void cpx_di();
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void anda_di();
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void bita_di();
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void lda_di();
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void sta_di();
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void eora_di();
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void adca_di();
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void ora_di();
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void adda_di();
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void jmp_di();
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void jsr_di();
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void ldx_di();
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void stx_di();
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void suba_ex();
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void cmpa_ex();
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void sbca_ex();
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void cpx_ex();
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void anda_ex();
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void bita_ex();
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void lda_ex();
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void sta_ex();
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void eora_ex();
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void adca_ex();
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void ora_ex();
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void adda_ex();
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void jmp_ex();
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void jsr_ex();
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void ldx_ex();
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void stx_ex();
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void suba_ix2();
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void cmpa_ix2();
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void sbca_ix2();
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void cpx_ix2();
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void anda_ix2();
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void bita_ix2();
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void lda_ix2();
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void sta_ix2();
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void eora_ix2();
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void adca_ix2();
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void ora_ix2();
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void adda_ix2();
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void jmp_ix2();
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void jsr_ix2();
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void ldx_ix2();
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void stx_ix2();
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void suba_ix1();
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void cmpa_ix1();
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void sbca_ix1();
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void cpx_ix1();
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void anda_ix1();
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void bita_ix1();
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void lda_ix1();
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void sta_ix1();
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void eora_ix1();
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void adca_ix1();
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void ora_ix1();
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void adda_ix1();
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void jmp_ix1();
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void jsr_ix1();
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void ldx_ix1();
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void stx_ix1();
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void suba_ix();
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void cmpa_ix();
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void sbca_ix();
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void cpx_ix();
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void anda_ix();
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void bita_ix();
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void lda_ix();
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void sta_ix();
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void eora_ix();
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void adca_ix();
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void ora_ix();
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void adda_ix();
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void jmp_ix();
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void jsr_ix();
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void ldx_ix();
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void stx_ix();
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void illegal();
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virtual void interrupt();
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virtual void interrupt_vector();
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const char *m_tag;
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// address spaces
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const address_space_config m_program_config;
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// CPU registers
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PAIR m_ea; /* effective address */
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UINT32 m_sp_mask; /* Stack pointer address mask */
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UINT32 m_sp_low; /* Stack pointer low water mark (or floor) */
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PAIR m_pc; /* Program counter */
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PAIR m_s; /* Stack pointer */
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UINT8 m_a; /* Accumulator */
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UINT8 m_x; /* Index register */
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UINT8 m_cc; /* Condition codes */
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UINT16 m_pending_interrupts; /* MB */
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int m_irq_state[9]; /* KW Additional lines for HD63705 */
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int m_nmi_state;
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// other internal states
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int m_icount;
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// address spaces
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address_space *m_program;
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direct_read_data *m_direct;
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};
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// ======================> m6805_device
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class m6805_device : public m6805_base_device
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{
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public:
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// construction/destruction
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m6805_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: m6805_base_device(mconfig, tag, owner, clock, M6805, "M6805", 12) { }
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protected:
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virtual void execute_set_input(int inputnum, int state);
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};
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// ======================> m68hc05eg_device
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class m68hc05eg_device : public m6805_base_device
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{
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public:
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// construction/destruction
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m68hc05eg_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: m6805_base_device(mconfig, tag, owner, clock, M68HC05EG, "M68HC05EG", 13) { }
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protected:
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// device-level overrides
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virtual void device_reset();
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virtual void execute_set_input(int inputnum, int state);
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virtual void interrupt_vector();
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};
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// ======================> m68705_device
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class m68705_device : public m6805_base_device
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{
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public:
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// construction/destruction
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m68705_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: m6805_base_device(mconfig, tag, owner, clock, M68705, "M68705", 12) { }
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protected:
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// device-level overrides
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virtual void device_reset();
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virtual void execute_set_input(int inputnum, int state);
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virtual void interrupt();
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};
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// ======================> hd63705_device
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class hd63705_device : public m6805_base_device
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{
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public:
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// construction/destruction
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hd63705_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: m6805_base_device(mconfig, tag, owner, clock, HD63705, "HD63705", 16) { }
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protected:
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// device-level overrides
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virtual void device_reset();
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virtual void execute_set_input(int inputnum, int state);
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virtual void interrupt_vector();
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// opcodes
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virtual void bil();
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virtual void bih();
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virtual void swi();
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};
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enum { M6805_PC=1, M6805_S, M6805_CC, M6805_A, M6805_X, M6805_IRQ_STATE };
|
||||
|
||||
#define M6805_IRQ_LINE 0
|
||||
|
||||
DECLARE_LEGACY_CPU_DEVICE(M6805, m6805);
|
||||
|
||||
/****************************************************************************
|
||||
* 68HC05EG section
|
||||
****************************************************************************/
|
||||
@ -20,11 +370,10 @@ DECLARE_LEGACY_CPU_DEVICE(M6805, m6805);
|
||||
#define M68HC05EG_INT_TIMER (M6805_IRQ_LINE+1)
|
||||
#define M68HC05EG_INT_CPI (M6805_IRQ_LINE+2)
|
||||
|
||||
DECLARE_LEGACY_CPU_DEVICE(M68HC05EG, m68hc05eg);
|
||||
|
||||
/****************************************************************************
|
||||
* 68705 section
|
||||
****************************************************************************/
|
||||
|
||||
#define M68705_A M6805_A
|
||||
#define M68705_PC M6805_PC
|
||||
#define M68705_S M6805_S
|
||||
@ -36,11 +385,10 @@ DECLARE_LEGACY_CPU_DEVICE(M68HC05EG, m68hc05eg);
|
||||
#define M68705_IRQ_LINE M6805_IRQ_LINE
|
||||
#define M68705_INT_TIMER 0x01
|
||||
|
||||
DECLARE_LEGACY_CPU_DEVICE(M68705, m68705);
|
||||
|
||||
/****************************************************************************
|
||||
* HD63705 section
|
||||
****************************************************************************/
|
||||
|
||||
#define HD63705_A M6805_A
|
||||
#define HD63705_PC M6805_PC
|
||||
#define HD63705_S M6805_S
|
||||
@ -63,8 +411,6 @@ DECLARE_LEGACY_CPU_DEVICE(M68705, m68705);
|
||||
#define HD63705_INT_ADCONV 0x07
|
||||
#define HD63705_INT_NMI 0x08
|
||||
|
||||
DECLARE_LEGACY_CPU_DEVICE(HD63705, hd63705);
|
||||
|
||||
CPU_DISASSEMBLE( m6805 );
|
||||
|
||||
#endif /* __M6805_H__ */
|
||||
|
||||
@ -30,7 +30,7 @@ struct m6809_config
|
||||
extern const device_type M6809;
|
||||
extern const device_type M6809E;
|
||||
|
||||
// ======================> m6809_device
|
||||
// ======================> m6809_base_device
|
||||
|
||||
// Used by core CPU interface
|
||||
class m6809_base_device : public cpu_device,
|
||||
@ -114,8 +114,6 @@ protected:
|
||||
|
||||
int m_extra_cycles; /* cycles used up by interrupts */
|
||||
|
||||
device_irq_acknowledge_callback m_irq_callback;
|
||||
|
||||
PAIR m_ea; /* effective address */
|
||||
|
||||
// other internal states
|
||||
|
||||
Loading…
Reference in New Issue
Block a user