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naomig1: Make the dma cpu-independant [O. Galibert]

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This commit is contained in:
Olivier Galibert 2013-06-08 12:31:25 +00:00
parent 165c949747
commit fe024709e1
14 changed files with 55 additions and 49 deletions
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2
src/mame/drivers/chihiro.c
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@ -3069,7 +3069,7 @@ static MACHINE_CONFIG_START( chihiro_base, chihiro_state )
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( chihirogd, chihiro_base )
MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", "pic", NULL, "maincpu", NOOP)
MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", "pic", NULL, NOOP)
MACHINE_CONFIG_END
#define ROM_LOAD16_WORD_SWAP_BIOS(bios,name,offset,length,hash) \

12
src/mame/drivers/naomi.c
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@ -2521,7 +2521,7 @@ MACHINE_CONFIG_END
*/
static MACHINE_CONFIG_DERIVED( naomi, naomi_base )
MCFG_NAOMI_ROM_BOARD_ADD("rom_board", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
MCFG_NAOMI_ROM_BOARD_ADD("rom_board", "naomibd_eeprom", WRITE8(dc_state, g1_irq))
MACHINE_CONFIG_END
/*
@ -2529,7 +2529,7 @@ MACHINE_CONFIG_END
*/
static MACHINE_CONFIG_DERIVED( naomigd, naomi_base )
MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", ":pic", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", ":pic", "naomibd_eeprom", WRITE8(dc_state, g1_irq))
MACHINE_CONFIG_END
/*
@ -2537,7 +2537,7 @@ MACHINE_CONFIG_END
*/
static MACHINE_CONFIG_DERIVED( naomim1, naomi_base )
MCFG_NAOMI_M1_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
MCFG_NAOMI_M1_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", WRITE8(dc_state, g1_irq))
MACHINE_CONFIG_END
/*
@ -2545,7 +2545,7 @@ MACHINE_CONFIG_END
*/
static MACHINE_CONFIG_DERIVED( naomim2, naomi_base )
MCFG_NAOMI_M2_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
MCFG_NAOMI_M2_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", WRITE8(dc_state, g1_irq))
MACHINE_CONFIG_END
/*
@ -2553,7 +2553,7 @@ MACHINE_CONFIG_END
*/
static MACHINE_CONFIG_DERIVED( naomim4, naomi_base )
MCFG_NAOMI_M4_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
MCFG_NAOMI_M4_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", WRITE8(dc_state, g1_irq))
MACHINE_CONFIG_END
/*
@ -2600,7 +2600,7 @@ static MACHINE_CONFIG_DERIVED( aw_base, naomi_aw_base )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(aw_map)
MCFG_MACRONIX_29L001MC_ADD("awflash")
MCFG_AW_ROM_BOARD_ADD("rom_board", ":rom_key", "maincpu", WRITE8(dc_state, g1_irq))
MCFG_AW_ROM_BOARD_ADD("rom_board", ":rom_key", WRITE8(dc_state, g1_irq))
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( aw1c, aw_base )

2
src/mame/drivers/triforce.c
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@ -547,7 +547,7 @@ static MACHINE_CONFIG_START( triforce_base, triforce_state )
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( triforcegd, triforce_base )
MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", "picreturn", NULL, "maincpu", NOOP)
MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", "picreturn", NULL, NOOP)
MACHINE_CONFIG_END

9
src/mame/includes/dc.h
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@ -8,6 +8,7 @@
#define __DC_H__
#include "video/powervr2.h"
#include "machine/naomig1.h"
class dc_state : public driver_device
{
@ -20,7 +21,8 @@ class dc_state : public driver_device
dc_ram(*this, "dc_ram"),
m_maincpu(*this, "maincpu"),
m_soundcpu(*this, "soundcpu"),
m_powervr2(*this, "powervr2") { }
m_powervr2(*this, "powervr2"),
m_naomig1(*this, "rom_board") { }
required_shared_ptr<UINT64> dc_framebuffer_ram; // '32-bit access area'
required_shared_ptr<UINT64> dc_texture_ram; // '64-bit access area'
@ -47,8 +49,6 @@ class dc_state : public driver_device
UINT8 sel;
}m_wave_dma;
/* video related */
virtual void machine_start();
virtual void machine_reset();
TIMER_CALLBACK_MEMBER(aica_dma_irq);
@ -82,6 +82,9 @@ class dc_state : public driver_device
required_device<cpu_device> m_maincpu;
required_device<cpu_device> m_soundcpu;
required_device<powervr2_device> m_powervr2;
optional_device<naomi_g1_device> m_naomig1;
void generic_dma(UINT32 main_adr, void *dma_ptr, UINT32 length, UINT32 size, bool to_mainram);
};
/*--------- Ch2-DMA Control Registers ----------*/

4
src/mame/machine/awboard.h
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@ -3,8 +3,8 @@
#include "naomig1.h"
#define MCFG_AW_ROM_BOARD_ADD(_tag, _keyregion, _maincpu_tag, _irq_cb) \
MCFG_NAOMI_G1_ADD(_tag, AW_ROM_BOARD, _maincpu_tag, _irq_cb) \
#define MCFG_AW_ROM_BOARD_ADD(_tag, _keyregion, _irq_cb) \
MCFG_NAOMI_G1_ADD(_tag, AW_ROM_BOARD, _irq_cb) \
aw_rom_board::static_set_keyregion(*device, _keyregion);
class aw_rom_board : public naomi_g1_device

20
src/mame/machine/dc.c
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@ -76,6 +76,22 @@ static const char *const sysctrl_names[] =
#endif
void dc_state::generic_dma(UINT32 main_adr, void *dma_ptr, UINT32 length, UINT32 size, bool to_mainram)
{
sh4_ddt_dma ddt;
if(to_mainram)
ddt.destination = main_adr;
else
ddt.source = main_adr;
ddt.buffer = dma_ptr;
ddt.length = length;
ddt.size =size;
ddt.direction = to_mainram;
ddt.channel = -1;
ddt.mode = -1;
sh4_dma_ddt(m_maincpu, &ddt);
}
TIMER_CALLBACK_MEMBER(dc_state::aica_dma_irq)
{
m_wave_dma.start = g2bus_regs[SB_ADST] = 0;
@ -720,6 +736,10 @@ void dc_state::machine_start()
{
rtc_initial_setup();
// dccons doesn't have a specific g1 device yet
if(m_naomig1)
m_naomig1->set_dma_cb(naomi_g1_device::dma_cb(FUNC(dc_state::generic_dma), this));
// save states
save_pointer(NAME(dc_rtcregister), 4);
save_pointer(NAME(dc_sysctrl_regs), 0x200/4);

4
src/mame/machine/naomibd.h
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@ -4,8 +4,8 @@
#include "machine/naomig1.h"
#include "machine/naomicrypt.h"
#define MCFG_NAOMI_BOARD_ADD(_tag, type, _eeprom_tag, _maincpu_tag, _irq_cb) \
MCFG_NAOMI_G1_ADD(_tag, type, _maincpu_tag, _irq_cb) \
#define MCFG_NAOMI_BOARD_ADD(_tag, type, _eeprom_tag, _irq_cb) \
MCFG_NAOMI_G1_ADD(_tag, type, _irq_cb) \
naomi_board::static_set_eeprom_tag(*device, _eeprom_tag);
class naomi_board : public naomi_g1_device

21
src/mame/machine/naomig1.c
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@ -27,17 +27,10 @@ naomi_g1_device::naomi_g1_device(const machine_config &mconfig, device_type type
: device_t(mconfig, type, name, tag, owner, clock),
irq_cb(*this)
{
cpu = 0;
}
void naomi_g1_device::set_maincpu_tag(const char *_maincpu_tag)
{
maincpu_tag = _maincpu_tag;
}
void naomi_g1_device::device_start()
{
cpu = machine().device<sh4_device>(maincpu_tag);
timer = timer_alloc(G1_TIMER_ID);
irq_cb.resolve_safe();
@ -234,16 +227,6 @@ READ32_MEMBER(naomi_g1_device::sb_gdlend_r)
void naomi_g1_device::dma(void *dma_ptr, UINT32 main_adr, UINT32 size, bool to_mainram)
{
sh4_ddt_dma ddt;
if(to_mainram)
ddt.destination = main_adr;
else
ddt.source = main_adr;
ddt.buffer = dma_ptr;
ddt.length = size >> 5;
ddt.size = 32;
ddt.direction = to_mainram;
ddt.channel = -1;
ddt.mode = -1;
sh4_dma_ddt(cpu, &ddt);
if(!_dma_cb.isnull())
_dma_cb(main_adr, dma_ptr, size >> 5, 32, to_mainram);
}

10
src/mame/machine/naomig1.h
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@ -2,11 +2,9 @@
#define _NAOMIG1_H_
#include "cpu/sh4/sh4.h"
#include "includes/dc.h"
#define MCFG_NAOMI_G1_ADD(_tag, type, _maincpu_tag, _irq_cb) \
#define MCFG_NAOMI_G1_ADD(_tag, type, _irq_cb) \
MCFG_DEVICE_ADD(_tag, type, 0) \
downcast<naomi_g1_device *>(device)->set_maincpu_tag(_maincpu_tag); \
downcast<naomi_g1_device *>(device)->set_irq_cb(DEVCB2_ ## _irq_cb);
class naomi_g1_device : public device_t
@ -16,9 +14,11 @@ public:
DMA_GDROM_IRQ
};
typedef delegate<void (UINT32 main_adr, void *dma_ptr, UINT32 length, UINT32 size, bool to_mainram)> dma_cb;
naomi_g1_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
void set_maincpu_tag(const char *maincpu_tag);
template<class _cb> void set_irq_cb(_cb cb) { irq_cb.set_callback(cb); }
void set_dma_cb(dma_cb _cb) { _dma_cb = _cb; }
DECLARE_ADDRESS_MAP(amap, 32);
@ -61,10 +61,10 @@ protected:
private:
UINT32 gdstar, gdlen, gddir, gden, gdst;
sh4_device *cpu;
const char *maincpu_tag;
emu_timer *timer;
devcb2_write8 irq_cb;
dma_cb _dma_cb;
void dma(void *dma_ptr, UINT32 main_adr, UINT32 size, bool to_mainram);
};

4
src/mame/machine/naomigd.h
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@ -3,8 +3,8 @@
#include "machine/naomibd.h"
#define MCFG_NAOMI_GDROM_BOARD_ADD(_tag, _image_tag, _pic_tag, _eeprom_tag, _maincpu_tag, _irq_cb) \
MCFG_NAOMI_BOARD_ADD(_tag, NAOMI_GDROM_BOARD, _eeprom_tag, _maincpu_tag, _irq_cb) \
#define MCFG_NAOMI_GDROM_BOARD_ADD(_tag, _image_tag, _pic_tag, _eeprom_tag, _irq_cb) \
MCFG_NAOMI_BOARD_ADD(_tag, NAOMI_GDROM_BOARD, _eeprom_tag, _irq_cb) \
naomi_gdrom_board::static_set_tags(*device, _image_tag, _pic_tag);
class naomi_gdrom_board : public naomi_board

4
src/mame/machine/naomim1.h
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@ -3,8 +3,8 @@
#include "naomibd.h"
#define MCFG_NAOMI_M1_BOARD_ADD(_tag, _key_tag, _eeprom_tag, _maincpu_tag, _irq_cb) \
MCFG_NAOMI_BOARD_ADD(_tag, NAOMI_M1_BOARD, _eeprom_tag, _maincpu_tag, _irq_cb) \
#define MCFG_NAOMI_M1_BOARD_ADD(_tag, _key_tag, _eeprom_tag, _irq_cb) \
MCFG_NAOMI_BOARD_ADD(_tag, NAOMI_M1_BOARD, _eeprom_tag, _irq_cb) \
naomi_m1_board::static_set_tags(*device, _key_tag);
class naomi_m1_board : public naomi_board

4
src/mame/machine/naomim2.h
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@ -3,8 +3,8 @@
#include "naomibd.h"
#define MCFG_NAOMI_M2_BOARD_ADD(_tag, _key_tag, _eeprom_tag, _maincpu_tag, _irq_cb) \
MCFG_NAOMI_BOARD_ADD(_tag, NAOMI_M2_BOARD, _eeprom_tag, _maincpu_tag, _irq_cb) \
#define MCFG_NAOMI_M2_BOARD_ADD(_tag, _key_tag, _eeprom_tag, _irq_cb) \
MCFG_NAOMI_BOARD_ADD(_tag, NAOMI_M2_BOARD, _eeprom_tag, _irq_cb) \
naomi_m2_board::static_set_tags(*device, _key_tag);
class naomi_m2_board : public naomi_board

4
src/mame/machine/naomim4.h
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@ -3,8 +3,8 @@
#include "naomibd.h"
#define MCFG_NAOMI_M4_BOARD_ADD(_tag, _key_tag, _eeprom_tag, _maincpu_tag, _irq_cb) \
MCFG_NAOMI_BOARD_ADD(_tag, NAOMI_M4_BOARD, _eeprom_tag, _maincpu_tag, _irq_cb) \
#define MCFG_NAOMI_M4_BOARD_ADD(_tag, _key_tag, _eeprom_tag, _irq_cb) \
MCFG_NAOMI_BOARD_ADD(_tag, NAOMI_M4_BOARD, _eeprom_tag, _irq_cb) \
naomi_m4_board::static_set_tags(*device, _key_tag);
class naomi_m4_board : public naomi_board

4
src/mame/machine/naomirom.h
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@ -3,8 +3,8 @@
#include "naomibd.h"
#define MCFG_NAOMI_ROM_BOARD_ADD(_tag, _eeprom_tag, _maincpu_tag, _irq_cb) \
MCFG_NAOMI_BOARD_ADD(_tag, NAOMI_ROM_BOARD, _eeprom_tag, _maincpu_tag, _irq_cb)
#define MCFG_NAOMI_ROM_BOARD_ADD(_tag, _eeprom_tag, _irq_cb) \
MCFG_NAOMI_BOARD_ADD(_tag, NAOMI_ROM_BOARD, _eeprom_tag, _irq_cb)
class naomi_rom_board : public naomi_board
{