Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-25 17:56:43 +03:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

via6522: Remove the retrigger stuff, vectrex shows the via is *that* dumb

Browse Source 
via6522: Fix the timing again
mac128: Adjust the via timing too, since the via wants to run at start of access
This commit is contained in:
Olivier Galibert 2021-03-22 21:43:12 +01:00
parent c8b532068f
commit fec6a67d4d
2 changed files with 23 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
src/devices/machine/6522via.cpp
View File

@ -776,19 +776,13 @@ u8 via6522_device::read(offs_t offset)
LOGSHIFT(" - ACR: %02x ", m_acr);
if (SI_O2_CONTROL(m_acr) || SO_O2_CONTROL(m_acr))
{
if (m_shift_timer->expire().is_never())
{
m_shift_timer->adjust(clocks_to_attotime(7) / 2); // 8 edges to start shifter from a read -- use 7 for a mac128 issue to be fixed later
LOGSHIFT(" - read SR starts O2 timer ");
}
m_shift_timer->adjust(clocks_to_attotime(7) / 2); // 7 edges to cb1 change from start of read
LOGSHIFT(" - read SR starts O2 timer ");
}
else if (SI_T2_CONTROL(m_acr) || SO_T2_CONTROL(m_acr))
{
if (m_shift_timer->expire().is_never())
{
m_shift_timer->adjust(clocks_to_attotime(m_t2ll + 2) / 2);
LOGSHIFT(" - read SR starts T2 timer ");
}
m_shift_timer->adjust(clocks_to_attotime(m_t2ll + 2) / 2);
LOGSHIFT(" - read SR starts T2 timer ");
}
else if (!SO_T2_RATE(m_acr))
{
@ -978,19 +972,13 @@ void via6522_device::write(offs_t offset, u8 data)
LOGSHIFT(" - ACR is: %02x ", m_acr);
if (SO_O2_CONTROL(m_acr) || SI_O2_CONTROL(m_acr))
{
if (m_shift_timer->expire().is_never())
{
m_shift_timer->adjust(clocks_to_attotime(8) / 2); // 8 edges to start shifter from a write
LOGSHIFT(" - write SR starts O2 timer");
}
m_shift_timer->adjust(clocks_to_attotime(6) / 2); // 6 edges to cb2 change from start of write
LOGSHIFT(" - write SR starts O2 timer");
}
else if (SO_T2_RATE(m_acr) || SO_T2_CONTROL(m_acr) || SI_T2_CONTROL(m_acr))
{
if (m_shift_timer->expire().is_never())
{
m_shift_timer->adjust(clocks_to_attotime(m_t2ll + 2) / 2);
LOGSHIFT(" - write starts T2 timer");
}
m_shift_timer->adjust(clocks_to_attotime(m_t2ll + 2) / 2);
LOGSHIFT(" - write starts T2 timer");
}
else
{

18
src/mame/drivers/mac128.cpp
View File

@ -194,6 +194,7 @@ private:
uint16_t ram_600000_r(offs_t offset);
void ram_600000_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~ 0);
void via_sync();
void via_sync_end();
uint16_t mac_via_r(offs_t offset);
void mac_via_w(offs_t offset, uint16_t data);
uint16_t mac_autovector_r(offs_t offset);
@ -692,13 +693,21 @@ void mac128_state::via_sync()
// is synced on that clock, so that's at a multiple of 10 in
// absolute time
// - 4 cycles later E goes down and that's the end of the access
// - 4 cycles later E goes down and that's the end of the access,
// We sync on the start of cycle (so that the via timings go ok)
// then on the end on via_sync_end()
uint64_t cur_cycle = m_maincpu->total_cycles();
uint64_t vpa_cycle = cur_cycle+2;
uint64_t via_start_cycle = (vpa_cycle + 9) / 10;
uint64_t end_cycle = via_start_cycle * 10 + 4;
m_maincpu->adjust_icount(cur_cycle - end_cycle + 4); // 4 cycles already counted by the core
uint64_t m68k_start_cycle = via_start_cycle * 10;
m_maincpu->adjust_icount(cur_cycle - m68k_start_cycle); // 4 cycles already counted by the core
}
void mac128_state::via_sync_end()
{
m_maincpu->adjust_icount(-4);
}
uint16_t mac128_state::mac_via_r(offs_t offset)
@ -712,6 +721,7 @@ uint16_t mac128_state::mac_via_r(offs_t offset)
data = m_via->read(offset);
via_sync_end();
return (data & 0xff) | (data << 8);
}
@ -723,6 +733,8 @@ void mac128_state::mac_via_w(offs_t offset, uint16_t data)
via_sync();
m_via->write(offset, (data >> 8) & 0xff);
via_sync_end();
}
void mac128_state::mac_autovector_w(offs_t offset, uint16_t data)