z80 was tested with pacman and m6502 was tested with apple2e.
Side-effects must be disabled before reading memory, otherwise apple2e
starts failing after the first read to 0xc080.
Since GDB doesn't support those processors, I made up the features name
with "mame.<cpuname>". I also had to choose the registers to export in
the target.xml file, and since I don't have any experience with these
processors I don't know if I made the best choice.
* gdbstub: added new GDB stub debugger
This debugger can be used to connect to an external debugger that
communicates using the GDB Remote Serial Protocol, such as GDB itself
or many other GDB frontends.
Currently i386 (ct486), arm7 (gba), and ppc (pmac6100) are supported.
* gdbstub: enable GDB stub debugger in mac and windows builds
- Replace the old-style fake I/O space with callbacks
- Add address spaces to handle remappable accesses to internal RAM and registers
- Eliminate set_config in favor of separate device types for each model (not differentiated properly yet...)
The extra operand cycle in CMOS versions becomes a dummy read rather than a writeback, and page boundaries do not figure into cycle timings for indexed modes.
Hardware reset triggers a SCSI_STATUS_RESET interrupt when the MR signal is asserted, but this is also true when the device first powers on.
Move the interrupt generation to device_reset so all hardware resets trigger the interrupt.
NOTE: MCU NOT hooked up, just fix ROM names and MCU dump only
out of whatsnew: Add in PCB locations for Birdie Try and correct ROM labels and document the PCB combo
Working for a very tiny value of working; no graphics or audio, and many things are still unimplemented. I'll bump the status when there's more to show, but this can install and boot IRIX 4.0.5 via serial console now.
This fixes a bug causing IRIX to crash on 4D/20. Specifically, IRIX doesn't handle the case where the pc is pointing to an unmapped address when an interrupt occurs; presumably on real hardware this doesn't happen because the instruction fetch happens before interrupts are tested (or the pc isn't updated until after), and the fetch exception is prioritised over the incoming interrupt.
