Subject: change for cpunum_set_irq_callback() callback function
This patch adds the running_machine* parameter to the function passed
into cpunum_set_irq_callback() and adds the IRQ_CALLBACK macro for
the callback function.
Subject: Update for "Euro League (bootleg)"
Hello,
some tiny updates for the driver wc90b.c :
-Added dumps for all GALs on the PCB
-Removed the second YM2203, it isn't present on the bootleg boards
-Changed the clocks according to the oscilators found on the board,
the previous speeds were measured on a goal92 PCB, not using a real "Euro League" PCB.
-Added a new osc to xtal.h
If you need any info about this update, please mail me.
Regards: ClawGrip (Tomas Garcia-Meras)
--
Also merged memory maps [Aaron Giles]
only remaining form is the one that takes a pointer parameter.
Added macros for STATE_PRESAVE and STATE_POSTLOAD to define common
functions. Added machine parameter to these functions.
Updated all drivers and CPU/sound cores to use the new macros
and consolidate on the single function type. As a result pushed
the machine parameter through a few initialization stacks.
Removed unnecessary postload callbacks which only marked all tiles
dirty, since this is done automatically by the tilemap engine.
trace through in a debug build, yet should operate the same as before.
Created a complete set of functions for all databus sizes (8,16,32,64) and
all endiannesses. A few functions are redundant, but it is now very clear
which functions to use in which scenarios. It is also now possible to rely
on being able to access values of 8, 16, 32 or 64 bits via the built-in
accessors without fear of crashing.
Updated all cores using 8-bit handlers to explicitly call the 8-bit handlers
with the appropriate endianness.
Fixed a few games which were calling n-bit handlers directly to use the
generic forms. In the future, this is all the access drivers will have.
fixed reading from SXYP
fixed reading from IRGB
fixed writing to LZCR
fixed sign extension of GTE control registers
fixed writing to FLAG
New games added or promoted from NOT_WORKING status
---------------------------------------------------
1 on 1 Government (JAPAN)
Added ability to test the instruction/data cache ram. The scratchpad and BIU register are now handled internally to the CPU.
All writes are performed with masks. SWL/SWR used to be implemented with two writes ( one byte and one word ) when writing three bytes, now it only ever performs one. Byte and Word writes use masks as they leave the rest of the register on the bus, which can be picked up by larger registers.
The read/write functions to use are cached when the SR bits are updated, as are the bad address masks.
Added coprocessor 1 & 3 support, though they don't do anything useful.
All loads now go through the delay pipeline, a lwl/lwr will grab the value out of the pipeline if it's updating the same register.
Added undocumented behaviour of BLEZ/BGTZ. The comparison for zero can be changed by specifying an alternate register in the RT field ( the documentation says you should always use register 0 ).
Restricted to 16 COP0 registers & generate an exception if any of the 5 for the MMU are used.
Added BCF/BCT instructions, although I have found no conditions that affect them yet.
Generates an exception if any MMU instructions are executed.
Sets the CE instruction for all exceptions, not just those involving a coprocessor. The bits of the opcode that specify the coprocessor are grabbed no matter what the instruction.
Added TAR register and BT bit in SR. When an exception occurs during a branch, BT determines whether it was taken or not. The TAR register gets set to the destination of the branch.
Fixed the BD bit when you are in a branch delay slot and you didn't take the branch, this shows up in the pipeline as !pc.
Fixed branches within a branch delay slot.
Multiply & divide instructions can be aborted if you write to HI/LO before reading the result.
Added data breakpoints, you don't appear to be able to set breakpoints on any of the addresses internal to the CPU.
Multiply/divide/GTE instructions can execute when an exception is taken, although the EPC indicates that it hasn't. The BIOS avoids rerunning GTE instructions as they are destructive, so you have to make sure they run.
Added bus error handling, PSXCPU is limited to 8mb of ram & any access outside this range will trigger an exception. I believe this is to be an internal limit.
Added CXD8611R as a specific CPU type, System 12 appears to allow more than 8mb of ram & it's possible that this is different.
Mapped out all instructions to either generate an exception or ignore bits.
Updated the disassembler to match the decoding.
Fixed disassembling of branch instructions in a branch delay slot.
Lui checks for a ori/addiu following and will show you the result.
Added step over/out support.
Fixed standalone disassembler.
Rewrote INP recording from scratch, since all old INPs are broken anyways.
Header now includes timestamp, which overrides the default time base for MAME's system time.
Each frame recorded now gets a timestamp.
Analog ports are recorded once per frame and interpolated.
Analog port calculations are all done in fixed point for consistent results.
A bunch of other minor tweaks in the input port code.
There may still be a few changes to the final INP format (considering adding
NVRAM data directly in the INP file, for example....) but this at least seems
to work for the games I've tried.
All custom itemids were mapped to class SWITCH. With the recent modification, this implicitly changed to ABSOLUTE.
This fix will use the passed itemid to determine the class.
Subject: pit8253 device
I have converted the pit8253 implementation into a device. To make it
easier to use I've also created a src/emu/devconv.h in the same style
as src/emu/memconv.h.
I do not have all roms/disk images to test all drivers. I have only
been able to test pf2012, filetto, and topgunnr.
Subject: Further ACIA changes
Added dynamic control of RX and TX pins to 6850 ACIA emulation - this is
needed for correct operation of the MPU4 Video communications system,
and may be handy for some MESS systems. To use, set the rx and tx clocks
to 0 in the acia interface, then use acia_tx_clock_in() and
acia_rx_clock_in() respectively.
Subject: small change for MESS cleanup
This adds the "Machine" parameter to a MESS function call in MAME
code to go along with Machine -> machine ckeanups in MESS
Subject: Machine -> machine cleanups
This patch changes "Machine" to "machine", when the runnin-machine
parameter is already available. In some cases I could even remove the
dprecat.h.
I will look for some occurances where it can be easily changed and
afterward take a step at adding the running_machine parameter in a
few places.
* Fix timing of stream_update in discrete_sound_w
All sound cores update before processing changed data
* Add streeam_update to discrete_sound_r
* Now supports multiple output nodes per module.
There is the possibility to support multiple outputs per module.
In this case, NODE_XXX is the default output. Alternative outputs may
be accessed by using NODE_XXX_YY where 00<Y<08.
You may also access nodes with macros:
NODE_XXX = NODE_SUB(XXX, 0)
NODE_XXX = NODE(XXX)
NODE_XXX_YY = NODE_SUB(XXX, YY) with YY != 00
This should e.g. make discrete sound emulation easier
when dealing with e.g. flip flops (Q & QQ) and binary counters
* added sanity checks to check consistency issues introduced by this change
* modules specify number of outputs ==> Certain special modules (WAVELOG)
may no longer be used as input nodes
* removed explicit (NODE_XX + expr) from a couple of drivers
All occurrences of ACCESSING_LSB, ACCESSING_MSB, ACCESSING_LSB16, ACCESSING_MSB16, ACCESSING_LSB32, ACCESSING_MSB32, ACCESSING_LSW32, ACCESSING_MSW32 & simple mem_mask checks have been replace with the new macros.
The old macros are gone.
