- Simplified ROM/RAM banking.
- Added Alpha and Numerical keyboards for POS variants.
- Applied software list filters.
- Added topslot for Organiser II variants.
- Removed fake LZ64S model, ROMs moved to LZ64.
psion/psion_pack.cpp: Allow setting image_interface.
New working clones
------------------
Organiser II Alpha POS 200 [Nigel Barnes, Jaap Scherphuis]
Organiser II P 250 [Nigel Barnes, Jaap Scherphuis]
Organiser II P 432 [Nigel Barnes, Jaap Scherphuis]
* Made interrupt check function generate far more compact code (about
85% reduction in number of native instructions on x86-64).
* Optimised out-of-cycles check.
* Applied prior optimisation for trap/interrupt checks to static
exception checks as well (code is still copy/pasted).
* Hi-hat decay knob is now working.
* Open and closed hats have different decays.
* Better default tuning for the snare.
* Removed `strobe_` prefix from functions where it was redundant. Made it an argument in a function where it matters.
New systems marked not working
------------------------------
MICE-IIIS 68000 [ArcadeHacker]
Also renamed "Microtek International" to just "Microtek" as manufacturer name on the driver for older MICE models (the commercial brand was "Microtek", without any suffix).
New systems marked not working
------------------------------
Turnier Dart [Victor Fernandez (City Game)]
New clones marked not working
------------------------------
Turnier Dart (HB8-97) [Victor Fernandez (City Game)]
- igs/spoker.cpp: dumped missing GFX ROM for jinhulu2101is and cjdh6. Renamed cjdh6 to huahuas2a as it was misnamed [little0]
- igs/spoker.cpp: implemented more tile banking bits following Haze's IGS033 implementation, gives correct GFX for the sets which use that chip without breaking the ones using the IGS001 / IGS002 combo
* Tatsumi code location shuffle
* put the wrong class name here
* chip type difference is definitely not the CLUT size, which is weird, but now confirmed on a PCB.
---------
Co-authored-by: David Haywood <hazemamewip@hotmail.com>
* Cleaned up and commented code for generating an exception, reducing
about nine memory accesses to update SR to two.
* Implemented NEGS, and fixed ADDS and SUBS not setting excption handler
address.
* Optimised code to update Z flag on logic operations to avoid branches.
* Reduced copy/paste a bit more.
------------------------------
Da Fu Wang III (V130LI) [Dr.Liu(BJ), little0]
Huahua Shijie II (v100FI) [Dr.Liu(BJ), little0]
Hua Sheng II (v120DI) [Dr.Liu(BJ), little0]
Hu Lu Wang II (v100KI) [Dr.Liu(BJ), little0]
Jin Huang Guan [Dr.Liu(BJ), little0]
Shuiguo Leyuan (V150UI) [Dr.Liu(BJ), little0]
Zuanshi Wutai (V110II) [Dr.Liu(BJ), little0]
New clones marked not working
-----------------------------
Jin Hu Lu II (v100GI) [Dr.Liu(BJ), little0]
cpu/e132xs.cpp: Refactored code generation to improve performance and
fixed some issues:
* Moved a considerable amound of logic from execution time to code
generation time.
* Fixed some cases where add/subtract carry was being interpreted
incorrectly.
* Fixed a case where a load double intruction was incorrectly writing
the same register twice.
* Use UML flags to generate condition codes for addition/subtraction.
* Use UML carry flag for carry-/borrow-in.
* Reduced UML register pressure (improves performance for hosts with
fewer callee-saved CPU registers).
* Moved more logic to helper functions to simplify maintenance.
cpu/drcbex64.cpp: Fixed upper bits of UML registers being cleared when
used as address offset for LOAD/STORE.
cpu/drcbex64.cpp: Don't do expensive zero/sign flag update for shift
operations if only carry flag will be used.
cpu/drcbex64.cpp: Reduced copy/paste in READ[M]/WRITE[M] generators.
- Added a default NVRAM to fastdrwp.
- Derivated inputs for fasdrwp.
- Added buttons-lamps layout for fastdrwp.
- Promoted fastdrwp set to working.
Systems promoted to working
---------------------------
Fast Draw (poker conversion kit) [Roberto Fresca, Grull Osgo]
Sega Rally has an instruction that calculates d += p and loads a value into d at the same time; it is the loaded value that should be used, not the result of the ALU operation
Also only test the d register when performing an ALU operation
cpu/drcbex64.cpp: Avoid a lot of unnecessary flag manipulation on
shift/rotate operations. Don't calculate flags when not requested.
Don't preserve carry in for operations that don't use it as an input.
cpu/drcbex64.cpp: Avoid loading CL when ECX can be used. Loading CL
doesn't clear the upper bits, so it depends on the previous value of
RCX, causing pipeline dependencies. Loading ECX can grab a fresh rename
register.
cpu/drcbearm64.cpp: Attempt more optimisation on one more load immediate
operation.
cpu/e132xs: Get rid of a redundant TEST - ROLAND can set the Z flag.
