Game is now playable
New games added or promoted from NOT_WORKING status
---------------------------------------------------
Double Dealer [Angelo Salese,David Haywood]
* Remaining games checked and adapted to changes in cpu core
* Cardline still broken. I need the exact and complete cpu name.
* Added more variants 803X, 80CXX, AT89C4051
* Fix segas18.c (segaic16.c) mcu maps.
* Fix sslam.c
* Fix limenko.c videopkr.c : Issue with core allocation of ram (duplicate savestate)
Yet another 8-bit Incredible Technologies board. Different in several
significant ways from previous models:
* YM2608B for audio, replacing YM3812+OKI6295
* TMS34070 for palettes instead of PC RAMDAC
* Different video memory layout
* improved serial port timing (f15se (micro3d.c) sound board now works)
* better infrastructure for adding more variants like DS5002
* Fixed port reading
* Rewrote Macros for better readibility
* Fixed and rewrote Interrupt handling
* Now returns INTERNAL_DIVIDER, adjusted cycle counts
* Remove unnecessary and duplicated code
* Remove unnecessary functions
* Rewrite to have sfr-registers stored in int_ram.
* Debugger may now watch sfr-registers as well.
* implemented interrupt callbacks (HOLD_LINE now supported)
* Runtime switch for processor type - remove ifdefs
* internal memory maps for internal rom versions (internal ram now displayed in debugger)
* more timer cleanups from manual
micro3d:
* serial port communication between main cpu and sound board works
* sound board now works
m72 - lohtb2:
* full emulation of protection device
* Samples are now piped through the mcu
* Added additional branch, move and bitfield ops.
* Plygonet now passes its memory test and uploads a new program.
[[Next step is to install an opbase handler and let the dsp56k run further into its new proggie.]]
Game is now playable
New games added or promoted from NOT_WORKING status
---------------------------------------------------
(Medal) Yumefuda [Bet] [Angelo Salese]
* Complete rewrite focusing on legibility and extensibility.
* 27/121 opcodes (mostly) implemented.
* Bugfix for reset status of interrupt priority bits.
* Bugfix for disassembly of register-to-register parallel data move.
[[These changes bring the driver up to the point where the plygonet hardware begins banking memory. The behavior is understood, so I should have the driver back to where it was before the rewrite soon. Then real progress can be made.]]
(also added a to-check note, 16-bit wide DMA is currently using 32-bit functions, is this correct?)
Removed Speedups from CPS3 / PsikyoSH, while they do still give a decent speed boost they're not really needed with the DRC and just clutter the code.
