Commit Graph

17 Commits

Author SHA1 Message Date
DavidHaywood
10e3dba1d0 xavix - store the extra codebank byte in a private stack when making long calls etc. (fixes crash on calibration screen in rad_hnt2)
this seems feasible as it's an extension to the CPU, so keeping it in a private stack would maintain better compatibility with 6502 code
2019-06-14 21:22:24 +01:00
David Haywood
4af89199f5 XaviX - looking at more timers (nw) (#4299)
* XaviX - looking at more timers (nw)

* fix crash with ekara -cart1 ec0015 song 1, confirms other indirect opcodes must bypass lowbus

* (nw)

* and this hack can go away now (nw)
2018-11-14 19:34:39 -05:00
David Haywood
9e016b9510 XaviX - revert some previous changes that didn't have desired effect and caused an issue (#4197)
* partial revert of previous changes that were problematic (nw)

* improve handling of some SuperXaviX opcodes (nw)
2018-10-26 10:15:28 -04:00
David Haywood
25b70ce773 XaviX - support per-line rendering and raster interrupts (#4180)
* checkpoint (nw)

* improve rasters (nw)

* improve again (nw)

* raster effect improvements (nw)

* tidy (nw)

* keep happy (nw)

* also keep things happy (nw)

* rad_rh notes (nw)

* kill unneeded code (nw)

* (nw)

* oops (nw)

* extra rad_bass inputs (nw)

* misc refactors (nw)

* 2nd palette on superxavix (nw)

* improvements to line renderer (nw)

* optimize slightly (nw)

* bitmap layer related (nw)

* this bitmap in xavtennis is very big (nw)
2018-10-22 21:35:02 -04:00
David Haywood
8143ab0dc0 XaviX - first pass at allowing some opcodes to bypass zero page (fixes namcons1 and others) (#4157)
* XaviX - irst pass at allowing some opcodes to bypass zero page (fixes namcons1 and others)

* dirt rebel bits (nw)

* dirt rebel (nw)

* xavtenni (nw)
2018-10-18 21:11:22 -04:00
David Haywood
441d067878 XaviX - get ttv_mx to show some screens (nw) (#4153)
* on review of code I'm fairly sure these work with the accumulator (nw)

* get ttv_mx to show some screens (nw)

* oops (nw)

* more ops (nw)

* (nw)

* help xavtenni along (nw)

* less logging (nw)
2018-10-17 16:35:39 -04:00
Vas Crabb
c15531dddc srcclean (nw) 2018-05-27 04:48:13 +10:00
Olivier Galibert
4c24f25845 emumem: Rename direct_read_handler to memory_access_cache. Parametrize the template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert] 2018-05-11 18:23:04 +09:00
David Haywood
6627a9e480 start looking at the extra opcodes in the SSD 2000 type XaviX chip (s… (#3514)
* start looking at the extra opcodes in the SSD 2000 type XaviX chip (seems some undocumented 6502 opcodes are replaced with more custom ones)

* (nw)

* the xavix memory mapping gets stranger with each piece of new evidence (nw)
2018-05-04 12:22:18 -04:00
Vas Crabb
ac79c90607 srcclean (nw) 2018-04-22 09:24:13 +10:00
David Haywood
261bcfa3cd XaviX - current checkpoint, tidying, reorganization etc. (+ general TV game work) (#3450)
* xavix - tidy ups, reorganization, current notes etc.

* didn't mean to push a copy (nw)

* shift some common code around for palette handling (nw)

* lean less heavily on memory system (nw)

* revert 'shift some common code around for palette handling (nw)' to be revisited later.

* add missed include guards (nw)

* new machines marked as NOT WORKING
Skannerz TV [Sean RIddle, Peter Wilhelmsen]

This will need the communication protocol with the barcode scanner unit reverse engeering (the scanner unit has it's own MCU that isn't dumped and for which we have no method of dumping) this also probably means it will need improvements to the general vii.cpp handling of interrupts and serial ports (which Cricket needs too)
2018-04-16 22:34:42 -04:00
Vas Crabb
8142f24c43 don't pass so many naked pointers around (nw) 2018-03-25 01:44:45 +11:00
Vas Crabb
8dad4881f6 srcclean (nw) 2018-02-25 01:34:04 +11:00
David Haywood
f2caf3fbb0 xavix - some changes to keep code running better, I think it's trying… (#3180)
* xavix - some changes to keep code running better, I think it's trying to do a palette writes at 6800/6900 before crashing now (nw)

* new machines marked as NOT WORKING
Play TV Monster Truck [Sean Riddle, Peter Wilhelmsen]

* experiments (nw)

* ram address 0xff (internal ram / zero page ram) is used to bank data reads at 0x8000 (the equiavlent of how the custom ocpods bank code reads there instead)
2018-02-08 16:03:57 -05:00
Olivier Galibert
38306e6b27 m6502: Fixed paged variants tracing and breakpoints [O. Galibert] 2018-02-07 18:20:33 +01:00
David Haywood
2c592e7f14 xavix - generate some interrupts, code runs a lot better now (nw) (#3174)
* new machines marked as NOT WORKING - Play TV Ping Pong [Sean Riddle]

The code on this one is much closer to Taito Nostalgia, seemingly only using the callfar / returnfar extended opcodes, this further makes me think that XaviX Tennis is a Super XaviX title instead.

* some guesswork (nw)

* it sure *looks* like the dma (nw)

* xavix - generate some interrupts, code runs a lot better now (nw)
2018-02-06 19:37:26 -05:00
David Haywood
1e09ab0ceb create derived 6502 type for XaviX because it has at least one custom… (#3154)
* create derived 6502 type for XaviX because it has at least one custom 4-byte opcode that doesn't fit any other type.
treating that opcode as NOP for now.

have a feeling it might be something to do with the other integrated hardware, might be 'execute co-processor code chain at this address' or something similar
It isn't a standard JSL (Jump Subroutine Long)  like the SNES cpu opcode in the same place as this, it seems to point at some code-like structures tho)
could also be a secondary operation mode with different encoding like ARM's Thumb mode tho I guess.

We currently only have a single XaviX based dump (taitons1) but there are more on the way.  I'm going to see if the code flow makes any sense at all with these missing, or if any of it gives a clue as to what they should actually do.

* xavix - let's call these callf and retf then

after further investigation these are some kind of extra 'long jump' subroutine / task handlers, the 0x80 also being a custom opcode was throwing me off trying to identify them before.

looks like they might have been hacking 65816 features into the regular 6502 core?

* prepare for extra address bits (nw)

* better program flow (nw)
2018-02-02 14:34:12 -05:00