7 Commits

Author	SHA1	Message	Date
mamehaze	f354ad36e0	speculative notes (nw)	2015-03-12 16:20:35 +00:00
mamehaze	6d56aa957c	expose some more V53 pins for the internal peripherals to the outside world (nw) ... timers seem very active, does some DMA ops (transfering a big block of 0 data) a few times on startup, then stops.. maybe because no interrupts happen. interrupt table looks.. weird, need to understand how it configures the interrupt controller and what that means. there are port writes to low port numbers, writes to port 0x0000 in the format with data in the format 0x??00 0x??01 0x??02 0x??03 0x??04 0x??05 0x??06 0x??07 0x??08 0x??09 0x??0a 0x??0b 0x??0c 0x??0d 0x??0e 0x??0f 0x??10 0x??11 0x??12 0x??13 0x??14 0x??15 0x??16 0x??17 0x??18 0x??19 0x??1a 0x??1b 0x??1c 0x??1d 0x??1e 0x??1f and after each write to port 0 with those values it writes some other data to ports 2,4,6. if the information is correct, and this is a 32-channel based sound system, then that could well be some kind of configuration for the channels.	2015-03-10 21:48:56 +00:00
mamehaze	d28b18c415	it now attempts to do a whole bunch of 0x20 sized transfers from RAM (0xcfe8 - 0xd007) to DMA port 3 shortly after startup... (nw)	2015-03-09 00:05:41 +00:00
mamehaze	41b78b9efd	carl noted that this seems to be the same thing, and is more complete, so use it instead (nw)	2015-03-08 21:21:35 +00:00
mamehaze	bb75bf30c6	hng64 / v53 - looking at DMA (nw)	2015-03-08 16:22:52 +00:00
mamehaze	37bf50f2bc	few bits of v53 stuff, start dynamic peripheral mapping, attempts to set up timers at least (nw)	2015-03-08 11:56:50 +00:00
mamehaze	04e15f745f	shuffle more HNG64 stuff around, add stub CPU classes for the different CPU types it uses so that we can start implementing the peripherals properly rather than hacking them into the driver (nw)	2015-03-07 22:42:15 +00:00