mirror of
https://github.com/holub/mame
synced 2025-06-04 03:46:29 +03:00
1a899d987f
device_add_mconfig modernization. [Ryan Holtz] -amiga_dmac: Replaced old devcb with devcb3. [Ryan Holtz] -mc6854, ataintf, mb89352, mc6854, wd33c93: Added devcb3 support. [Ryan Holtz] -8042kbdc, i8255, idectrl, intelfsh, mb89352, ram, wd33c93, volt_reg: Default clocks to 0 (nw) -bebox, indy_indigo2: machine_config modernization. [Ryan Holtz]
130 lines
4.5 KiB
C++
130 lines
4.5 KiB
C++
// license:BSD-3-Clause
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// copyright-holders:smf
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/***************************************************************************
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idectrl.h
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Generic (PC-style) IDE controller implementation.
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***************************************************************************/
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#ifndef MAME_MACHINE_IDECTRL_H
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#define MAME_MACHINE_IDECTRL_H
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#pragma once
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#include "ataintf.h"
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/***************************************************************************
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DEVICE CONFIGURATION MACROS
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***************************************************************************/
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#define MCFG_IDE_CONTROLLER_ADD(_tag, _slot_intf, _master, _slave, _fixed) \
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MCFG_DEVICE_ADD(_tag, IDE_CONTROLLER, 0) \
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MCFG_DEVICE_MODIFY(_tag ":0") \
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MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _master, _fixed) \
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MCFG_DEVICE_MODIFY(_tag ":1") \
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MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _slave, _fixed) \
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MCFG_DEVICE_MODIFY(_tag)
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class ide_controller_device : public abstract_ata_interface_device
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{
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public:
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ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
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uint16_t read_cs0(offs_t offset, uint16_t mem_mask = 0xffff);
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uint16_t read_cs1(offs_t offset, uint16_t mem_mask = 0xffff);
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void write_cs0(offs_t offset, uint16_t data, uint16_t mem_mask = 0xffff);
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void write_cs1(offs_t offset, uint16_t data, uint16_t mem_mask = 0xffff);
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DECLARE_READ16_MEMBER(cs0_r) { return read_cs0(offset, mem_mask); }
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DECLARE_READ16_MEMBER(cs1_r) { return read_cs1(offset, mem_mask); }
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DECLARE_WRITE16_MEMBER(cs0_w) { write_cs0(offset, data, mem_mask); }
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DECLARE_WRITE16_MEMBER(cs1_w) { write_cs1(offset, data, mem_mask); }
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protected:
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ide_controller_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
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};
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DECLARE_DEVICE_TYPE(IDE_CONTROLLER, ide_controller_device)
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#define MCFG_IDE_CONTROLLER_32_ADD(_tag, _slot_intf, _master, _slave, _fixed) \
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MCFG_DEVICE_ADD(_tag, IDE_CONTROLLER_32, 0) \
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MCFG_DEVICE_MODIFY(_tag ":0") \
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MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _master, _fixed) \
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MCFG_DEVICE_MODIFY(_tag ":1") \
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MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _slave, _fixed) \
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MCFG_DEVICE_MODIFY(_tag)
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class ide_controller_32_device : public abstract_ata_interface_device
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{
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public:
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ide_controller_32_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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uint32_t read_cs0(offs_t offset, uint32_t mem_mask = 0xffffffff);
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uint32_t read_cs1(offs_t offset, uint32_t mem_mask = 0xffffffff);
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void write_cs0(offs_t offset, uint32_t data, uint32_t mem_mask = 0xffffffff);
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void write_cs1(offs_t offset, uint32_t data, uint32_t mem_mask = 0xffffffff);
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DECLARE_READ32_MEMBER(cs0_r) { return read_cs0(offset, mem_mask); }
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DECLARE_READ32_MEMBER(cs1_r) { return read_cs1(offset, mem_mask); }
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DECLARE_WRITE32_MEMBER(cs0_w) { write_cs0(offset, data, mem_mask); }
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DECLARE_WRITE32_MEMBER(cs1_w) { write_cs1(offset, data, mem_mask); }
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protected:
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ide_controller_32_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
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};
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DECLARE_DEVICE_TYPE(IDE_CONTROLLER_32, ide_controller_32_device)
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#define MCFG_BUS_MASTER_IDE_CONTROLLER_ADD(_tag, _slot_intf, _master, _slave, _fixed) \
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MCFG_DEVICE_ADD(_tag, BUS_MASTER_IDE_CONTROLLER, 0) \
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MCFG_DEVICE_MODIFY(_tag ":0") \
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MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _master, _fixed) \
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MCFG_DEVICE_MODIFY(_tag ":1") \
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MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _slave, _fixed) \
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MCFG_DEVICE_MODIFY(_tag)
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#define MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(bmcpu, bmspace) \
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downcast<bus_master_ide_controller_device &>(*device).set_bus_master_space(bmcpu, bmspace);
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class bus_master_ide_controller_device : public ide_controller_32_device
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{
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public:
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bus_master_ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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void set_bus_master_space(const char *bmcpu, uint32_t bmspace) { m_bmcpu = bmcpu; m_bmspace = bmspace; }
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DECLARE_READ32_MEMBER( bmdma_r );
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DECLARE_WRITE32_MEMBER( bmdma_w );
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protected:
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virtual void device_start() override;
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virtual void set_irq(int state) override;
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virtual void set_dmarq(int state) override;
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private:
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void execute_dma();
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const char *m_bmcpu;
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uint32_t m_bmspace;
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address_space *m_dma_space;
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uint8_t m_dma_address_xor;
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offs_t m_dma_address;
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uint32_t m_dma_bytes_left;
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offs_t m_dma_descriptor;
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uint8_t m_dma_last_buffer;
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uint8_t m_bus_master_command;
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uint8_t m_bus_master_status;
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uint32_t m_bus_master_descriptor;
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int m_irq;
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int m_dmarq;
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};
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DECLARE_DEVICE_TYPE(BUS_MASTER_IDE_CONTROLLER, bus_master_ide_controller_device)
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#endif // MAME_MACHINE_IDECTRL_H
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