25b6f6a58d
Notes: - for whatever reason the tlcs_z80 internal CTC fails to recognize/find its owner tag, does anyone know how to fix this? it's probably trivial, but I need an helping hand or pve500 cannot be launched anymore... - @Haze: can you check your inder_sb.c code? your CTC interface was wrong, judging from the comments in the source (the first cb was for the interrupt, and no callback was present by default for the ZC/TO3...) and I'm not sure what the code is intended to actually do
190 lines
3.9 KiB
C
190 lines
3.9 KiB
C
/***************************************************************************
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MC-80.xx by Miodrag Milanovic
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15/05/2009 Initial implementation
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12/05/2009 Skeleton driver.
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****************************************************************************/
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#include "includes/mc80.h"
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/*****************************************************************************/
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/* Implementation for MC80.2x */
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/*****************************************************************************/
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IRQ_CALLBACK_MEMBER(mc80_state::mc8020_irq_callback)
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{
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return 0x00;
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}
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MACHINE_RESET_MEMBER(mc80_state,mc8020)
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{
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}
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WRITE_LINE_MEMBER( mc80_state::ctc_z0_w )
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{
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}
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WRITE_LINE_MEMBER( mc80_state::ctc_z1_w )
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{
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}
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WRITE_LINE_MEMBER(mc80_state::ctc_z2_w)
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{
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downcast<z80ctc_device *>(machine().device("z80ctc"))->trg0(state);
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downcast<z80ctc_device *>(machine().device("z80ctc"))->trg1(state);
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}
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READ8_MEMBER( mc80_state::mc80_port_b_r )
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{
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return 0;
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}
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READ8_MEMBER( mc80_state::mc80_port_a_r )
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{
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return 0;
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}
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WRITE8_MEMBER( mc80_state::mc80_port_a_w )
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{
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}
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WRITE8_MEMBER( mc80_state::mc80_port_b_w )
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{
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}
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Z80PIO_INTERFACE( mc8020_z80pio_intf )
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{
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DEVCB_NULL, /* callback when change interrupt status */
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DEVCB_DRIVER_MEMBER(mc80_state, mc80_port_a_r),
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DEVCB_DRIVER_MEMBER(mc80_state, mc80_port_a_w),
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DEVCB_NULL,
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DEVCB_DRIVER_MEMBER(mc80_state, mc80_port_b_r),
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DEVCB_DRIVER_MEMBER(mc80_state, mc80_port_b_w),
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DEVCB_NULL
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};
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/*****************************************************************************/
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/* Implementation for MC80.3x */
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/*****************************************************************************/
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WRITE8_MEMBER( mc80_state::mc8030_zve_write_protect_w )
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{
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}
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WRITE8_MEMBER( mc80_state::mc8030_vis_w )
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{
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// reg C
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// 7 6 5 4 -- module
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// 3 - 0 left half, 1 right half
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// 2 1 0
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// =====
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// 0 0 0 - dark
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// 0 0 1 - light
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// 0 1 0 - in reg pixel
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// 0 1 1 - negate in reg pixel
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// 1 0 x - operation code in B reg
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// reg B
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//
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UINT16 addr = ((offset & 0xff00) >> 2) | ((offset & 0x08) << 2) | (data >> 3);
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static const UINT8 val[] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
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int c = offset & 1;
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m_p_videoram[addr] = m_p_videoram[addr] | (val[data & 7]*c);
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}
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WRITE8_MEMBER( mc80_state::mc8030_eprom_prog_w )
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{
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}
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IRQ_CALLBACK_MEMBER(mc80_state::mc8030_irq_callback )
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{
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return 0x20;
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}
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MACHINE_RESET_MEMBER(mc80_state,mc8030)
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{
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}
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READ8_MEMBER( mc80_state::zve_port_a_r )
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{
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return 0xff;
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}
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READ8_MEMBER( mc80_state::zve_port_b_r )
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{
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return 0xff;
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}
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WRITE8_MEMBER( mc80_state::zve_port_a_w )
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{
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}
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WRITE8_MEMBER( mc80_state::zve_port_b_w )
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{
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}
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Z80PIO_INTERFACE( mc8030_zve_z80pio_intf )
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{
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DEVCB_CPU_INPUT_LINE("maincpu", INPUT_LINE_IRQ0), /* callback when change interrupt status */
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DEVCB_DRIVER_MEMBER(mc80_state, zve_port_a_r),
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DEVCB_DRIVER_MEMBER(mc80_state, zve_port_a_w),
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DEVCB_NULL,
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DEVCB_DRIVER_MEMBER(mc80_state, zve_port_b_r),
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DEVCB_DRIVER_MEMBER(mc80_state, zve_port_b_w),
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DEVCB_NULL
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};
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READ8_MEMBER( mc80_state::asp_port_a_r )
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{
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return 0xff;
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}
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READ8_MEMBER( mc80_state::asp_port_b_r )
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{
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return 0xff;
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}
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WRITE8_MEMBER( mc80_state::asp_port_a_w )
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{
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}
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WRITE8_MEMBER( mc80_state::asp_port_b_w )
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{
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}
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Z80PIO_INTERFACE( mc8030_asp_z80pio_intf )
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{
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DEVCB_CPU_INPUT_LINE("maincpu", INPUT_LINE_IRQ0), /* callback when change interrupt status */
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DEVCB_DRIVER_MEMBER(mc80_state, asp_port_a_r),
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DEVCB_DRIVER_MEMBER(mc80_state, asp_port_a_w),
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DEVCB_NULL,
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DEVCB_DRIVER_MEMBER(mc80_state, asp_port_b_r),
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DEVCB_DRIVER_MEMBER(mc80_state, asp_port_b_w),
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DEVCB_NULL
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};
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// SIO CH A in = keyboard; out = beeper; CH B = IFSS (??)
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Z80SIO_INTERFACE( mc8030_asp_z80sio_intf )
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{
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0, 0, 0, 0,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL
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};
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