mirror of
https://github.com/holub/mame
synced 2025-06-03 11:26:56 +03:00
3598b772bc
The purpose of making it const before was to discourage direct tampering,
but private/protected does a better job of that now anyhow, and it is
annoying now.
s/const[ \t]+address_space\b/address_space/g;
Is basically what I did.
180 lines
4.9 KiB
C
180 lines
4.9 KiB
C
/*****************************************************************************
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*
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* sh2common.h
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*
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* SH-2 non-specific components
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*
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*****************************************************************************/
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#pragma once
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#ifndef __SH2COMN_H__
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#define __SH2COMN_H__
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#define USE_SH2DRC
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#ifdef USE_SH2DRC
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#include "cpu/drcfe.h"
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#include "cpu/drcuml.h"
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#include "cpu/drcumlsh.h"
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#endif
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#define SH2_CODE_XOR(a) ((a) ^ NATIVE_ENDIAN_VALUE_LE_BE(2,0))
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typedef struct _irq_entry irq_entry;
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struct _irq_entry
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{
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int irq_vector;
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int irq_priority;
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};
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enum
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{
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ICF = 0x00800000,
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OCFA = 0x00080000,
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OCFB = 0x00040000,
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OVF = 0x00020000
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};
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#define T 0x00000001
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#define S 0x00000002
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#define I 0x000000f0
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#define Q 0x00000100
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#define M 0x00000200
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#define AM 0xc7ffffff
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#define FLAGS (M|Q|I|S|T)
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#define Rn ((opcode>>8)&15)
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#define Rm ((opcode>>4)&15)
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#define CPU_TYPE_SH1 (0)
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#define CPU_TYPE_SH2 (1)
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#define REGFLAG_R(n) (1 << (n))
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/* register flags 1 */
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#define REGFLAG_PR (1 << 0)
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#define REGFLAG_MACL (1 << 1)
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#define REGFLAG_MACH (1 << 2)
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#define REGFLAG_GBR (1 << 3)
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#define REGFLAG_VBR (1 << 4)
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#define REGFLAG_SR (1 << 5)
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#define CHECK_PENDING_IRQ(message) \
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do { \
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int irq = -1; \
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if (sh2->pending_irq & (1 << 0)) irq = 0; \
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if (sh2->pending_irq & (1 << 1)) irq = 1; \
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if (sh2->pending_irq & (1 << 2)) irq = 2; \
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if (sh2->pending_irq & (1 << 3)) irq = 3; \
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if (sh2->pending_irq & (1 << 4)) irq = 4; \
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if (sh2->pending_irq & (1 << 5)) irq = 5; \
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if (sh2->pending_irq & (1 << 6)) irq = 6; \
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if (sh2->pending_irq & (1 << 7)) irq = 7; \
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if (sh2->pending_irq & (1 << 8)) irq = 8; \
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if (sh2->pending_irq & (1 << 9)) irq = 9; \
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if (sh2->pending_irq & (1 << 10)) irq = 10; \
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if (sh2->pending_irq & (1 << 11)) irq = 11; \
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if (sh2->pending_irq & (1 << 12)) irq = 12; \
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if (sh2->pending_irq & (1 << 13)) irq = 13; \
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if (sh2->pending_irq & (1 << 14)) irq = 14; \
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if (sh2->pending_irq & (1 << 15)) irq = 15; \
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if ((sh2->internal_irq_level != -1) && (sh2->internal_irq_level > irq)) irq = sh2->internal_irq_level; \
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if (irq >= 0) \
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sh2_exception(sh2,message,irq); \
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} while(0)
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typedef struct
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{
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UINT32 ppc;
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UINT32 pc;
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UINT32 pr;
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UINT32 sr;
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UINT32 gbr, vbr;
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UINT32 mach, macl;
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UINT32 r[16];
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UINT32 ea;
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UINT32 delay;
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UINT32 cpu_off;
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UINT32 dvsr, dvdnth, dvdntl, dvcr;
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UINT32 pending_irq;
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UINT32 test_irq;
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UINT32 pending_nmi;
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INT32 irqline;
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UINT32 evec; // exception vector for DRC
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UINT32 irqsr; // IRQ-time old SR for DRC
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UINT32 target; // target for jmp/jsr/etc so the delay slot can't kill it
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irq_entry irq_queue[16];
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int pcfsel; // last pcflush entry set
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int maxpcfsel; // highest valid pcflush entry
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UINT32 pcflushes[16]; // pcflush entries
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INT8 irq_line_state[17];
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device_irq_callback irq_callback;
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legacy_cpu_device *device;
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address_space *program;
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address_space *internal;
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UINT32 *m;
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INT8 nmi_line_state;
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UINT16 frc;
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UINT16 ocra, ocrb, icr;
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UINT64 frc_base;
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int frt_input;
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int internal_irq_level;
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int internal_irq_vector;
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int icount;
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emu_timer *timer;
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emu_timer *dma_timer[2];
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int dma_timer_active[2];
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int is_slave, cpu_type;
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int (*dma_callback_kludge)(UINT32 src, UINT32 dst, UINT32 data, int size);
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void (*ftcsr_read_callback)(UINT32 data);
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#ifdef USE_SH2DRC
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drccache * cache; /* pointer to the DRC code cache */
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drcuml_state * drcuml; /* DRC UML generator state */
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drcfe_state * drcfe; /* pointer to the DRC front-end state */
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UINT32 drcoptions; /* configurable DRC options */
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/* internal stuff */
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UINT8 cache_dirty; /* true if we need to flush the cache */
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/* parameters for subroutines */
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UINT64 numcycles; /* return value from gettotalcycles */
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UINT32 arg0; /* print_debug argument 1 */
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UINT32 arg1; /* print_debug argument 2 */
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UINT32 irq; /* irq we're taking */
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/* register mappings */
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drcuml_parameter regmap[16]; /* parameter to register mappings for all 16 integer registers */
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drcuml_codehandle * entry; /* entry point */
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drcuml_codehandle * read8; /* read byte */
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drcuml_codehandle * write8; /* write byte */
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drcuml_codehandle * read16; /* read half */
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drcuml_codehandle * write16; /* write half */
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drcuml_codehandle * read32; /* read word */
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drcuml_codehandle * write32; /* write word */
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drcuml_codehandle * interrupt; /* interrupt */
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drcuml_codehandle * nocode; /* nocode */
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drcuml_codehandle * out_of_cycles; /* out of cycles exception handler */
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#endif
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} sh2_state;
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void sh2_common_init(sh2_state *sh2, legacy_cpu_device *device, device_irq_callback irqcallback);
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void sh2_recalc_irq(sh2_state *sh2);
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void sh2_set_irq_line(sh2_state *sh2, int irqline, int state);
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void sh2_exception(sh2_state *sh2, const char *message, int irqline);
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#endif /* __SH2COMN_H__ */
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