mirror of
https://github.com/holub/mame
synced 2025-05-24 06:30:04 +03:00
0dc663e2e9
to 8-bit handlers to match the others. To ease pain, added DECLARE_READ/WRITE_HANDLER macros that set up a default parameter. Also updated devcb so that the handlers can be called with or without the mem_mask. [Aaron Giles]
180 lines
4.6 KiB
C++
180 lines
4.6 KiB
C++
/*****************************************************************************
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*
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* includes/dgn_beta.h
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*
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****************************************************************************/
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#ifndef DGN_BETA_H_
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#define DGN_BETA_H_
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#include "video/mc6845.h"
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#include "machine/wd17xx.h"
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#include "machine/6821pia.h"
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/* Tags */
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#define MAINCPU_TAG "maincpu"
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#define DMACPU_TAG "dmacpu"
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#define PIA_0_TAG "pia_0"
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#define PIA_1_TAG "pia_1"
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#define PIA_2_TAG "pia_2"
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#define FDC_TAG "wd2797"
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#define DGNBETA_CPU_SPEED_HZ 2000000 /* 2MHz */
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#define DGNBETA_FRAMES_PER_SECOND 50
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#define RamSize 256 /* 256K by default */
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#define RamPageSize 4096 /* ram pages are 4096 bytes */
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#define MaxTasks 16 /* Tasks 0..15 */
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#define MaxPage 16 /* 16 4K pages */
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#define NoPagingTask MaxTasks /* Task registers to use when paging disabled 16 */
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#define RAMPage 0 /* Page with RAM in at power on */
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#define VideoPage 6 /* Page where video ram mapped */
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#define IOPage MaxPage-1 /* Page for I/O */
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#define ROMPage MaxPage-2 /* Page for ROM */
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#define LastPage MaxPage-1
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#define RAMPageValue 0x00 /* page with RAM at power on */
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#define VideoPageValue 0x1F /* Default page for video ram */
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#define NoMemPageValue 0xC0 /* Page guaranteed not to have memory in */
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#define ROMPageValue 0xFE /* Page with boot ROM */
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#define IOPageValue 0xFF /* Page with I/O & Boot ROM */
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#define TextVidBasePage 0x18 /* Base page of text video ram */
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/***** Keyboard stuff *****/
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#define NoKeyrows 0x0a /* Number of rows in keyboard */
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/* From Dragon Beta OS9 keyboard driver */
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#define KAny 0x04 /* Any key pressed mask PB2 */
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#define KOutClk 0x08 /* Ouput shift register clock */
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#define KInClk 0x10 /* Input shift register clock */
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#define KOutDat KInClk /* Also used for data into output shifter */
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#define KInDat 0x20 /* Keyboard data in from keyboard (serial stream) */
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/***** WD2797 pins *****/
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#define DSMask 0x03 /* PA0 & PA1 are binary encoded drive */
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#define ENPCtrl 0x20 /* PA5 on PIA */
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#define DDenCtrl 0x40 /* PA6 on PIA */
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/***** Video Modes *****/
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enum BETA_VID_MODES
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{
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TEXT_40x25, /* Text mode 40x25 */
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TEXT_80x25, /* Text mode 80x25 */
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GRAPH_320x256x4, /* Graphics 320x256x4 */
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GRAPH_320x256x16, /* Graphics 320x256x16 */
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GRAPH_640x512x2 /* Graphics 640X512X2 */
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};
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#define iosize (0xfEFF-0xfc00)
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struct PageReg
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{
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int value; /* Value of the page register */
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UINT8 *memory; /* The memory it actually points to */
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};
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class dgn_beta_state : public driver_device
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{
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public:
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dgn_beta_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_mc6845(*this, "crtc"),
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m_videoram(*this, "videoram"){ }
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required_device<mc6845_device> m_mc6845;
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required_shared_ptr<UINT8> m_videoram;
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UINT8 *m_system_rom;
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int m_LogDatWrites;
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int m_Keyboard[NoKeyrows];
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int m_RowShifter;
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int m_Keyrow;
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int m_d_pia0_pb_last;
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int m_d_pia0_cb2_last;
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int m_KInDat_next;
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int m_KAny_next;
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int m_d_pia1_pa_last;
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int m_d_pia1_pb_last;
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int m_DMA_NMI_LAST;
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int m_wd2797_written;
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int m_TaskReg;
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int m_PIATaskReg;
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int m_EnableMapRegs;
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PageReg m_PageRegs[MaxTasks+1][MaxPage+1];
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int m_beta_6845_RA;
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int m_beta_scr_x;
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int m_beta_scr_y;
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int m_beta_HSync;
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int m_beta_VSync;
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int m_beta_DE;
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int m_LogRegWrites;
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int m_BoxColour;
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int m_BoxMinX;
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int m_BoxMinY;
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int m_BoxMaxX;
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int m_BoxMaxY;
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int m_HSyncMin;
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int m_VSyncMin;
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int m_DEPos;
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int m_NoScreen;
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bitmap_ind16 *m_bit;
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int m_MinAddr;
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int m_MaxAddr;
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int m_MinX;
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int m_MaxX;
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int m_MinY;
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int m_MaxY;
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int m_VidAddr;
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int m_ClkMax;
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int m_GCtrl;
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int m_FlashCount;
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int m_FlashBit;
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int m_s_DoubleY;
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int m_DoubleHL;
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int m_ColourRAM[4];
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int m_Field;
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int m_DrawInterlace;
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virtual void machine_start();
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virtual void palette_init();
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};
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/*----------- defined in machine/dgn_beta.c -----------*/
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extern const wd17xx_interface dgnbeta_wd17xx_interface;
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extern const pia6821_interface dgnbeta_pia_intf[];
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// Page IO at FE00
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DECLARE_READ8_HANDLER( dgn_beta_page_r );
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DECLARE_WRITE8_HANDLER( dgn_beta_page_w );
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/* WD2797 FDC */
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DECLARE_READ8_HANDLER(dgnbeta_wd2797_r);
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DECLARE_WRITE8_HANDLER(dgnbeta_wd2797_w);
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void dgn_beta_frame_interrupt (running_machine &machine, int data);
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/*----------- defined in video/dgn_beta.c -----------*/
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/* mc6845 video display generator */
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void dgnbeta_vid_set_gctrl(running_machine &machine, int data);
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/* 74HC670 4x4bit colour ram */
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DECLARE_WRITE8_HANDLER(dgnbeta_colour_ram_w);
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extern const mc6845_interface dgnbeta_crtc6845_interface;
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#endif /* DGN_BETA_H_ */
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