mirror of
https://github.com/holub/mame
synced 2025-10-05 00:38:58 +03:00
6b96f7ba60
This fixes an over simplification. Logic devices implicitly assumed that GND/VDD actually is connected to GND(i.e. 0V). There is no immediate benefit from this change. It is a preparation for the future scalability. Now all power terminals (typically 7/14, 8/16) have to be explicitly connected to the supply rails. Also added a validation mode to the netlist core. This is not intended for running, but solely to better indentify pins which are not properly connected.
54 lines
2.0 KiB
C
54 lines
2.0 KiB
C
// license:BSD-3-Clause
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// copyright-holders:Ryan Holtz
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/*
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* nld_74166.h
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*
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* 74166: Parallel-Load 8-Bit Shift Register
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*
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* +--------------+
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* SER |1 ++ 16| VCC
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* A |2 15| SH/LDQ
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* B |3 14| H
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* C |4 74166 13| QH
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* D |5 12| G
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* CLKINH |6 11| F
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* CLK |7 10| E
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* GND |8 9| CLRQ
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* +--------------+
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*
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* SH/LDQ: Shift / !Load
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* CLKINH: Clock Inhibit
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* SER: Serial In
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*
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* Naming convention attempts to follow Texas Instruments datasheet
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*
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*/
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#ifndef NLD_74166_H_
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#define NLD_74166_H_
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#include "netlist/nl_setup.h"
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#define TTL_74166(name, cCLK, cCLKINH, cSH_LDQ, cSER, cA, cB, cC, cD, cE, cF, cG, cH, cCLRQ) \
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NET_REGISTER_DEV(TTL_74166, name) \
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NET_CONNECT(name, GND, GND) \
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NET_CONNECT(name, VCC, VCC) \
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NET_CONNECT(name, CLK, cCLK) \
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NET_CONNECT(name, CLKINH, cCLKINH) \
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NET_CONNECT(name, SH_LDQ, cSH_LDQ) \
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NET_CONNECT(name, SER, cSER) \
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NET_CONNECT(name, A, cA) \
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NET_CONNECT(name, B, cB) \
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NET_CONNECT(name, C, cC) \
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NET_CONNECT(name, D, cD) \
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NET_CONNECT(name, E, cE) \
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NET_CONNECT(name, F, cF) \
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NET_CONNECT(name, G, cG) \
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NET_CONNECT(name, H, cH) \
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NET_CONNECT(name, CLRQ, cCLRQ)
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#define TTL_74166_DIP(name) \
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NET_REGISTER_DEV(TTL_74166_DIP, name)
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#endif /* NLD_74166_H_ */
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