mirror of
https://github.com/holub/mame
synced 2025-10-04 16:34:53 +03:00

This fixes an over simplification. Logic devices implicitly assumed that GND/VDD actually is connected to GND(i.e. 0V). There is no immediate benefit from this change. It is a preparation for the future scalability. Now all power terminals (typically 7/14, 8/16) have to be explicitly connected to the supply rails. Also added a validation mode to the netlist core. This is not intended for running, but solely to better indentify pins which are not properly connected.
89 lines
1.9 KiB
C++
89 lines
1.9 KiB
C++
// license:BSD-3-Clause
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// copyright-holders:Ryan Holtz
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/*
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* nld_74365.cpp
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*
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*/
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#include "nld_74365.h"
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#include "netlist/nl_base.h"
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#include "nlid_system.h"
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namespace netlist
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{
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namespace devices
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{
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/* FIXME: This should be a single device, i.e. one tristate buffer only.
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*
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* FIXME: Implement tristate output.
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*
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*/
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NETLIB_OBJECT(74365)
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{
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NETLIB_CONSTRUCTOR(74365)
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, m_G1Q(*this, "G1Q")
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, m_G2Q(*this, "G2Q")
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, m_A(*this, {{ "A1", "A2", "A3", "A4", "A5", "A6" }})
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, m_Y(*this, {{ "Y1", "Y2", "Y3", "Y4", "Y5", "Y6" }})
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, m_power_pins(*this)
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{
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}
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NETLIB_UPDATEI();
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protected:
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logic_input_t m_G1Q;
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logic_input_t m_G2Q;
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object_array_t<logic_input_t, 6> m_A;
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object_array_t<logic_output_t, 6> m_Y;
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nld_power_pins m_power_pins;
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};
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NETLIB_OBJECT_DERIVED(74365_dip, 74365)
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{
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NETLIB_CONSTRUCTOR_DERIVED(74365_dip, 74365)
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{
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register_subalias("1", m_G1Q);
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register_subalias("2", m_A[0]);
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register_subalias("3", m_Y[0]);
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register_subalias("4", m_A[1]);
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register_subalias("5", m_Y[1]);
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register_subalias("6", m_A[2]);
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register_subalias("7", m_Y[2]);
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register_subalias("8", "GND");
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register_subalias("9", m_A[3]);
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register_subalias("10", m_Y[3]);
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register_subalias("11", m_A[4]);
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register_subalias("12", m_Y[4]);
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register_subalias("13", m_A[5]);
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register_subalias("14", m_Y[5]);
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register_subalias("15", m_G2Q);
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register_subalias("16", "VCC");
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}
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};
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NETLIB_UPDATE(74365)
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{
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if (!m_G1Q() && !m_G2Q())
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{
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for (std::size_t i=0; i<6; i++)
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m_Y[i].push(m_A[i](), NLTIME_FROM_NS(20)); // FIXME: Correct timing
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}
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else
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{
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for (std::size_t i=0; i<6; i++)
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m_Y[i].push(0, NLTIME_FROM_NS(20)); // FIXME: Correct timing
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}
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}
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NETLIB_DEVICE_IMPL(74365, "TTL_74365", "+G1Q,+G2Q,+A1,+A2,+A3,+A4,+A5,+A6,@VCC,@GND")
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NETLIB_DEVICE_IMPL(74365_dip, "TTL_74365_DIP", "")
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} //namespace devices
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} // namespace netlist
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