Roberto Fresca 86b987a9a9 Improvements to CEI 906 III system. [Roberto Fresca] ... * Corrected docs about the 906III memory map. * Mapped the AY8912. * Added AY8912 proper interfase. Tied SW2 to AY8912 port. * PIA0, portA is polled constantly. Tied some debug handlers to understand how the input system works. * Added notes about the PIAs R/W.		2010-08-20 12:57:45 +00:00
docs	Changed behavior of -watchdog option to act like a real watchdog. It now	2009-12-24 02:52:17 +00:00
src	Improvements to CEI 906 III system. [Roberto Fresca]	2010-08-20 12:57:45 +00:00
.gitattributes	Massive memory system change. This is another step along the path toward	2010-08-19 06:57:51 +00:00
makefile	Created CPU-specific device types for all CPUs, using new macros	2010-07-03 00:12:44 +00:00