93 lines
2.4 KiB
C++
93 lines
2.4 KiB
C++
#ifndef DM7000_H_
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#define DM7000_H_
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#include "emu.h"
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#include "cpu/powerpc/ppc.h"
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#include "machine/terminal.h"
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#define TERMINAL_TAG "terminal"
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class dm7000_state : public driver_device
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{
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public:
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dm7000_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_terminal(*this, TERMINAL_TAG)
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{
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}
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required_device<ppc4xx_device> m_maincpu;
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required_device<generic_terminal_device> m_terminal;
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DECLARE_WRITE8_MEMBER ( dm7000_iic0_w );
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DECLARE_READ8_MEMBER ( dm7000_iic0_r );
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DECLARE_WRITE8_MEMBER ( dm7000_iic1_w );
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DECLARE_READ8_MEMBER ( dm7000_iic1_r );
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DECLARE_WRITE8_MEMBER ( dm7000_scc0_w );
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DECLARE_READ8_MEMBER ( dm7000_scc0_r );
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DECLARE_WRITE8_MEMBER(kbd_put);
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UINT8 m_scc0_lcr;
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UINT8 m_scc0_lsr;
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UINT8 m_term_data;
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DECLARE_WRITE8_MEMBER ( dm7000_gpio0_w );
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DECLARE_READ8_MEMBER ( dm7000_gpio0_r );
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DECLARE_WRITE8_MEMBER ( dm7000_scp0_w );
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DECLARE_READ8_MEMBER ( dm7000_scp0_r );
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DECLARE_WRITE16_MEMBER ( dm7000_enet_w );
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DECLARE_READ16_MEMBER ( dm7000_enet_r );
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DECLARE_READ32_MEMBER( dcr_r );
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DECLARE_WRITE32_MEMBER( dcr_w );
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UINT16 m_enet_regs[32];
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UINT32 dcr[1024];
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virtual void machine_reset();
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virtual void video_start();
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UINT32 screen_update_dm7000(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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};
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/* */
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#define UART_DLL 0
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#define UART_RBR 0
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#define UART_THR 0
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#define UART_DLH 1
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#define UART_IER 1
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#define UART_IIR 2
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#define UART_FCR 2
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#define UART_LCR 3
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#define UART_LCR_DLAB 0x80
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#define UART_MCR 4
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#define UART_LSR 5
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#define UART_LSR_TEMT 0x20
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#define UART_LSR_THRE 0x40
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#define UART_MSR 6
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#define UART_SCR 7
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/* */
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#define SCP_SPMODE 0
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#define SCP_RXDATA 1
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#define SCP_TXDATA 2
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#define SCP_SPCOM 3
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#define SCP_STATUS 4
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#define SCP_STATUS_RXRDY 1
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#define SCP_CDM 6
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/* STB045xxx DCRs */
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#define DCRSTB045_CICVCR 0x033 /* CIC Video Control Register */
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#define DCRSTB045_SCCR 0x120 /* Serial Clock Control Register */
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#define DCRSTB045_VIDEO_CNTL 0x140 /* Video Control Register */
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#define DCRSTB045_CMD_STAT 0x14a /* Command status */
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#define DCRSTB045_DISP_MODE 0x154 /* Display Mode Register */
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#define DCRSTB045_FRAME_BUFR_BASE 0x179 /* Frame Buffers Base Address Register */
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#endif /* DM7000_H_ */
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