mirror of
https://github.com/holub/mame
synced 2025-05-29 09:03:08 +03:00
368 lines
7.2 KiB
C++
368 lines
7.2 KiB
C++
// license:BSD-3-Clause
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// copyright-holders:Curt Coder
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/**********************************************************************
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MOS Technology 8722 Memory Management Unit emulation
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**********************************************************************/
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#include "emu.h"
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#include "mos8722.h"
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//#define VERBOSE 1
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#include "logmacro.h"
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//**************************************************************************
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// DEVICE DEFINITIONS
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//**************************************************************************
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DEFINE_DEVICE_TYPE(MOS8722, mos8722_device, "mos8722", "MOS 8722 MMU")
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//**************************************************************************
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// MACROS / CONSTANTS
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//**************************************************************************
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#define CR_IO BIT(m_reg[CR], 0)
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#define CR_ROM_LO BIT(m_reg[CR], 1)
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#define CR_ROM_MID ((m_reg[CR] >> 2) & 0x03)
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#define CR_ROM_HI ((m_reg[CR] >> 4) & 0x03)
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#define CR_A16 BIT(m_reg[CR], 6)
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// mode configuration register
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#define MCR_8500 BIT(m_reg[MCR], 0)
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#define MCR_FSDIR BIT(m_reg[MCR], 3)
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#define MCR_GAME BIT(m_reg[MCR], 4)
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#define MCR_EXROM BIT(m_reg[MCR], 5)
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#define MCR_C64 BIT(m_reg[MCR], 6)
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#define MCR_40_80 BIT(m_reg[MCR], 7)
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// RAM configuration register
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static const offs_t RCR_BOTTOM_ADDRESS[4] = { 0x0400, 0x1000, 0x0400, 0x1000 };
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static const offs_t RCR_TOP_ADDRESS[4] = { 0xf000, 0xf000, 0xe000, 0xc000 };
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#define RCR_SHARE (m_reg[RCR] & 0x03)
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#define RCR_BOTTOM BIT(m_reg[RCR], 2)
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#define RCR_TOP BIT(m_reg[RCR], 3)
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#define RCR_VA16 BIT(m_reg[RCR], 6)
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// page 0 pointer register
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#define P0H_A16 BIT(m_reg[P0H], 0)
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// page 1 pointer register
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#define P1H_A16 BIT(m_reg[P1H], 0)
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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//-------------------------------------------------
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// mos8722_device - constructor
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//-------------------------------------------------
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mos8722_device::mos8722_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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device_t(mconfig, MOS8722, tag, owner, clock),
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m_write_z80en(*this),
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m_write_fsdir(*this),
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m_read_game(*this),
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m_read_exrom(*this),
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m_read_sense40(*this)
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{
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void mos8722_device::device_start()
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{
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// resolve callbacks
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m_write_z80en.resolve_safe();
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m_write_fsdir.resolve_safe();
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m_read_game.resolve_safe(1);
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m_read_exrom.resolve_safe(1);
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m_read_sense40.resolve_safe(1);
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void mos8722_device::device_reset()
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{
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for (auto & elem : m_reg)
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{
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elem = 0;
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}
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m_reg[P1L] = 0x01;
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m_p0h_latch = 0;
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m_p1h_latch = 0;
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m_write_z80en(MCR_8500);
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m_write_fsdir(MCR_FSDIR);
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}
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//-------------------------------------------------
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// read - register read
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//-------------------------------------------------
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uint8_t mos8722_device::read(offs_t offset, uint8_t data)
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{
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if (MCR_C64) return data;
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if (!CR_IO && offset >= 0xd500 && offset < 0xd50c)
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{
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switch (offset & 0x0f)
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{
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case CR:
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data = m_reg[CR] | 0x80;
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break;
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case MCR:
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data = m_reg[MCR] | 0x06;
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data &= ((m_read_game() << 4) | ~0x10);
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data &= ((m_read_exrom() << 5) | ~0x20);
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data &= ((m_read_sense40() << 7) | ~0x80);
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break;
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case VR:
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data = 0x20;
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break;
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default:
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data = m_reg[offset & 0x0f];
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break;
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}
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}
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else if (offset >= 0xff00 && offset < 0xff05)
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{
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switch (offset & 0x0f)
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{
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case CR:
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data = m_reg[CR] | 0x80;
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break;
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default:
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data = m_reg[offset & 0x0f];
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break;
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}
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}
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return data;
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}
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//-------------------------------------------------
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// write - register write
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//-------------------------------------------------
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void mos8722_device::write(offs_t offset, uint8_t data)
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{
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if (MCR_C64) return;
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if (!CR_IO && offset >= 0xd500 && offset < 0xd50c)
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{
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LOG("MOS8722 Write %01x : %02x\n", offset & 0x0f, data);
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switch (offset & 0x0f)
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{
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case CR:
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m_reg[CR] = data & 0x7f;
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break;
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case PCRA:
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case PCRB:
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case PCRC:
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case PCRD:
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m_reg[offset & 0x0f] = data & 0x7f;
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break;
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case MCR:
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{
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int _8500 = MCR_8500;
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int fsdir = MCR_FSDIR;
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m_reg[MCR] = data;
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if (_8500 != MCR_8500) m_write_z80en(MCR_8500);
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if (fsdir != MCR_FSDIR) m_write_fsdir(MCR_FSDIR);
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break;
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}
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case RCR:
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m_reg[RCR] = data & 0x4f;
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break;
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case P0L:
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m_reg[P0L] = data;
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m_reg[P0H] = m_p0h_latch;
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break;
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case P0H:
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m_p0h_latch = data & 0x01;
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break;
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case P1L:
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m_reg[P1L] = data;
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m_reg[P1H] = m_p1h_latch;
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break;
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case P1H:
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m_p1h_latch = data & 0x01;
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break;
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default:
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m_reg[offset & 0x0f] = data;
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}
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}
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else if (offset >= 0xff00 && offset < 0xff05)
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{
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LOG("MOS8722 Write %01x : %02x\n", offset & 0x0f, data);
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switch (offset & 0x0f)
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{
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case CR:
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m_reg[CR] = data & 0x7f;
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break;
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default:
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m_reg[CR] = m_reg[offset & 0x0f];
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break;
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}
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}
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}
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//-------------------------------------------------
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// fsdir_r - fast serial direction read
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//-------------------------------------------------
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READ_LINE_MEMBER( mos8722_device::fsdir_r )
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{
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return MCR_FSDIR;
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}
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//-------------------------------------------------
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// ta_r - translated address read
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//-------------------------------------------------
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offs_t mos8722_device::ta_r(offs_t offset, int aec, int *ms0, int *ms1, int *ms2, int *ms3, int *cas0, int *cas1)
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{
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offs_t ta;
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*ms0 = 1;
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*ms1 = 1;
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*ms2 = CR_IO;
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*ms3 = !MCR_C64;
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if (aec)
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{
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// CPU access
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ta = offset & 0xff00;
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*cas0 = CR_A16;
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*cas1 = !*cas0;
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if (!MCR_C64)
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{
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if (offset >= 0xff00 && offset < 0xff05)
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{
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// MMU registers
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*cas0 = 1;
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*cas1 = 1;
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}
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else if (!MCR_8500 && !CR_A16 && offset < 0x1000)
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{
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// Z80 ROM
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ta = 0xd000 | (offset & 0xf00);
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*ms0 = 0;
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*ms1 = 0;
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}
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else
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{
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if (offset < 0x0100)
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{
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// page 0 pointer
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ta = m_reg[P0L] << 8;
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*cas0 = P0H_A16;
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*cas1 = !*cas0;
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}
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else if (offset < 0x0200)
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{
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// page 1 pointer
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ta = m_reg[P1L] << 8;
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*cas0 = P1H_A16;
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*cas1 = !*cas0;
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}
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else if (offset >= 0x4000 && offset < 0x8000)
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{
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// low ROM
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*ms0 = CR_ROM_LO;
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*ms1 = CR_ROM_LO;
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}
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else if (offset >= 0x8000 && offset < 0xc000)
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{
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// middle ROM
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*ms0 = BIT(CR_ROM_MID, 1);
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*ms1 = BIT(CR_ROM_MID, 0);
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}
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else if (offset >= 0xc000)
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{
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// high ROM
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*ms0 = BIT(CR_ROM_HI, 1);
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*ms1 = BIT(CR_ROM_HI, 0);
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}
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if (*ms0 && *ms1)
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{
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if ((offset >> 8) == m_reg[P0L])
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{
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ta = 0x0000;
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}
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else if ((offset >> 8) == m_reg[P1L])
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{
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ta = 0x0100;
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}
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}
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if ((RCR_BOTTOM && offset < RCR_BOTTOM_ADDRESS[RCR_SHARE]) ||
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(RCR_TOP && offset >= RCR_TOP_ADDRESS[RCR_SHARE]))
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{
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// RAM sharing
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*cas0 = 0;
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*cas1 = !*cas0;
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}
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}
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}
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}
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else
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{
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// VIC access
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ta = 0xf000 | (offset & 0xf00);
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*cas0 = RCR_VA16;
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*cas1 = !*cas0;
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}
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return ta;
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}
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