Tolik-Trek/Shared_Includes
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Anatoliy Belyanskiy 2023-12-30 02:49:19 +10:00
parent 86315fd7a0
commit 54298bfb52
1 changed files with 21 additions and 21 deletions
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42
constants/SP2000.inc
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@ -2022,41 +2022,41 @@ STC3_C EQU #13
;-------------------[Ports] ;-------------------[Ports]
; Counter Timer Control ; Counter Timer Control
CTC: CTC:
.Ch_0 EQU #10 ; Control Register .Ch_0 EQU #10 ; Control Register
.Ch_1 EQU #11 ; Control Register .Ch_1 EQU #11 ; Control Register
.Ch_2 EQU #12 ; Control Register .Ch_2 EQU #12 ; Control Register
.Ch_3 EQU #13 ; Control Register .Ch_3 EQU #13 ; Control Register
; Serial I/O ; Serial I/O
SIO: SIO:
.Ch_A.Data EQU #18 ; Data register COM .Ch_A.Data EQU #18 ; Data register keyboard DAT_A
.Ch_A.Ctrl EQU #19 ; Control register COM .Ch_A.Ctrl EQU #19 ; Control register keyboard COM_A
.Ch_B.Data EQU #1A ; Data register keyboard & mouse .Ch_B.Data EQU #1A ; Data register mouse DMOUSE
.Ch_B.Ctrl EQU #1B ; Control register keyboard & mouse .Ch_B.Ctrl EQU #1B ; Control register mouse CMOUSE
; Parallel I/O ; Parallel I/O
PIO: PIO:
.Port_A.Data EQU #1C ; Data register LPT 1 .Port_A.Data EQU #1C ; Data register LPT 1
.Port_A.Command EQU #1D ; Command register LPT 1 .Port_A.Command EQU #1D ; Command register LPT 1
.Port_B.Data EQU #1E ; Data register LPT 2 .Port_B.Data EQU #1E ; Data register LPT 2
;⮫쪮 ç¥à¥§ ॣ¨áâà BC, ¨­ ç¥ €«ìâ¥à  ¯¥à¥å¢ â¨â ;⮫쪮 ç¥à¥§ ॣ¨áâà BC, ¨­ ç¥ €«ìâ¥à  ¯¥à¥å¢ â¨â
.Port_B.Command EQU #1F ; Command register LPT 2 .Port_B.Command EQU #1F ; Command register LPT 2
; Watch Dog timer ; Watch Dog timer
WDT: WDT:
.Master_Reg EQU #F0 ; Master register WDTMR .Master_Reg EQU #F0 ; Master register WDTMR
.Control_Reg EQU #F1 ; Control register WDTCR .Control_Reg EQU #F1 ; Control register WDTCR
; Interrupt Priority Register ; Interrupt Priority Register
IntPrior_Reg EQU #F4 IntPrior_Reg EQU #F4
;System Control ;System Control
SYS: SYS:
.Control EQU #EE ; System Control Register Pointer SCRP .Control EQU #EE ; System Control Register Pointer SCRP
.Data EQU #EF ; System Control Data Port SCDP .Data EQU #EF ; System Control Data Port SCDP
;------------------------[] ;------------------------[]
;-------------------[Regs ] ;-------------------[Regs ]
REG: REG:
.WaitState_Ctrl EQU 00 ; Wait state control register WCR .WaitState_Ctrl EQU 00 ; Wait state control register WCR
.WaitState_MemBound EQU 01 ; Memory Wait state Boundary Register MWBR .WaitState_MemBound EQU 01 ; Memory Wait state Boundary Register MWBR
.CS_Boundary EQU 02 ; Chip Select Boundary Register CSBR .CS_Boundary EQU 02 ; Chip Select Boundary Register CSBR
.Misc_Ctrl EQU 03 ; Misc.Control Register MCR .Misc_Ctrl EQU 03 ; Misc.Control Register MCR
;------------------------[] ;------------------------[]
ENDMODULE ENDMODULE
; ;