589 lines
15 KiB
Plaintext
589 lines
15 KiB
Plaintext
--
|
|
-- Copyright (C) 1988-2000 Altera Corporation
|
|
-- Any megafunction design, and related net list (encrypted or decrypted),
|
|
-- support information, device programming or simulation file, and any other
|
|
-- associated documentation or information provided by Altera or a partner
|
|
-- under Altera's Megafunction Partnership Program may be used only to
|
|
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
|
-- use of such megafunction design, net list, support information, device
|
|
-- programming or simulation file, or any other related documentation or
|
|
-- information is prohibited for any other purpose, including, but not
|
|
-- limited to modification, reverse engineering, de-compiling, or use with
|
|
-- any other silicon devices, unless such use is explicitly licensed under
|
|
-- a separate agreement with Altera or a megafunction partner. Title to
|
|
-- the intellectual property, including patents, copyrights, trademarks,
|
|
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
|
-- net list, support information, device programming or simulation file, or
|
|
-- any other related documentation or information provided by Altera or a
|
|
-- megafunction partner, remains with Altera, the megafunction partner, or
|
|
-- their respective licensors. No other licenses, including any licenses
|
|
-- needed under any third party's intellectual property, are provided herein.
|
|
--
|
|
CHIP video2
|
|
BEGIN
|
|
DEVICE = AUTO;
|
|
END;
|
|
|
|
DEFAULT_DEVICES
|
|
BEGIN
|
|
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
|
|
AUTO_DEVICE = EP1K30TC144-1;
|
|
AUTO_DEVICE = EP1K30QC208-1;
|
|
AUTO_DEVICE = EP1K30FC256-1;
|
|
AUTO_DEVICE = EP1K50TC144-1;
|
|
AUTO_DEVICE = EP1K50QC208-1;
|
|
AUTO_DEVICE = EP1K50FC256-1;
|
|
AUTO_DEVICE = EP1K50FC484-1;
|
|
AUTO_DEVICE = EP1K100QC208-1;
|
|
AUTO_DEVICE = EP1K100FC256-1;
|
|
AUTO_DEVICE = EP1K100FC484-1;
|
|
END;
|
|
|
|
TIMING_POINT
|
|
BEGIN
|
|
MAINTAIN_STABLE_SYNTHESIS = ON;
|
|
DEVICE_FOR_TIMING_SYNTHESIS = EP1K30FC256-3;
|
|
CUT_ALL_BIDIR = ON;
|
|
CUT_ALL_CLEAR_PRESET = ON;
|
|
FREQUENCY = 200MHz;
|
|
END;
|
|
|
|
IGNORED_ASSIGNMENTS
|
|
BEGIN
|
|
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
|
|
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
|
|
IGNORE_TIMING_ASSIGNMENTS = OFF;
|
|
IGNORE_CHIP_ASSIGNMENTS = OFF;
|
|
IGNORE_PIN_ASSIGNMENTS = OFF;
|
|
IGNORE_LC_ASSIGNMENTS = OFF;
|
|
IGNORE_DEVICE_ASSIGNMENTS = OFF;
|
|
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
|
|
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
|
|
FIT_IGNORE_TIMING = OFF;
|
|
END;
|
|
|
|
LOGIC_OPTIONS
|
|
BEGIN
|
|
|VAO15 : FAST_IO = ON;
|
|
|VAO14 : FAST_IO = ON;
|
|
|VAO13 : FAST_IO = ON;
|
|
|VAO12 : FAST_IO = ON;
|
|
|VAO11 : FAST_IO = ON;
|
|
|VAO10 : FAST_IO = ON;
|
|
|VAO9 : FAST_IO = ON;
|
|
|VAO8 : FAST_IO = ON;
|
|
|VAO7 : FAST_IO = ON;
|
|
|VAO6 : FAST_IO = ON;
|
|
|VAO5 : FAST_IO = ON;
|
|
|VAO4 : FAST_IO = ON;
|
|
|VAO3 : FAST_IO = ON;
|
|
|VAO2 : FAST_IO = ON;
|
|
|VAO1 : FAST_IO = ON;
|
|
|VAO0 : FAST_IO = ON;
|
|
END;
|
|
|
|
GLOBAL_PROJECT_DEVICE_OPTIONS
|
|
BEGIN
|
|
RESERVED_LCELLS_PERCENT = 0;
|
|
RESERVED_PINS_PERCENT = 0;
|
|
SECURITY_BIT = OFF;
|
|
USER_CLOCK = OFF;
|
|
AUTO_RESTART = OFF;
|
|
RELEASE_CLEARS = OFF;
|
|
ENABLE_DCLK_OUTPUT = OFF;
|
|
DISABLE_TIME_OUT = OFF;
|
|
CONFIG_SCHEME = ACTIVE_SERIAL;
|
|
FLEX8000_ENABLE_JTAG = OFF;
|
|
DATA0 = RESERVED_TRI_STATED;
|
|
DATA1_TO_DATA7 = UNRESERVED;
|
|
nWS_nRS_nCS_CS = UNRESERVED;
|
|
RDYnBUSY = UNRESERVED;
|
|
RDCLK = UNRESERVED;
|
|
SDOUT = RESERVED_DRIVES_OUT;
|
|
ADD0_TO_ADD12 = UNRESERVED;
|
|
ADD13 = UNRESERVED;
|
|
ADD14 = UNRESERVED;
|
|
ADD15 = UNRESERVED;
|
|
ADD16 = UNRESERVED;
|
|
ADD17 = UNRESERVED;
|
|
CLKUSR = UNRESERVED;
|
|
nCEO = UNRESERVED;
|
|
ENABLE_CHIP_WIDE_RESET = OFF;
|
|
ENABLE_CHIP_WIDE_OE = OFF;
|
|
ENABLE_INIT_DONE_OUTPUT = OFF;
|
|
FLEX10K_JTAG_USER_CODE = 7F;
|
|
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
|
|
MAX7000S_USER_CODE = FFFF;
|
|
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
|
|
MAX7000S_ENABLE_JTAG = ON;
|
|
MULTIVOLT_IO = OFF;
|
|
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
|
|
FLEX6000_ENABLE_JTAG = OFF;
|
|
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
|
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
|
|
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
|
MAX7000AE_USER_CODE = FFFFFFFF;
|
|
MAX7000AE_ENABLE_JTAG = ON;
|
|
FLEX_CONFIGURATION_EPROM = AUTO;
|
|
CONFIG_EPROM_USER_CODE = FFFFFFFF;
|
|
CONFIG_EPROM_PULLUP_RESISTOR = ON;
|
|
MAX7000B_VCCIO_IOBANK1 = 3.3V;
|
|
MAX7000B_VCCIO_IOBANK2 = 3.3V;
|
|
MAX7000B_ENABLE_VREFA = OFF;
|
|
MAX7000B_ENABLE_VREFB = OFF;
|
|
END;
|
|
|
|
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
|
|
BEGIN
|
|
OPTIMIZE_FOR_SPEED = 5;
|
|
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
|
|
AUTO_GLOBAL_CLOCK = ON;
|
|
AUTO_GLOBAL_CLEAR = ON;
|
|
AUTO_GLOBAL_PRESET = ON;
|
|
AUTO_GLOBAL_OE = ON;
|
|
AUTO_FAST_IO = OFF;
|
|
DEVICE_FAMILY = ACEX1K;
|
|
AUTO_REGISTER_PACKING = OFF;
|
|
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
|
|
AUTO_OPEN_DRAIN_PINS = ON;
|
|
AUTO_IMPLEMENT_IN_EAB = OFF;
|
|
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
|
|
STYLE = FAST;
|
|
END;
|
|
|
|
COMPILER_PROCESSING_CONFIGURATION
|
|
BEGIN
|
|
USE_QUARTUS_FITTER = ON;
|
|
DESIGN_DOCTOR = OFF;
|
|
DESIGN_DOCTOR_RULES = EPLD;
|
|
FUNCTIONAL_SNF_EXTRACTOR = OFF;
|
|
TIMING_SNF_EXTRACTOR = ON;
|
|
OPTIMIZE_TIMING_SNF = OFF;
|
|
LINKED_SNF_EXTRACTOR = OFF;
|
|
RPT_FILE_EQUATIONS = ON;
|
|
RPT_FILE_HIERARCHY = ON;
|
|
RPT_FILE_LCELL_INTERCONNECT = ON;
|
|
RPT_FILE_USER_ASSIGNMENTS = ON;
|
|
GENERATE_AHDL_TDO_FILE = OFF;
|
|
SMART_RECOMPILE = OFF;
|
|
FITTER_SETTINGS = NORMAL;
|
|
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
|
|
END;
|
|
|
|
COMPILER_INTERFACES_CONFIGURATION
|
|
BEGIN
|
|
EDIF_NETLIST_WRITER = OFF;
|
|
EDIF_OUTPUT_VERSION = 200;
|
|
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
|
|
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
|
|
XNF_GENERATE_AHDL_TDX_FILE = ON;
|
|
VERILOG_NETLIST_WRITER = OFF;
|
|
VHDL_NETLIST_WRITER = OFF;
|
|
USE_SYNOPSYS_SYNTHESIS = OFF;
|
|
SYNOPSYS_COMPILER = DESIGN;
|
|
SYNOPSYS_DESIGNWARE = OFF;
|
|
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
|
|
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
|
|
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
|
|
VHDL_READER_VERSION = VHDL87;
|
|
VHDL_WRITER_VERSION = VHDL87;
|
|
VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
|
VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
|
|
VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
|
|
EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
|
|
VERILOG_FLATTEN_BUS = OFF;
|
|
VHDL_FLATTEN_BUS = OFF;
|
|
VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
|
|
VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
|
|
VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
|
|
EDIF_INPUT_LMF1 = *.lmf;
|
|
EDIF_INPUT_LMF2 = *.lmf;
|
|
EDIF_OUTPUT_EDC_FILE = *.edc;
|
|
EDIF_INPUT_VCC = VCC;
|
|
EDIF_INPUT_GND = GND;
|
|
EDIF_OUTPUT_VCC = VCC;
|
|
EDIF_OUTPUT_GND = GND;
|
|
EDIF_INPUT_USE_LMF1 = OFF;
|
|
EDIF_INPUT_USE_LMF2 = OFF;
|
|
EDIF_OUTPUT_USE_EDC = OFF;
|
|
EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
|
|
EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
|
EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
|
|
EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
|
|
EDIF_FLATTEN_BUS = OFF;
|
|
EDIF_BUS_DELIMITERS = [];
|
|
EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
|
|
NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
|
|
END;
|
|
|
|
CUSTOM_DESIGN_DOCTOR_RULES
|
|
BEGIN
|
|
RIPPLE_CLOCKS = ON;
|
|
GATED_CLOCKS = ON;
|
|
MULTI_LEVEL_CLOCKS = ON;
|
|
MULTI_CLOCK_NETWORKS = ON;
|
|
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
|
|
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
|
|
PRESET_CLEAR_NETWORKS = ON;
|
|
ASYNCHRONOUS_INPUTS = ON;
|
|
DELAY_CHAINS = ON;
|
|
RACE_CONDITIONS = ON;
|
|
EXPANDER_NETWORKS = ON;
|
|
MASTER_RESET = OFF;
|
|
END;
|
|
|
|
SIMULATOR_CONFIGURATION
|
|
BEGIN
|
|
CHECK_OUTPUTS = OFF;
|
|
USE_DEVICE = OFF;
|
|
SETUP_HOLD = OFF;
|
|
OSCILLATION = OFF;
|
|
OSCILLATION_TIME = 0.0ns;
|
|
GLITCH = OFF;
|
|
GLITCH_TIME = 0.0ns;
|
|
START_TIME = 0.0ns;
|
|
BIDIR_PIN = STRONG;
|
|
END_TIME = 10.0us;
|
|
END;
|
|
|
|
TIMING_ANALYZER_CONFIGURATION
|
|
BEGIN
|
|
ANALYSIS_MODE = REGISTERED_PERFORMANCE;
|
|
AUTO_RECALCULATE = OFF;
|
|
CUT_OFF_IO_PIN_FEEDBACK = ON;
|
|
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
|
|
LIST_ONLY_LONGEST_PATH = ON;
|
|
CELL_WIDTH = 18;
|
|
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
|
|
INCLUDE_PATHS_GREATER_THAN = OFF;
|
|
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
|
|
INCLUDE_PATHS_LESS_THAN = OFF;
|
|
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
|
|
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
|
|
LIST_PATH_COUNT = 10;
|
|
LIST_PATH_FREQUENCY = 10MHz;
|
|
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
|
|
END;
|
|
|
|
OTHER_CONFIGURATION
|
|
BEGIN
|
|
LAST_MAXPLUS2_VERSION = 10.0;
|
|
EXPLICIT_FAMILY = 1;
|
|
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
|
|
ORIGINAL_MAXPLUS2_VERSION = 9.6;
|
|
ROW_PINS_PERCENT = 50;
|
|
EXP_PER_LCELL_PERCENT = 100;
|
|
FAN_IN_PER_LCELL_PERCENT = 100;
|
|
LCELLS_PER_ROW_PERCENT = 100;
|
|
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
|
|
DEFAULT_9K_EXP_PER_LCELL = 1/2;
|
|
FLEX_10K_52_COLUMNS = 40;
|
|
NORMAL_LCELL_INSERT = ON;
|
|
CARRY_OUT_PINS_LCELL_INSERT = OFF;
|
|
ROW_PINS_LCELL_INSERT = ON;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
|
|
BEGIN
|
|
CASCADE_CHAIN = IGNORE;
|
|
CASCADE_CHAIN_LENGTH = -1;
|
|
CARRY_CHAIN = IGNORE;
|
|
CARRY_CHAIN_LENGTH = -1;
|
|
MINIMIZATION = FULL;
|
|
SLOW_SLEW_RATE = OFF;
|
|
XOR_SYNTHESIS = ON;
|
|
TURBO_BIT = OFF;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
FAST_IO = OFF;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
DECOMPOSE_GATES = ON;
|
|
REDUCE_LOGIC = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = ON;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
REFACTORIZATION = ON;
|
|
SUBFACTOR_EXTRACTION = ON;
|
|
MULTI_LEVEL_FACTORING = ON;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
REGISTER_OPTIMIZATION = ON;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
|
|
BEGIN
|
|
CASCADE_CHAIN = IGNORE;
|
|
CASCADE_CHAIN_LENGTH = -1;
|
|
CARRY_CHAIN = IGNORE;
|
|
CARRY_CHAIN_LENGTH = -1;
|
|
MINIMIZATION = FULL;
|
|
SLOW_SLEW_RATE = OFF;
|
|
XOR_SYNTHESIS = ON;
|
|
TURBO_BIT = ON;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
FAST_IO = OFF;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
DECOMPOSE_GATES = ON;
|
|
REDUCE_LOGIC = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = ON;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
REFACTORIZATION = ON;
|
|
SUBFACTOR_EXTRACTION = ON;
|
|
MULTI_LEVEL_FACTORING = ON;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
REGISTER_OPTIMIZATION = ON;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
|
|
BEGIN
|
|
CASCADE_CHAIN = IGNORE;
|
|
CASCADE_CHAIN_LENGTH = -1;
|
|
CARRY_CHAIN = IGNORE;
|
|
CARRY_CHAIN_LENGTH = -1;
|
|
MINIMIZATION = FULL;
|
|
SLOW_SLEW_RATE = OFF;
|
|
XOR_SYNTHESIS = OFF;
|
|
TURBO_BIT = ON;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
FAST_IO = OFF;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
DECOMPOSE_GATES = ON;
|
|
REDUCE_LOGIC = OFF;
|
|
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
REFACTORIZATION = OFF;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
MULTI_LEVEL_FACTORING = OFF;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
REGISTER_OPTIMIZATION = OFF;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
|
|
BEGIN
|
|
CASCADE_CHAIN = IGNORE;
|
|
CASCADE_CHAIN_LENGTH = 2;
|
|
CARRY_CHAIN = IGNORE;
|
|
CARRY_CHAIN_LENGTH = 32;
|
|
MINIMIZATION = FULL;
|
|
SLOW_SLEW_RATE = OFF;
|
|
XOR_SYNTHESIS = OFF;
|
|
TURBO_BIT = OFF;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
IGNORE_SOFT_BUFFERS = ON;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
DECOMPOSE_GATES = ON;
|
|
REDUCE_LOGIC = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = ON;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
REFACTORIZATION = ON;
|
|
SUBFACTOR_EXTRACTION = ON;
|
|
MULTI_LEVEL_FACTORING = ON;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
REGISTER_OPTIMIZATION = ON;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
|
|
BEGIN
|
|
SLOW_SLEW_RATE = OFF;
|
|
XOR_SYNTHESIS = ON;
|
|
TURBO_BIT = OFF;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
FAST_IO = OFF;
|
|
MINIMIZATION = FULL;
|
|
CASCADE_CHAIN = IGNORE;
|
|
CARRY_CHAIN = IGNORE;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
DECOMPOSE_GATES = ON;
|
|
REDUCE_LOGIC = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = ON;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
REFACTORIZATION = OFF;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
MULTI_LEVEL_FACTORING = ON;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
REGISTER_OPTIMIZATION = ON;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
|
|
BEGIN
|
|
SLOW_SLEW_RATE = OFF;
|
|
XOR_SYNTHESIS = ON;
|
|
TURBO_BIT = ON;
|
|
PARALLEL_EXPANDERS = ON;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
FAST_IO = OFF;
|
|
MINIMIZATION = FULL;
|
|
CASCADE_CHAIN = IGNORE;
|
|
CARRY_CHAIN = IGNORE;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
DECOMPOSE_GATES = ON;
|
|
REDUCE_LOGIC = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = ON;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
REFACTORIZATION = OFF;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
MULTI_LEVEL_FACTORING = ON;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
REGISTER_OPTIMIZATION = ON;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
|
|
BEGIN
|
|
SLOW_SLEW_RATE = OFF;
|
|
XOR_SYNTHESIS = OFF;
|
|
TURBO_BIT = ON;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
FAST_IO = OFF;
|
|
MINIMIZATION = FULL;
|
|
CASCADE_CHAIN = IGNORE;
|
|
CARRY_CHAIN = IGNORE;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
DECOMPOSE_GATES = ON;
|
|
REDUCE_LOGIC = OFF;
|
|
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
REFACTORIZATION = OFF;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
MULTI_LEVEL_FACTORING = OFF;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
REGISTER_OPTIMIZATION = OFF;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
|
|
BEGIN
|
|
SLOW_SLEW_RATE = OFF;
|
|
XOR_SYNTHESIS = OFF;
|
|
TURBO_BIT = OFF;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
IGNORE_SOFT_BUFFERS = ON;
|
|
MINIMIZATION = FULL;
|
|
CASCADE_CHAIN = AUTO;
|
|
CARRY_CHAIN = AUTO;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
DECOMPOSE_GATES = ON;
|
|
REDUCE_LOGIC = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = ON;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
REFACTORIZATION = ON;
|
|
SUBFACTOR_EXTRACTION = ON;
|
|
MULTI_LEVEL_FACTORING = ON;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
REGISTER_OPTIMIZATION = ON;
|
|
CASCADE_CHAIN_LENGTH = 2;
|
|
CARRY_CHAIN_LENGTH = 32;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
|
|
BEGIN
|
|
CASCADE_CHAIN = IGNORE;
|
|
CASCADE_CHAIN_LENGTH = -1;
|
|
CARRY_CHAIN = IGNORE;
|
|
CARRY_CHAIN_LENGTH = -1;
|
|
MINIMIZATION = PARTIAL;
|
|
SLOW_SLEW_RATE = OFF;
|
|
XOR_SYNTHESIS = OFF;
|
|
TURBO_BIT = OFF;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
FAST_IO = OFF;
|
|
SOFT_BUFFER_INSERTION = OFF;
|
|
DECOMPOSE_GATES = OFF;
|
|
REDUCE_LOGIC = OFF;
|
|
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
REFACTORIZATION = OFF;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
MULTI_LEVEL_FACTORING = OFF;
|
|
RESYNTHESIZE_NETWORK = OFF;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
REGISTER_OPTIMIZATION = OFF;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
|
|
BEGIN
|
|
CASCADE_CHAIN = IGNORE;
|
|
CASCADE_CHAIN_LENGTH = -1;
|
|
CARRY_CHAIN = IGNORE;
|
|
CARRY_CHAIN_LENGTH = -1;
|
|
MINIMIZATION = PARTIAL;
|
|
SLOW_SLEW_RATE = OFF;
|
|
XOR_SYNTHESIS = OFF;
|
|
TURBO_BIT = ON;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
FAST_IO = OFF;
|
|
SOFT_BUFFER_INSERTION = OFF;
|
|
DECOMPOSE_GATES = OFF;
|
|
REDUCE_LOGIC = OFF;
|
|
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
REFACTORIZATION = OFF;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
MULTI_LEVEL_FACTORING = OFF;
|
|
RESYNTHESIZE_NETWORK = OFF;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
REGISTER_OPTIMIZATION = OFF;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
|
|
BEGIN
|
|
CASCADE_CHAIN = IGNORE;
|
|
CASCADE_CHAIN_LENGTH = -1;
|
|
CARRY_CHAIN = IGNORE;
|
|
CARRY_CHAIN_LENGTH = -1;
|
|
MINIMIZATION = PARTIAL;
|
|
SLOW_SLEW_RATE = OFF;
|
|
XOR_SYNTHESIS = OFF;
|
|
TURBO_BIT = ON;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
FAST_IO = OFF;
|
|
SOFT_BUFFER_INSERTION = OFF;
|
|
DECOMPOSE_GATES = ON;
|
|
REDUCE_LOGIC = OFF;
|
|
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
REFACTORIZATION = OFF;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
MULTI_LEVEL_FACTORING = OFF;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
REGISTER_OPTIMIZATION = OFF;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
|
|
BEGIN
|
|
CASCADE_CHAIN = MANUAL;
|
|
CASCADE_CHAIN_LENGTH = 2;
|
|
CARRY_CHAIN = MANUAL;
|
|
CARRY_CHAIN_LENGTH = 32;
|
|
MINIMIZATION = PARTIAL;
|
|
SLOW_SLEW_RATE = OFF;
|
|
XOR_SYNTHESIS = OFF;
|
|
TURBO_BIT = OFF;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
IGNORE_SOFT_BUFFERS = ON;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
DECOMPOSE_GATES = OFF;
|
|
REDUCE_LOGIC = OFF;
|
|
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
REFACTORIZATION = OFF;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
MULTI_LEVEL_FACTORING = OFF;
|
|
RESYNTHESIZE_NETWORK = OFF;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
REGISTER_OPTIMIZATION = OFF;
|
|
END;
|
|
|