1472 lines
67 KiB
Plaintext
1472 lines
67 KiB
Plaintext
Project Information c:\sprinter\src\altera\max\sp2_max.rpt
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MAX+plus II Compiler Report File
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Version 10.0 9/14/2000
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Compiled: 07/02/2022 02:06:11
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Copyright (C) 1988-2000 Altera Corporation
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Any megafunction design, and related net list (encrypted or decrypted),
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support information, device programming or simulation file, and any other
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associated documentation or information provided by Altera or a partner
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under Altera's Megafunction Partnership Program may be used only to
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program PLD devices (but not masked PLD devices) from Altera. Any other
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use of such megafunction design, net list, support information, device
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programming or simulation file, or any other related documentation or
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information is prohibited for any other purpose, including, but not
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limited to modification, reverse engineering, de-compiling, or use with
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any other silicon devices, unless such use is explicitly licensed under
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a separate agreement with Altera or a megafunction partner. Title to
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the intellectual property, including patents, copyrights, trademarks,
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||
trade secrets, or maskworks, embodied in any such megafunction design,
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||
net list, support information, device programming or simulation file, or
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||
any other related documentation or information provided by Altera or a
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megafunction partner, remains with Altera, the megafunction partner, or
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their respective licensors. No other licenses, including any licenses
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needed under any third party's intellectual property, are provided herein.
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***** Project compilation was successful
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SINC_controller
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** DEVICE SUMMARY **
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Chip/ Input Output Bidir Shareable
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POF Device Pins Pins Pins LCs Expanders % Utilized
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SP2_MAX EPM7128STC100-10 29 30 4 64 40 50 %
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User Pins: 29 30 4
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Project Information c:\sprinter\src\altera\max\sp2_max.rpt
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** PROJECT COMPILATION MESSAGES **
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Warning: Line 52, File c:\sprinter\src\altera\max\sp2_max.tdf:
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Symbolic name "XA2" was declared but never used
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Warning: Line 148, File c:\sprinter\src\altera\max\sp2_max.tdf:
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Symbolic name "CTV8C" was declared but never used
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Warning: Line 88, File c:\sprinter\src\altera\max\sp2_max.tdf:
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Symbolic name "GND65" was declared but never used
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Warning: Line 52, File c:\sprinter\src\altera\max\sp2_max.tdf:
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Symbolic name "XA1" was declared but never used
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Warning: Line 83, File c:\sprinter\src\altera\max\sp2_max.tdf:
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Symbolic name "XHR_RDY" was declared but never used
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Warning: Line 52, File c:\sprinter\src\altera\max\sp2_max.tdf:
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Symbolic name "XA0" was declared but never used
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Warning: Line 143, File c:\sprinter\src\altera\max\sp2_max.tdf:
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Symbolic name "EXP_X" was declared but never used
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Warning: Line 144, File c:\sprinter\src\altera\max\sp2_max.tdf:
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Symbolic name "EXP_Y" was declared but never used
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Warning: Line 70, File c:\sprinter\src\altera\max\sp2_max.tdf:
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Symbolic name "VGA_IN" was declared but never used
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Warning: Line 75, File c:\sprinter\src\altera\max\sp2_max.tdf:
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Symbolic name "SINC_IN" was declared but never used
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Warning: Line 89, File c:\sprinter\src\altera\max\sp2_max.tdf:
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Symbolic name "GND33" was declared but never used
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Warning: Flipflop 'CTV8M' stuck at GND
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Warning: No Clock transition on flipflop 'CNF_OFF'
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Warning: Primitive 'BEEP' is stuck at GND
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Warning: Primitive 'DENS_X' is stuck at VCC
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Warning: Primitive 'HD_CS' is stuck at GND
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Warning: Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead.
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Info: Reserved unused input pin 'XA2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
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Info: Reserved unused input pin 'XA1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
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Info: Reserved unused input pin 'XA0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
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Info: Reserved unused input pin 'VGA_IN' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
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Info: Reserved unused input pin 'SINC_IN' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
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Info: Reserved unused input pin 'XHR_RDY' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
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Info: Reserved unused input pin 'GND65' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
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Info: Reserved unused input pin 'GND33' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
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** PROJECT TIMING MESSAGES **
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Warning: Found ripple clock -- warning messages and Report File information on tco, tsu, and fmax may be inaccurate
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Warning: Can't provide fmax of 100.00 MHz on Clock pin "RSTB". Current fmax is 43.47 MHz.
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Warning: Can't provide fmax of 100.00 MHz on Clock pin "STE". Current fmax is 43.47 MHz.
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Warning: Can't provide fmax of 100.00 MHz on Clock pin "TG42_IN". Current fmax is 27.02 MHz.
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Warning: Can't provide fmax of 100.00 MHz on Clock pin "WSTB". Current fmax is 43.47 MHz.
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Project Information c:\sprinter\src\altera\max\sp2_max.rpt
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** PIN/LOCATION/CHIP ASSIGNMENTS **
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Actual
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User Assignments
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Assignments (if different) Node Name
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SP2_MAX@35 AUD
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SP2_MAX@84 BEEP
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SP2_MAX@13 CLK_WG
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SP2_MAX@32 CLKZZ
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SP2_MAX@31 CLK14
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SP2_MAX@6 CMOS_AS
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SP2_MAX@99 CMOS_DRD
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SP2_MAX@100 CMOS_DWR
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SP2_MAX@54 /CONF_X
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SP2_MAX@96 DENS_X
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SP2_MAX@60 D0
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SP2_MAX@89 EPM_RES
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SP2_MAX@14 FDAT
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SP2_MAX@44 FDD_C0
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SP2_MAX@45 FDD_C1
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SP2_MAX@46 FDD_C2
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SP2_MAX@33 GND33
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SP2_MAX@65 GND65
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SP2_MAX@52 HD_CS
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SP2_MAX@47 HDD_C0
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SP2_MAX@42 HDD_C1
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SP2_MAX@41 HDD_C2
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SP2_MAX@40 HDD_C3
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SP2_MAX@48 HD_DIR
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SP2_MAX@90 PW_GOOD
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SP2_MAX@16 QDAT
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SP2_MAX@92 RDAT
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SP2_MAX@25 RSTB
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SP2_MAX@67 SINC
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SP2_MAX@68 SINC_H
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SP2_MAX@69 SINC_IN
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SP2_MAX@64 SINC_V
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SP2_MAX@20 SINC_1
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SP2_MAX@19 SINC_2
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SP2_MAX@30 SL
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SP2_MAX@29 SR
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SP2_MAX@94 STE
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SP2_MAX@36 TG42_BUF
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SP2_MAX@87 TG42_IN
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SP2_MAX@85 TG42_OUT
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SP2_MAX@12 TR43
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SP2_MAX@61 VGA_IN
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SP2_MAX@9 WD
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SP2_MAX@98 WDAT
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SP2_MAX@97 /WG_RD
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SP2_MAX@93 /WG_WR
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SP2_MAX@57 WR_CNF
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SP2_MAX@8 WR_PDOS
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SP2_MAX@10 WSTB
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SP2_MAX@37 XACS
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SP2_MAX@17 XA0
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SP2_MAX@21 XA1
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SP2_MAX@23 XA2
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SP2_MAX@76 XHD_RD
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SP2_MAX@71 XHD_RES
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SP2_MAX@75 XHD_WR
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SP2_MAX@79 XHD1_CS1
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SP2_MAX@80 XHD1_CS2
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SP2_MAX@81 XHD2_CS1
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SP2_MAX@83 XHD2_CS2
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SP2_MAX@88 XHR_RDY
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SP2_MAX@56 10K_CLK
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SP2_MAX@58 10K_D0
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Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt
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SP2_MAX
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***** Logic for device 'SP2_MAX' compiled without errors.
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Device: EPM7128STC100-10
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Device Options:
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Turbo Bit = ON
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Security Bit = ON
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Enable JTAG Support = ON
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User Code = ffff
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MultiVolt I/O = OFF
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C C T X X X X R R
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M M P E X T G H H H H E E
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O O / D / V W P H G 4 D D D D S S X
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S S W E W C _ M R 4 2 2 V 2 1 1 E E H
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_ _ W G N G R C G _ _ 2 _ B _ C _ _ _ R R D
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D D D _ S G S _ D I O R R _ G O E C C C C C V V _
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W R A R _ N T W A N O E D I N U E S I S S S E E R
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R D T D X D E R T T D S Y N D T P 2 O 1 2 1 D D D
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----------------------------------------------------_
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/ 100 98 96 94 92 90 88 86 84 82 80 78 76 |_
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/ 99 97 95 93 91 89 87 85 83 81 79 77 |
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RESERVED | 1 75 | XHD_WR
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RESERVED | 2 74 | GND
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VCCIO | 3 73 | #TDO
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#TDI | 4 72 | RESERVED
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RESERVED | 5 71 | XHD_RES
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CMOS_AS | 6 70 | RESERVED
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RESERVED | 7 69 | SINC_IN
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WR_PDOS | 8 68 | SINC_H
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WD | 9 67 | SINC
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WSTB | 10 66 | VCCIO
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GND | 11 65 | GND65
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TR43 | 12 64 | SINC_V
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CLK_WG | 13 EPM7128STC100-10 63 | RESERVED
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FDAT | 14 62 | #TCK
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#TMS | 15 61 | VGA_IN
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QDAT | 16 60 | D0
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XA0 | 17 59 | GND
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VCCIO | 18 58 | 10K_D0
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SINC_2 | 19 57 | WR_CNF
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SINC_1 | 20 56 | 10K_CLK
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XA1 | 21 55 | RESERVED
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RESERVED | 22 54 | /CONF_X
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XA2 | 23 53 | RESERVED
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RESERVED | 24 52 | HD_CS
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RSTB | 25 51 | VCCIO
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| 27 29 31 33 35 37 39 41 43 45 47 49 _|
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\ 26 28 30 32 34 36 38 40 42 44 46 48 50 |
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\-----------------------------------------------------
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G R R S S C C G V A T X G V H H H G F F F H H R R
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N E E R L L L N C U G A N C D D D N D D D D D E E
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D S S K K D C D 4 C D C D D D D D D D D _ S S
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E E 1 Z 3 I 2 S I _ _ _ _ _ _ _ D E E
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R R 4 Z 3 O _ N C C C C C C C I R R
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V V B T 3 2 1 0 1 2 0 R V V
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E E U E E
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D D F D D
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N.C. = No Connect. This pin has no internal connection to the device.
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VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
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VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
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GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
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RESERVED = Unused I/O pin, which MUST be left unconnected.
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^ = Dedicated configuration pin.
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+ = Reserved configuration pin, which is tri-stated during user mode.
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* = Reserved configuration pin, which drives out in user mode.
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PDn = Power Down pin.
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@ = Special-purpose pin.
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# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
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& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
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Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt
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SP2_MAX
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** RESOURCE USAGE **
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Shareable External
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Logic Array Block Logic Cells I/O Pins Expanders Interconnect
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A: LC1 - LC16 6/16( 37%) 8/10( 80%) 2/16( 12%) 13/36( 36%)
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B: LC17 - LC32 14/16( 87%) 8/10( 80%) 16/16(100%) 29/36( 80%)
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C: LC33 - LC48 16/16(100%) 8/10( 80%) 6/16( 37%) 26/36( 72%)
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D: LC49 - LC64 6/16( 37%) 8/10( 80%) 2/16( 12%) 6/36( 16%)
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E: LC65 - LC80 1/16( 6%) 8/10( 80%) 1/16( 6%) 6/36( 16%)
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F: LC81 - LC96 4/16( 25%) 8/10( 80%) 3/16( 18%) 17/36( 47%)
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G: LC97 - LC112 8/16( 50%) 7/10( 70%) 5/16( 31%) 31/36( 86%)
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H: LC113 - LC128 9/16( 56%) 8/10( 80%) 7/16( 43%) 12/36( 33%)
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Total dedicated input pins used: 4/4 (100%)
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Total I/O pins used: 63/80 ( 78%)
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Total logic cells used: 64/128 ( 50%)
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Total shareable expanders used: 40/128 ( 31%)
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Total Turbo logic cells used: 55/128 ( 42%)
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Total shareable expanders not available (n/a): 2/128 ( 1%)
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Average fan-in: 5.73
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Total fan-in: 367
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Total input pins required: 29
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Total fast input logic cells required: 0
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Total output pins required: 30
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Total bidirectional pins required: 4
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Total reserved pins required 4
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Total logic cells required: 64
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Total flipflops required: 58
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Total product terms required: 222
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Total logic cells lending parallel expanders: 0
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Total shareable expanders in database: 35
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Synthesized logic cells: 0/ 128 ( 0%)
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Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt
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SP2_MAX
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** INPUTS **
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Shareable
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Expanders Fan-In Fan-Out
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
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32 56 D BIDIR 2 2 0 1 2 4 10 CLKZZ
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54 85 F OPNDRN 0 0 0 8 2 9 1 /CONF_X
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60 (93) (F) INPUT 0 0 0 0 0 1 0 D0
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89 - - INPUT 0 0 0 0 0 2 0 EPM_RES
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44 (70) (E) INPUT 0 0 0 0 0 13 0 FDD_C0
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45 (72) (E) INPUT 0 0 0 0 0 16 0 FDD_C1
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46 (73) (E) INPUT 0 0 0 0 0 14 0 FDD_C2
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33 (54) (D) INPUT 0 0 0 0 0 0 0 GND33
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65 (101) (G) INPUT 0 0 0 0 0 0 0 GND65
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47 (75) (E) INPUT 0 0 0 0 0 17 0 HDD_C0
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42 (69) (E) INPUT 0 0 0 0 0 16 0 HDD_C1
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41 (67) (E) INPUT 0 0 0 0 0 16 0 HDD_C2
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40 (65) (E) INPUT 0 0 0 0 0 13 0 HDD_C3
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90 - - INPUT 0 0 0 0 0 1 0 PW_GOOD
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92 (16) (A) INPUT 0 0 0 0 0 1 1 RDAT
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25 (33) (C) INPUT 0 0 0 0 0 0 1 RSTB
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69 (105) (G) INPUT 0 0 0 0 0 0 0 SINC_IN
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20 41 C BIDIR 0 0 0 0 8 2 0 SINC_1
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19 43 C BIDIR 2 1 0 0 11 2 0 SINC_2
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30 (59) (D) INPUT 0 0 0 0 0 0 1 SL
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29 (61) (D) INPUT 0 0 0 0 0 0 1 SR
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94 (13) (A) INPUT 0 0 0 0 0 0 1 STE
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87 - - INPUT 0 0 0 0 0 7 1 TG42_IN
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12 (21) (B) INPUT 0 0 0 0 0 0 2 TR43
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61 (94) (F) INPUT 0 0 0 0 0 0 0 VGA_IN
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9 (24) (B) INPUT 0 0 0 0 0 0 2 WD
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57 (89) (F) INPUT 0 0 0 0 0 1 0 WR_CNF
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10 (22) (B) INPUT 0 0 0 0 0 0 1 WSTB
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37 (49) (D) INPUT 0 0 0 0 0 0 1 XACS
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17 (45) (C) INPUT 0 0 0 0 0 0 0 XA0
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21 (40) (C) INPUT 0 0 0 0 0 0 0 XA1
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23 (37) (C) INPUT 0 0 0 0 0 0 0 XA2
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88 - - INPUT 0 0 0 0 0 0 0 XHR_RDY
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Code:
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s = Synthesized pin or logic cell
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t = Turbo logic cell
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+ = Synchronous flipflop
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/ = Slow slew-rate output
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! = NOT gate push-back
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r = Fitter-inserted logic cell
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Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt
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SP2_MAX
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** OUTPUTS **
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Shareable
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Expanders Fan-In Fan-Out
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
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35 53 D FF t 0 0 0 0 4 3 5 AUD
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84 126 H OUTPUT t 0 0 0 0 0 0 0 BEEP
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13 19 B FF t 2 2 0 0 4 1 4 CLK_WG
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32 56 D TRI/FF t 2 2 0 1 2 4 10 CLKZZ
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31 57 D FF t 0 0 0 0 1 0 0 CLK14
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6 29 B FF t ! 0 0 0 7 1 0 0 CMOS_AS
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99 6 A FF t 0 0 0 7 1 0 0 CMOS_DRD
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100 5 A FF t 0 0 0 7 1 0 0 CMOS_DWR
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54 85 F OPNDRN/FF t 0 0 0 8 2 9 1 /CONF_X
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96 11 A OUTPUT t 0 0 0 0 0 0 0 DENS_X
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14 17 B FF t 8 7 0 1 4 1 4 FDAT
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52 81 F OUTPUT t 0 0 0 0 0 0 0 HD_CS
|
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48 77 E FF t 1 1 0 4 2 0 0 HD_DIR
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16 46 C FF t 3 3 0 0 8 0 0 QDAT
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67 102 G OUTPUT t 0 0 0 0 2 0 0 SINC
|
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68 104 G FF t 0 0 0 0 5 4 11 SINC_H
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64 99 G FF t 4 0 0 7 9 3 8 SINC_V
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20 41 C TRI/FF t 0 0 0 0 8 2 0 SINC_1
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19 43 C TRI/FF t 2 1 0 0 11 2 0 SINC_2
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36 51 D OUTPUT t 0 0 0 1 0 1 0 TG42_BUF
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85 128 H OUTPUT t 0 0 0 0 1 0 0 TG42_OUT
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98 8 A FF t 2 0 0 0 5 0 0 WDAT
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97 9 A FF t 0 0 0 7 1 0 0 /WG_RD
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93 14 A FF t 0 0 0 7 1 0 0 /WG_WR
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||
8 25 B FF t 0 0 0 7 1 0 0 WR_PDOS
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||
76 115 H FF 1 1 0 4 2 0 0 XHD_RD
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||
71 109 G FF 0 0 0 2 1 1 0 XHD_RES
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75 113 H FF 1 1 0 4 2 0 0 XHD_WR
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||
79 120 H FF 6 6 0 8 1 0 0 XHD1_CS1
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||
80 121 H FF 6 6 0 8 1 0 0 XHD1_CS2
|
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81 123 H FF 6 6 0 8 1 0 0 XHD2_CS1
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83 125 H FF 6 6 0 8 1 0 0 XHD2_CS2
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56 88 F FF 0 0 0 4 1 10 0 10K_CLK
|
||
58 91 F FF 3 0 1 8 4 3 6 10K_D0
|
||
|
||
|
||
Code:
|
||
|
||
s = Synthesized pin or logic cell
|
||
t = Turbo logic cell
|
||
+ = Synchronous flipflop
|
||
/ = Slow slew-rate output
|
||
! = NOT gate push-back
|
||
r = Fitter-inserted logic cell
|
||
|
||
|
||
Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt
|
||
SP2_MAX
|
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|
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** BURIED LOGIC **
|
||
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||
Shareable
|
||
Expanders Fan-In Fan-Out
|
||
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
|
||
(77) 117 H DFFE t 0 0 0 1 1 2 0 CNF_OFF
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||
(21) 40 C TFFE t 0 0 0 0 1 1 4 CTH0
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- 39 C TFFE t 0 0 0 0 2 1 3 CTH1
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(15) 48 C TFFE t 0 0 0 0 5 2 3 CTH2
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(23) 37 C TFFE t 0 0 0 0 6 2 2 CTH3
|
||
(17) 45 C TFFE t 0 0 0 0 7 2 1 CTH4
|
||
- 103 G DFFE t 1 1 0 0 4 1 8 CTV0
|
||
(69) 105 G DFFE t 1 1 0 0 4 1 8 CTV1
|
||
(25) 33 C DFFE t 1 1 0 0 5 2 6 CTV2
|
||
(24) 35 C TFFE t 1 1 0 0 6 2 5 CTV3
|
||
- 44 C TFFE t 1 1 0 0 7 2 4 CTV4
|
||
(22) 38 C TFFE t 1 1 0 0 8 2 3 CTV5
|
||
- 34 C TFFE t 1 1 0 0 9 2 2 CTV6
|
||
- 47 C TFFE t 1 1 0 0 10 2 1 CTV7
|
||
- 20 B TFFE t 5 0 0 3 3 2 5 CT_WG
|
||
(12) 21 B TFFE t 0 0 0 0 1 3 7 CT0
|
||
- 18 B TFFE t 0 0 0 0 2 1 1 CT1
|
||
- 58 D TFFE t 0 0 0 0 3 1 0 CT2
|
||
(65) 101 G DFFE t 0 0 0 3 1 1 2 LR_T0
|
||
- 100 G DFFE t 0 0 0 3 1 1 2 LR_T1
|
||
- 23 B DFFE t 1 1 0 0 5 1 2 REG_P0
|
||
- 26 B DFFE t 1 1 0 0 5 1 2 REG_P1
|
||
(9) 24 B TFFE t 2 2 0 0 2 1 1 STWG0
|
||
(7) 27 B TFFE t 2 2 0 0 3 1 0 STWG1
|
||
- 42 C TFFE t 3 3 0 0 8 1 4 WGR0
|
||
- 36 C TFFE t 4 3 1 0 8 1 4 WGR1
|
||
- 28 B TFFE t 3 3 0 0 8 1 4 WGR2
|
||
(4) 32 B TFFE t 3 3 0 0 8 1 4 WGR3
|
||
(37) 49 D TFFE t 2 2 0 1 1 2 0 XCT0
|
||
(10) 22 B DFFE t 7 7 0 1 3 1 0 :180
|
||
|
||
|
||
Code:
|
||
|
||
s = Synthesized pin or logic cell
|
||
t = Turbo logic cell
|
||
+ = Synchronous flipflop
|
||
/ = Slow slew-rate output
|
||
! = NOT gate push-back
|
||
r = Fitter-inserted logic cell
|
||
|
||
|
||
Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt
|
||
SP2_MAX
|
||
|
||
** LOGIC CELL INTERCONNECTIONS **
|
||
|
||
Logic Array Block 'A':
|
||
|
||
Logic cells placed in LAB 'A'
|
||
+----------- LC6 CMOS_DRD
|
||
| +--------- LC5 CMOS_DWR
|
||
| | +------- LC11 DENS_X
|
||
| | | +----- LC8 WDAT
|
||
| | | | +--- LC9 /WG_RD
|
||
| | | | | +- LC14 /WG_WR
|
||
| | | | | |
|
||
| | | | | | Other LABs fed by signals
|
||
| | | | | | that feed LAB 'A'
|
||
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
|
||
|
||
Pin
|
||
89 -> - - - - - - | - - - - - * * - | <-- EPM_RES
|
||
44 -> * * - - * * | * * - - - * * * | <-- FDD_C0
|
||
45 -> * * - - * * | * * - - * * * * | <-- FDD_C1
|
||
46 -> * * - - * * | * * - - - * * * | <-- FDD_C2
|
||
47 -> * * - - * * | * * - - * * * * | <-- HDD_C0
|
||
42 -> * * - - * * | * * - - * * * * | <-- HDD_C1
|
||
41 -> * * - - * * | * * - - * * * * | <-- HDD_C2
|
||
40 -> * * - - * * | * * - - - * * * | <-- HDD_C3
|
||
90 -> - - - - - - | - - - - - - * - | <-- PW_GOOD
|
||
87 -> - - - - - - | - - - * - * - * | <-- TG42_IN
|
||
88 -> - - - - - - | - - - - - - - - | <-- XHR_RDY
|
||
LC20 -> - - - * - - | * * - - - - - - | <-- CT_WG
|
||
LC101-> - - - * - - | * * - - - - - - | <-- LR_T0
|
||
LC100-> - - - * - - | * * - - - - - - | <-- LR_T1
|
||
LC23 -> - - - * - - | * * - - - - - - | <-- REG_P0
|
||
LC26 -> - - - * - - | * * - - - - - - | <-- REG_P1
|
||
LC88 -> * * - - * * | * * - - * * - * | <-- 10K_CLK
|
||
|
||
|
||
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
|
||
- = The logic cell or pin is not an input to the logic cell (or LAB).
|
||
|
||
|
||
Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt
|
||
SP2_MAX
|
||
|
||
** LOGIC CELL INTERCONNECTIONS **
|
||
|
||
Logic Array Block 'B':
|
||
|
||
Logic cells placed in LAB 'B'
|
||
+--------------------------- LC19 CLK_WG
|
||
| +------------------------- LC29 CMOS_AS
|
||
| | +----------------------- LC20 CT_WG
|
||
| | | +--------------------- LC21 CT0
|
||
| | | | +------------------- LC18 CT1
|
||
| | | | | +----------------- LC17 FDAT
|
||
| | | | | | +--------------- LC23 REG_P0
|
||
| | | | | | | +------------- LC26 REG_P1
|
||
| | | | | | | | +----------- LC24 STWG0
|
||
| | | | | | | | | +--------- LC27 STWG1
|
||
| | | | | | | | | | +------- LC28 WGR2
|
||
| | | | | | | | | | | +----- LC32 WGR3
|
||
| | | | | | | | | | | | +--- LC25 WR_PDOS
|
||
| | | | | | | | | | | | | +- LC22 :180
|
||
| | | | | | | | | | | | | |
|
||
| | | | | | | | | | | | | | Other LABs fed by signals
|
||
| | | | | | | | | | | | | | that feed LAB 'B'
|
||
LC | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
|
||
LC19 -> * - - - - - - - * * - - - - | - * - - - - * - | <-- CLK_WG
|
||
LC20 -> * - * - - - * * * * - - - - | * * - - - - - - | <-- CT_WG
|
||
LC21 -> - - - * * * - - - - * * - * | - * * * - - - - | <-- CT0
|
||
LC17 -> - - - - - - - - - - * * - - | - * * - - - - - | <-- FDAT
|
||
LC23 -> - - - - - - * * - - - - - - | * * - - - - - - | <-- REG_P0
|
||
LC26 -> - - - - - - * * - - - - - - | * * - - - - - - | <-- REG_P1
|
||
LC24 -> * - - - - - - - * * - - - - | - * - - - - - - | <-- STWG0
|
||
LC27 -> * - - - - - - - - * - - - - | - * - - - - - - | <-- STWG1
|
||
LC28 -> - - - - - - - - - - * * - - | - * * - - - - - | <-- WGR2
|
||
LC32 -> - - - - - - - - - - * * - - | - * * - - - - - | <-- WGR3
|
||
LC22 -> - - - - - * - - - - - - - - | - * - - - - - - | <-- :180
|
||
|
||
Pin
|
||
89 -> - - - - - - - - - - - - - - | - - - - - * * - | <-- EPM_RES
|
||
44 -> - * - - - - - - - - - - * - | * * - - - * * * | <-- FDD_C0
|
||
45 -> - * - - - - - - - - - - * - | * * - - * * * * | <-- FDD_C1
|
||
46 -> - * - - - - - - - - - - * - | * * - - - * * * | <-- FDD_C2
|
||
47 -> - * - - - - - - - - - - * - | * * - - * * * * | <-- HDD_C0
|
||
42 -> - * - - - - - - - - - - * - | * * - - * * * * | <-- HDD_C1
|
||
41 -> - * - - - - - - - - - - * - | * * - - * * * * | <-- HDD_C2
|
||
40 -> - * - - - - - - - - - - * - | * * - - - * * * | <-- HDD_C3
|
||
90 -> - - - - - - - - - - - - - - | - - - - - - * - | <-- PW_GOOD
|
||
92 -> - - - - - * - - - - - - - * | - * - - - - - - | <-- RDAT
|
||
25 -> - - * - - - - - - - - - - - | - * - - - - - - | <-- RSTB
|
||
94 -> - - * - - - - - - - - - - - | - * - - - - - - | <-- STE
|
||
87 -> - - - - - - - - - - - - - - | - - - * - * - * | <-- TG42_IN
|
||
10 -> - - * - - - - - - - - - - - | - * - - - - - - | <-- WSTB
|
||
88 -> - - - - - - - - - - - - - - | - - - - - - - - | <-- XHR_RDY
|
||
LC56 -> - - * * * * - - - - * * - * | - * * * - - - - | <-- CLKZZ
|
||
LC101-> - - - - - - * * - - - - - - | * * - - - - - - | <-- LR_T0
|
||
LC100-> - - - - - - * * - - - - - - | * * - - - - - - | <-- LR_T1
|
||
LC42 -> - - - - - - - - - - * * - - | - * * - - - - - | <-- WGR0
|
||
LC36 -> - - - - - - - - - - * * - - | - * * - - - - - | <-- WGR1
|
||
LC88 -> - * - - - - - - - - - - * - | * * - - * * - * | <-- 10K_CLK
|
||
LC91 -> - - * - - * - - - - * * - * | - * * - - * - - | <-- 10K_D0
|
||
|
||
|
||
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
|
||
- = The logic cell or pin is not an input to the logic cell (or LAB).
|
||
|
||
|
||
Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt
|
||
SP2_MAX
|
||
|
||
** LOGIC CELL INTERCONNECTIONS **
|
||
|
||
Logic Array Block 'C':
|
||
|
||
Logic cells placed in LAB 'C'
|
||
+------------------------------- LC40 CTH0
|
||
| +----------------------------- LC39 CTH1
|
||
| | +--------------------------- LC48 CTH2
|
||
| | | +------------------------- LC37 CTH3
|
||
| | | | +----------------------- LC45 CTH4
|
||
| | | | | +--------------------- LC33 CTV2
|
||
| | | | | | +------------------- LC35 CTV3
|
||
| | | | | | | +----------------- LC44 CTV4
|
||
| | | | | | | | +--------------- LC38 CTV5
|
||
| | | | | | | | | +------------- LC34 CTV6
|
||
| | | | | | | | | | +----------- LC47 CTV7
|
||
| | | | | | | | | | | +--------- LC46 QDAT
|
||
| | | | | | | | | | | | +------- LC41 SINC_1
|
||
| | | | | | | | | | | | | +----- LC43 SINC_2
|
||
| | | | | | | | | | | | | | +--- LC42 WGR0
|
||
| | | | | | | | | | | | | | | +- LC36 WGR1
|
||
| | | | | | | | | | | | | | | |
|
||
| | | | | | | | | | | | | | | | Other LABs fed by signals
|
||
| | | | | | | | | | | | | | | | that feed LAB 'C'
|
||
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
|
||
LC40 -> * * * * * - - - - - - - * - - - | - - * - - - - - | <-- CTH0
|
||
LC39 -> - * * * * - - - - - - - * - - - | - - * - - - - - | <-- CTH1
|
||
LC48 -> - - * * * - - - - - - - * - - - | - - * - - - * - | <-- CTH2
|
||
LC37 -> - - - * * - - - - - - - * - - - | - - * - - - * - | <-- CTH3
|
||
LC45 -> - - - - * - - - - - - - * - - - | - - * - - - * - | <-- CTH4
|
||
LC33 -> - - - - - * * * * * * - - * - - | - - * - - - * - | <-- CTV2
|
||
LC35 -> - - - - - - * * * * * - - * - - | - - * - - - * - | <-- CTV3
|
||
LC44 -> - - - - - - - * * * * - - * - - | - - * - - - * - | <-- CTV4
|
||
LC38 -> - - - - - - - - * * * - - * - - | - - * - - - * - | <-- CTV5
|
||
LC34 -> - - - - - - - - - * * - - * - - | - - * - - - * - | <-- CTV6
|
||
LC47 -> - - - - - - - - - - * - - * - - | - - * - - - * - | <-- CTV7
|
||
LC41 -> - - - - - - - - - - - - * - - - | - - * - - - * - | <-- SINC_1
|
||
LC43 -> - - - - - - - - - - - - - * - - | - - * - - - * - | <-- SINC_2
|
||
LC42 -> - - - - - - - - - - - * - - * * | - * * - - - - - | <-- WGR0
|
||
LC36 -> - - - - - - - - - - - * - - * * | - * * - - - - - | <-- WGR1
|
||
|
||
Pin
|
||
89 -> - - - - - - - - - - - - - - - - | - - - - - * * - | <-- EPM_RES
|
||
90 -> - - - - - - - - - - - - - - - - | - - - - - - * - | <-- PW_GOOD
|
||
87 -> - - - - - - - - - - - - - - - - | - - - * - * - * | <-- TG42_IN
|
||
88 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- XHR_RDY
|
||
LC53 -> * * * * * - - - - - - - * - - - | - - * - - * * - | <-- AUD
|
||
LC56 -> - - - - - - - - - - - * - - * * | - * * * - - - - | <-- CLKZZ
|
||
LC103-> - - - - - * * * * * * - - * - - | - - * - - - * - | <-- CTV0
|
||
LC105-> - - - - - * * * * * * - - * - - | - - * - - - * - | <-- CTV1
|
||
LC21 -> - - - - - - - - - - - * - - * * | - * * * - - - - | <-- CT0
|
||
LC17 -> - - - - - - - - - - - * - - * * | - * * - - - - - | <-- FDAT
|
||
LC104-> - - * * * * * * * * * - * * - - | - - * - - - * - | <-- SINC_H
|
||
LC99 -> - - - - - * * * * * * - - * - - | - - * - - - * - | <-- SINC_V
|
||
LC28 -> - - - - - - - - - - - * - - * * | - * * - - - - - | <-- WGR2
|
||
LC32 -> - - - - - - - - - - - * - - * * | - * * - - - - - | <-- WGR3
|
||
LC91 -> - - - - - - - - - - - * - - * * | - * * - - * - - | <-- 10K_D0
|
||
|
||
|
||
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
|
||
- = The logic cell or pin is not an input to the logic cell (or LAB).
|
||
|
||
|
||
Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt
|
||
SP2_MAX
|
||
|
||
** LOGIC CELL INTERCONNECTIONS **
|
||
|
||
Logic Array Block 'D':
|
||
|
||
Logic cells placed in LAB 'D'
|
||
+----------- LC53 AUD
|
||
| +--------- LC56 CLKZZ
|
||
| | +------- LC57 CLK14
|
||
| | | +----- LC58 CT2
|
||
| | | | +--- LC51 TG42_BUF
|
||
| | | | | +- LC49 XCT0
|
||
| | | | | |
|
||
| | | | | | Other LABs fed by signals
|
||
| | | | | | that feed LAB 'D'
|
||
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'D':
|
||
LC56 -> * * - * - * | - * * * - - - - | <-- CLKZZ
|
||
LC58 -> * - - * - - | - - - * - - - - | <-- CT2
|
||
LC49 -> - * * - - * | - - - * - - - - | <-- XCT0
|
||
|
||
Pin
|
||
89 -> - - - - - - | - - - - - * * - | <-- EPM_RES
|
||
90 -> - - - - - - | - - - - - - * - | <-- PW_GOOD
|
||
87 -> - * - - * * | - - - * - * - * | <-- TG42_IN
|
||
88 -> - - - - - - | - - - - - - - - | <-- XHR_RDY
|
||
LC21 -> * - - * - - | - * * * - - - - | <-- CT0
|
||
LC18 -> * - - * - - | - - - * - - - - | <-- CT1
|
||
|
||
|
||
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
|
||
- = The logic cell or pin is not an input to the logic cell (or LAB).
|
||
|
||
|
||
Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt
|
||
SP2_MAX
|
||
|
||
** LOGIC CELL INTERCONNECTIONS **
|
||
|
||
Logic Array Block 'E':
|
||
|
||
Logic cells placed in LAB 'E'
|
||
+- LC77 HD_DIR
|
||
|
|
||
| Other LABs fed by signals
|
||
| that feed LAB 'E'
|
||
LC | | A B C D E F G H | Logic cells that feed LAB 'E':
|
||
|
||
Pin
|
||
89 -> - | - - - - - * * - | <-- EPM_RES
|
||
45 -> * | * * - - * * * * | <-- FDD_C1
|
||
47 -> * | * * - - * * * * | <-- HDD_C0
|
||
42 -> * | * * - - * * * * | <-- HDD_C1
|
||
41 -> * | * * - - * * * * | <-- HDD_C2
|
||
90 -> - | - - - - - - * - | <-- PW_GOOD
|
||
87 -> - | - - - * - * - * | <-- TG42_IN
|
||
88 -> - | - - - - - - - - | <-- XHR_RDY
|
||
LC85 -> * | - - - - * * * * | <-- /CONF_X
|
||
LC88 -> * | * * - - * * - * | <-- 10K_CLK
|
||
|
||
|
||
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
|
||
- = The logic cell or pin is not an input to the logic cell (or LAB).
|
||
|
||
|
||
Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt
|
||
SP2_MAX
|
||
|
||
** LOGIC CELL INTERCONNECTIONS **
|
||
|
||
Logic Array Block 'F':
|
||
|
||
Logic cells placed in LAB 'F'
|
||
+------- LC85 /CONF_X
|
||
| +----- LC81 HD_CS
|
||
| | +--- LC88 10K_CLK
|
||
| | | +- LC91 10K_D0
|
||
| | | |
|
||
| | | | Other LABs fed by signals
|
||
| | | | that feed LAB 'F'
|
||
LC | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
|
||
LC85 -> - - - * | - - - - * * * * | <-- /CONF_X
|
||
LC88 -> - - - * | * * - - * * - * | <-- 10K_CLK
|
||
LC91 -> - - - * | - * * - - * - - | <-- 10K_D0
|
||
|
||
Pin
|
||
60 -> - - - * | - - - - - * - - | <-- D0
|
||
89 -> * - - - | - - - - - * * - | <-- EPM_RES
|
||
44 -> * - - * | * * - - - * * * | <-- FDD_C0
|
||
45 -> * - - * | * * - - * * * * | <-- FDD_C1
|
||
46 -> * - * * | * * - - - * * * | <-- FDD_C2
|
||
47 -> * - * * | * * - - * * * * | <-- HDD_C0
|
||
42 -> * - - * | * * - - * * * * | <-- HDD_C1
|
||
41 -> * - - * | * * - - * * * * | <-- HDD_C2
|
||
40 -> * - - * | * * - - - * * * | <-- HDD_C3
|
||
90 -> - - - - | - - - - - - * - | <-- PW_GOOD
|
||
87 -> - - * - | - - - * - * - * | <-- TG42_IN
|
||
57 -> - - * - | - - - - - * - - | <-- WR_CNF
|
||
88 -> - - - - | - - - - - - - - | <-- XHR_RDY
|
||
LC53 -> * - - - | - - * - - * * - | <-- AUD
|
||
LC117-> - - * * | - - - - - * - - | <-- CNF_OFF
|
||
LC109-> * - - - | - - - - - * - - | <-- XHD_RES
|
||
|
||
|
||
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
|
||
- = The logic cell or pin is not an input to the logic cell (or LAB).
|
||
|
||
|
||
Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt
|
||
SP2_MAX
|
||
|
||
** LOGIC CELL INTERCONNECTIONS **
|
||
|
||
Logic Array Block 'G':
|
||
|
||
Logic cells placed in LAB 'G'
|
||
+--------------- LC103 CTV0
|
||
| +------------- LC105 CTV1
|
||
| | +----------- LC101 LR_T0
|
||
| | | +--------- LC100 LR_T1
|
||
| | | | +------- LC102 SINC
|
||
| | | | | +----- LC104 SINC_H
|
||
| | | | | | +--- LC99 SINC_V
|
||
| | | | | | | +- LC109 XHD_RES
|
||
| | | | | | | |
|
||
| | | | | | | | Other LABs fed by signals
|
||
| | | | | | | | that feed LAB 'G'
|
||
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
|
||
LC103-> * * - - - - - - | - - * - - - * - | <-- CTV0
|
||
LC105-> * * - - - - - - | - - * - - - * - | <-- CTV1
|
||
LC104-> * * - - * - * - | - - * - - - * - | <-- SINC_H
|
||
LC99 -> * * - - * - - * | - - * - - - * - | <-- SINC_V
|
||
|
||
Pin
|
||
89 -> - - - - - - - * | - - - - - * * - | <-- EPM_RES
|
||
44 -> - - - - - - * - | * * - - - * * * | <-- FDD_C0
|
||
45 -> - - - - - - * - | * * - - * * * * | <-- FDD_C1
|
||
46 -> - - - - - - * - | * * - - - * * * | <-- FDD_C2
|
||
47 -> - - - - - - * - | * * - - * * * * | <-- HDD_C0
|
||
42 -> - - - - - - * - | * * - - * * * * | <-- HDD_C1
|
||
41 -> - - - - - - * - | * * - - * * * * | <-- HDD_C2
|
||
40 -> - - - - - - * - | * * - - - * * * | <-- HDD_C3
|
||
90 -> - - - - - - - * | - - - - - - * - | <-- PW_GOOD
|
||
30 -> - - - * - - - - | - - - - - - * - | <-- SL
|
||
29 -> - - * - - - - - | - - - - - - * - | <-- SR
|
||
87 -> - - - - - - - - | - - - * - * - * | <-- TG42_IN
|
||
12 -> - - * * - - - - | - - - - - - * - | <-- TR43
|
||
9 -> - - * * - - - - | - - - - - - * - | <-- WD
|
||
88 -> - - - - - - - - | - - - - - - - - | <-- XHR_RDY
|
||
LC53 -> - - - - - * - - | - - * - - * * - | <-- AUD
|
||
LC19 -> - - * * - - - - | - * - - - - * - | <-- CLK_WG
|
||
LC85 -> - - - - - - * - | - - - - * * * * | <-- /CONF_X
|
||
LC48 -> - - - - - * - - | - - * - - - * - | <-- CTH2
|
||
LC37 -> - - - - - * - - | - - * - - - * - | <-- CTH3
|
||
LC45 -> - - - - - * - - | - - * - - - * - | <-- CTH4
|
||
LC33 -> - - - - - - * - | - - * - - - * - | <-- CTV2
|
||
LC35 -> - - - - - - * - | - - * - - - * - | <-- CTV3
|
||
LC44 -> - - - - - - * - | - - * - - - * - | <-- CTV4
|
||
LC38 -> - - - - - - * - | - - * - - - * - | <-- CTV5
|
||
LC34 -> - - - - - - * - | - - * - - - * - | <-- CTV6
|
||
LC47 -> - - - - - - * - | - - * - - - * - | <-- CTV7
|
||
LC41 -> - - - - - * - - | - - * - - - * - | <-- SINC_1
|
||
LC43 -> - - - - - - * - | - - * - - - * - | <-- SINC_2
|
||
|
||
|
||
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
|
||
- = The logic cell or pin is not an input to the logic cell (or LAB).
|
||
|
||
|
||
Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt
|
||
SP2_MAX
|
||
|
||
** LOGIC CELL INTERCONNECTIONS **
|
||
|
||
Logic Array Block 'H':
|
||
|
||
Logic cells placed in LAB 'H'
|
||
+----------------- LC126 BEEP
|
||
| +--------------- LC117 CNF_OFF
|
||
| | +------------- LC128 TG42_OUT
|
||
| | | +----------- LC115 XHD_RD
|
||
| | | | +--------- LC113 XHD_WR
|
||
| | | | | +------- LC120 XHD1_CS1
|
||
| | | | | | +----- LC121 XHD1_CS2
|
||
| | | | | | | +--- LC123 XHD2_CS1
|
||
| | | | | | | | +- LC125 XHD2_CS2
|
||
| | | | | | | | |
|
||
| | | | | | | | | Other LABs fed by signals
|
||
| | | | | | | | | that feed LAB 'H'
|
||
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
|
||
|
||
Pin
|
||
89 -> - - - - - - - - - | - - - - - * * - | <-- EPM_RES
|
||
44 -> - - - - - * * * * | * * - - - * * * | <-- FDD_C0
|
||
45 -> - - - * * * * * * | * * - - * * * * | <-- FDD_C1
|
||
46 -> - - - - - * * * * | * * - - - * * * | <-- FDD_C2
|
||
47 -> - - - * * * * * * | * * - - * * * * | <-- HDD_C0
|
||
42 -> - - - * * * * * * | * * - - * * * * | <-- HDD_C1
|
||
41 -> - - - * * * * * * | * * - - * * * * | <-- HDD_C2
|
||
40 -> - - - - - * * * * | * * - - - * * * | <-- HDD_C3
|
||
90 -> - - - - - - - - - | - - - - - - * - | <-- PW_GOOD
|
||
87 -> - - - - - * * * * | - - - * - * - * | <-- TG42_IN
|
||
37 -> - * - - - - - - - | - - - - - - - * | <-- XACS
|
||
88 -> - - - - - - - - - | - - - - - - - - | <-- XHR_RDY
|
||
LC85 -> - * - * * * * * * | - - - - * * * * | <-- /CONF_X
|
||
LC51 -> - - * - - - - - - | - - - - - - - * | <-- TG42_BUF
|
||
LC88 -> - - - * * - - - - | * * - - * * - * | <-- 10K_CLK
|
||
|
||
|
||
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
|
||
- = The logic cell or pin is not an input to the logic cell (or LAB).
|
||
|
||
|
||
Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt
|
||
SP2_MAX
|
||
|
||
** EQUATIONS **
|
||
|
||
D0 : INPUT;
|
||
EPM_RES : INPUT;
|
||
FDD_C0 : INPUT;
|
||
FDD_C1 : INPUT;
|
||
FDD_C2 : INPUT;
|
||
GND33 : INPUT;
|
||
GND65 : INPUT;
|
||
HDD_C0 : INPUT;
|
||
HDD_C1 : INPUT;
|
||
HDD_C2 : INPUT;
|
||
HDD_C3 : INPUT;
|
||
PW_GOOD : INPUT;
|
||
RDAT : INPUT;
|
||
RSTB : INPUT;
|
||
SINC_IN : INPUT;
|
||
SL : INPUT;
|
||
SR : INPUT;
|
||
STE : INPUT;
|
||
TG42_IN : INPUT;
|
||
TR43 : INPUT;
|
||
VGA_IN : INPUT;
|
||
WD : INPUT;
|
||
WR_CNF : INPUT;
|
||
WSTB : INPUT;
|
||
XACS : INPUT;
|
||
XA0 : INPUT;
|
||
XA1 : INPUT;
|
||
XA2 : INPUT;
|
||
XHR_RDY : INPUT;
|
||
|
||
-- Node name is 'AUD' = 'CT3' from file "sp2_max.tdf" line 100, column 4
|
||
-- Equation name is 'AUD', location is LC053, type is output.
|
||
AUD = TFFE( _EQ001, XCT1, VCC, VCC, VCC);
|
||
_EQ001 = CT0 & CT1 & CT2;
|
||
|
||
-- Node name is 'BEEP'
|
||
-- Equation name is 'BEEP', location is LC126, type is output.
|
||
BEEP = LCELL( GND $ GND);
|
||
|
||
-- Node name is 'CLK_WG' = 'STWG2' from file "sp2_max.tdf" line 114, column 6
|
||
-- Equation name is 'CLK_WG', location is LC019, type is output.
|
||
CLK_WG = TFFE( _EQ002, _EQ003, VCC, VCC, VCC);
|
||
_EQ002 = STWG0 & STWG1;
|
||
_EQ003 = _X001 & _X002;
|
||
_X001 = EXP(!CLK_WG & !CT_WG);
|
||
_X002 = EXP( CLK_WG & CT_WG);
|
||
|
||
-- Node name is 'CLKZZ' = 'XCT1' from file "sp2_max.tdf" line 94, column 5
|
||
-- Equation name is 'CLKZZ', location is LC056, type is bidir.
|
||
CLKZZ = TRI(XCT1, CNF_OFF);
|
||
XCT1 = TFFE( XCT0, _EQ004, VCC, VCC, VCC);
|
||
_EQ004 = _X003 & _X004;
|
||
_X003 = EXP(!TG42_IN & XCT1);
|
||
_X004 = EXP( TG42_IN & !XCT1);
|
||
|
||
-- Node name is 'CLK14' = ':166' from file "sp2_max.tdf" line 258, column 11
|
||
-- Equation name is 'CLK14', type is output
|
||
CLK14 = TFFE( VCC, XCT0, VCC, VCC, VCC);
|
||
|
||
-- Node name is 'CMOS_AS' = ':202' from file "sp2_max.tdf" line 431, column 13
|
||
-- Equation name is 'CMOS_AS', type is output
|
||
CMOS_AS = _LC029~NOT;
|
||
_LC029~NOT = DFFE( _EQ005 $ GND, 10K_CLK, FDD_C2, VCC, VCC);
|
||
_EQ005 = FDD_C0 & !FDD_C1 & !HDD_C0 & HDD_C1 & HDD_C2 & !HDD_C3;
|
||
|
||
-- Node name is 'CMOS_DRD' = ':203' from file "sp2_max.tdf" line 432, column 13
|
||
-- Equation name is 'CMOS_DRD', type is output
|
||
CMOS_DRD = DFFE( _EQ006 $ VCC, 10K_CLK, VCC, FDD_C2, VCC);
|
||
_EQ006 = !FDD_C0 & FDD_C1 & !HDD_C0 & HDD_C1 & HDD_C2 & HDD_C3;
|
||
|
||
-- Node name is 'CMOS_DWR' = ':201' from file "sp2_max.tdf" line 430, column 13
|
||
-- Equation name is 'CMOS_DWR', type is output
|
||
CMOS_DWR = DFFE( _EQ007 $ VCC, 10K_CLK, VCC, FDD_C2, VCC);
|
||
_EQ007 = FDD_C0 & !FDD_C1 & !HDD_C0 & HDD_C1 & HDD_C2 & HDD_C3;
|
||
|
||
-- Node name is 'CNF_OFF' from file "sp2_max.tdf" line 265, column 12
|
||
-- Equation name is 'CNF_OFF', location is LC117, type is buried.
|
||
CNF_OFF = DFFE( GND $ GND, GND, XACS, /CONF_X, VCC);
|
||
|
||
-- Node name is 'CTH0' from file "sp2_max.tdf" line 101, column 5
|
||
-- Equation name is 'CTH0', location is LC040, type is buried.
|
||
CTH0 = TFFE( VCC, !AUD, VCC, VCC, VCC);
|
||
|
||
-- Node name is 'CTH1' from file "sp2_max.tdf" line 101, column 5
|
||
-- Equation name is 'CTH1', location is LC039, type is buried.
|
||
CTH1 = TFFE( CTH0, !AUD, VCC, VCC, VCC);
|
||
|
||
-- Node name is 'CTH2' from file "sp2_max.tdf" line 101, column 5
|
||
-- Equation name is 'CTH2', location is LC048, type is buried.
|
||
CTH2 = TFFE( _EQ008, !AUD, VCC, VCC, VCC);
|
||
_EQ008 = CTH0 & CTH1 & !CTH2 & !SINC_H
|
||
# CTH0 & CTH1 & CTH2;
|
||
|
||
-- Node name is 'CTH3' from file "sp2_max.tdf" line 101, column 5
|
||
-- Equation name is 'CTH3', location is LC037, type is buried.
|
||
CTH3 = TFFE( _EQ009, !AUD, VCC, VCC, VCC);
|
||
_EQ009 = CTH0 & CTH1 & CTH2 & !CTH3 & !SINC_H
|
||
# CTH0 & CTH1 & CTH2 & CTH3
|
||
# CTH0 & CTH1 & CTH3 & SINC_H;
|
||
|
||
-- Node name is 'CTH4' from file "sp2_max.tdf" line 101, column 5
|
||
-- Equation name is 'CTH4', location is LC045, type is buried.
|
||
CTH4 = TFFE( _EQ010, !AUD, VCC, VCC, VCC);
|
||
_EQ010 = CTH0 & CTH1 & CTH2 & CTH3 & !CTH4 & !SINC_H
|
||
# CTH0 & CTH1 & CTH2 & CTH3 & CTH4
|
||
# CTH0 & CTH1 & CTH4 & SINC_H;
|
||
|
||
-- Node name is 'CTV0' from file "sp2_max.tdf" line 102, column 5
|
||
-- Equation name is 'CTV0', location is LC103, type is buried.
|
||
CTV0 = DFFE( _EQ011 $ GND, SINC_H, VCC, VCC, VCC);
|
||
_EQ011 = !CTV0 & _X005;
|
||
_X005 = EXP( CTV0 & CTV1 & SINC_V);
|
||
|
||
-- Node name is 'CTV1' from file "sp2_max.tdf" line 102, column 5
|
||
-- Equation name is 'CTV1', location is LC105, type is buried.
|
||
CTV1 = DFFE( _EQ012 $ GND, SINC_H, VCC, VCC, VCC);
|
||
_EQ012 = !CTV0 & CTV1 & _X005
|
||
# CTV0 & !CTV1 & _X005;
|
||
_X005 = EXP( CTV0 & CTV1 & SINC_V);
|
||
|
||
-- Node name is 'CTV2' from file "sp2_max.tdf" line 102, column 5
|
||
-- Equation name is 'CTV2', location is LC033, type is buried.
|
||
CTV2 = DFFE( _EQ013 $ GND, SINC_H, VCC, VCC, VCC);
|
||
_EQ013 = CTV0 & CTV1 & !CTV2 & _X005
|
||
# !CTV0 & CTV2 & _X005
|
||
# !CTV1 & CTV2 & _X005;
|
||
_X005 = EXP( CTV0 & CTV1 & SINC_V);
|
||
|
||
-- Node name is 'CTV3' from file "sp2_max.tdf" line 102, column 5
|
||
-- Equation name is 'CTV3', location is LC035, type is buried.
|
||
CTV3 = TFFE( _EQ014, SINC_H, VCC, VCC, VCC);
|
||
_EQ014 = CTV0 & CTV1 & CTV2 & !CTV3 & _X005
|
||
# CTV0 & CTV1 & CTV2 & CTV3
|
||
# CTV0 & CTV1 & CTV3 & SINC_V;
|
||
_X005 = EXP( CTV0 & CTV1 & SINC_V);
|
||
|
||
-- Node name is 'CTV4' from file "sp2_max.tdf" line 102, column 5
|
||
-- Equation name is 'CTV4', location is LC044, type is buried.
|
||
CTV4 = TFFE( _EQ015, SINC_H, VCC, VCC, VCC);
|
||
_EQ015 = CTV0 & CTV1 & CTV2 & CTV3 & !CTV4 & _X005
|
||
# CTV0 & CTV1 & CTV2 & CTV3 & CTV4
|
||
# CTV0 & CTV1 & CTV4 & SINC_V;
|
||
_X005 = EXP( CTV0 & CTV1 & SINC_V);
|
||
|
||
-- Node name is 'CTV5' from file "sp2_max.tdf" line 102, column 5
|
||
-- Equation name is 'CTV5', location is LC038, type is buried.
|
||
CTV5 = TFFE( _EQ016, SINC_H, VCC, VCC, VCC);
|
||
_EQ016 = CTV0 & CTV1 & CTV2 & CTV3 & CTV4 & !CTV5 & _X005
|
||
# CTV0 & CTV1 & CTV2 & CTV3 & CTV4 & CTV5
|
||
# CTV0 & CTV1 & CTV5 & SINC_V;
|
||
_X005 = EXP( CTV0 & CTV1 & SINC_V);
|
||
|
||
-- Node name is 'CTV6' from file "sp2_max.tdf" line 102, column 5
|
||
-- Equation name is 'CTV6', location is LC034, type is buried.
|
||
CTV6 = TFFE( _EQ017, SINC_H, VCC, VCC, VCC);
|
||
_EQ017 = CTV0 & CTV1 & CTV2 & CTV3 & CTV4 & CTV5 & !CTV6 & _X005
|
||
# CTV0 & CTV1 & CTV2 & CTV3 & CTV4 & CTV5 & CTV6
|
||
# CTV0 & CTV1 & CTV6 & SINC_V;
|
||
_X005 = EXP( CTV0 & CTV1 & SINC_V);
|
||
|
||
-- Node name is 'CTV7' from file "sp2_max.tdf" line 102, column 5
|
||
-- Equation name is 'CTV7', location is LC047, type is buried.
|
||
CTV7 = TFFE( _EQ018, SINC_H, VCC, VCC, VCC);
|
||
_EQ018 = CTV0 & CTV1 & CTV2 & CTV3 & CTV4 & CTV5 & CTV6 & !CTV7 &
|
||
_X005
|
||
# CTV0 & CTV1 & CTV2 & CTV3 & CTV4 & CTV5 & CTV6 & CTV7
|
||
# CTV0 & CTV1 & CTV7 & SINC_V;
|
||
_X005 = EXP( CTV0 & CTV1 & SINC_V);
|
||
|
||
-- Node name is 'CT_WG' from file "sp2_max.tdf" line 275, column 11
|
||
-- Equation name is 'CT_WG', location is LC020, type is buried.
|
||
CT_WG = TFFE( VCC, _EQ019, VCC, VCC, VCC);
|
||
_EQ019 = _X006 & _X007 & _X008;
|
||
_X006 = EXP(!CT_WG & !XCT1);
|
||
_X007 = EXP( CT_WG & XCT1 & _X009);
|
||
_X008 = EXP(!STE & !XCT1 & _X010 & !10K_D0);
|
||
_X009 = EXP(!STE & _X010 & !10K_D0);
|
||
_X010 = EXP(!RSTB & !WSTB & _X009);
|
||
|
||
-- Node name is 'CT0' from file "sp2_max.tdf" line 100, column 4
|
||
-- Equation name is 'CT0', location is LC021, type is buried.
|
||
CT0 = TFFE( VCC, XCT1, VCC, VCC, VCC);
|
||
|
||
-- Node name is 'CT1' from file "sp2_max.tdf" line 100, column 4
|
||
-- Equation name is 'CT1', location is LC018, type is buried.
|
||
CT1 = TFFE( CT0, XCT1, VCC, VCC, VCC);
|
||
|
||
-- Node name is 'CT2' from file "sp2_max.tdf" line 100, column 4
|
||
-- Equation name is 'CT2', location is LC058, type is buried.
|
||
CT2 = TFFE( _EQ020, XCT1, VCC, VCC, VCC);
|
||
_EQ020 = CT0 & CT1;
|
||
|
||
-- Node name is 'DENS_X'
|
||
-- Equation name is 'DENS_X', location is LC011, type is output.
|
||
DENS_X = LCELL( GND $ VCC);
|
||
|
||
-- Node name is 'FDAT' = ':178' from file "sp2_max.tdf" line 309, column 9
|
||
-- Equation name is 'FDAT', type is output
|
||
FDAT = DFFE( _EQ021 $ VCC, _EQ022, VCC, VCC, VCC);
|
||
_EQ021 = _LC022 & _X011 & _X012;
|
||
_X011 = EXP( RDAT & _X013 & _X014);
|
||
_X012 = EXP( _X015 & _X016);
|
||
_X013 = EXP( CT0 & !10K_D0);
|
||
_X014 = EXP( XCT1 & 10K_D0);
|
||
_X015 = EXP(!RDAT & _X013 & _X014);
|
||
_X016 = EXP( _X012 & _X017);
|
||
_X017 = EXP( RDAT & _X013 & _X014);
|
||
_EQ022 = _X018;
|
||
_X018 = EXP( _X013 & _X014);
|
||
_X013 = EXP( CT0 & !10K_D0);
|
||
_X014 = EXP( XCT1 & 10K_D0);
|
||
|
||
-- Node name is 'HD_CS'
|
||
-- Equation name is 'HD_CS', location is LC081, type is output.
|
||
HD_CS = LCELL( GND $ GND);
|
||
|
||
-- Node name is 'HD_DIR' = ':206' from file "sp2_max.tdf" line 460, column 27
|
||
-- Equation name is 'HD_DIR', type is output
|
||
HD_DIR = DFFE( _EQ023 $ VCC, 10K_CLK, VCC, !_EQ024, VCC);
|
||
_EQ023 = FDD_C1 & HDD_C0 & !HDD_C1 & HDD_C2;
|
||
_EQ024 = _X019;
|
||
_X019 = EXP( /CONF_X & HDD_C0);
|
||
|
||
-- Node name is 'LR_T0' from file "sp2_max.tdf" line 141, column 6
|
||
-- Equation name is 'LR_T0', location is LC101, type is buried.
|
||
LR_T0 = DFFE( _EQ025 $ WD, CLK_WG, VCC, VCC, VCC);
|
||
_EQ025 = SR & TR43 & WD;
|
||
|
||
-- Node name is 'LR_T1' from file "sp2_max.tdf" line 141, column 6
|
||
-- Equation name is 'LR_T1', location is LC100, type is buried.
|
||
LR_T1 = DFFE( _EQ026 $ WD, CLK_WG, VCC, VCC, VCC);
|
||
_EQ026 = SL & TR43 & WD;
|
||
|
||
-- Node name is 'QDAT' = 'WGR4' from file "sp2_max.tdf" line 116, column 5
|
||
-- Equation name is 'QDAT', location is LC046, type is output.
|
||
QDAT = TFFE( _EQ027, _EQ028, VCC, VCC, VCC);
|
||
_EQ027 = FDAT & WGR0 & WGR1 & WGR2 & WGR3;
|
||
_EQ028 = _X018;
|
||
_X018 = EXP( _X013 & _X014);
|
||
_X013 = EXP( CT0 & !10K_D0);
|
||
_X014 = EXP( XCT1 & 10K_D0);
|
||
|
||
-- Node name is 'REG_P0' from file "sp2_max.tdf" line 119, column 7
|
||
-- Equation name is 'REG_P0', location is LC023, type is buried.
|
||
REG_P0 = DFFE( _EQ029 $ LR_T0, !CT_WG, VCC, VCC, VCC);
|
||
_EQ029 = !LR_T0 & !LR_T1 & !REG_P0 & _X020
|
||
# LR_T1;
|
||
_X020 = EXP(!REG_P0 & !REG_P1);
|
||
|
||
-- Node name is 'REG_P1' from file "sp2_max.tdf" line 119, column 7
|
||
-- Equation name is 'REG_P1', location is LC026, type is buried.
|
||
REG_P1 = DFFE( _EQ030 $ LR_T1, !CT_WG, VCC, VCC, VCC);
|
||
_EQ030 = !LR_T0 & !LR_T1 & REG_P0 & REG_P1 & _X020
|
||
# !LR_T0 & !LR_T1 & !REG_P0 & !REG_P1 & _X020;
|
||
_X020 = EXP(!REG_P0 & !REG_P1);
|
||
|
||
-- Node name is 'SINC'
|
||
-- Equation name is 'SINC', location is LC102, type is output.
|
||
SINC = LCELL( SINC_V $ SINC_H);
|
||
|
||
-- Node name is 'SINC_H' = 'SINC_HT' from file "sp2_max.tdf" line 104, column 2
|
||
-- Equation name is 'SINC_H', location is LC104, type is output.
|
||
SINC_H = DFFE( _EQ031 $ GND, !AUD, VCC, VCC, VCC);
|
||
_EQ031 = CTH2 & !CTH3 & CTH4 & SINC_1;
|
||
|
||
-- Node name is 'SINC_V' = 'SINC_VT' from file "sp2_max.tdf" line 105, column 2
|
||
-- Equation name is 'SINC_V', location is LC099, type is output.
|
||
SINC_V = DFFE( _EQ032 $ GND, SINC_H, VCC, VCC, VCC);
|
||
_EQ032 = CTV2 & !CTV3 & CTV4 & CTV5 & !CTV6 & !CTV7 & SINC_2 & _X021
|
||
# CTV2 & CTV3 & CTV4 & CTV5 & !CTV6 & !CTV7 & SINC_2;
|
||
_X021 = EXP( _X022 & _X023);
|
||
_X022 = EXP( FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & !HDD_C1 & !HDD_C2 &
|
||
HDD_C3);
|
||
_X023 = EXP( /CONF_X & _X021 & _X024);
|
||
_X024 = EXP(!FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & !HDD_C1 & !HDD_C2 &
|
||
HDD_C3);
|
||
|
||
-- Node name is 'SINC_1' = 'CTH5' from file "sp2_max.tdf" line 101, column 5
|
||
-- Equation name is 'SINC_1', location is LC041, type is bidir.
|
||
SINC_1 = TRI(CTH5, VCC);
|
||
CTH5 = TFFE( _EQ033, !AUD, VCC, VCC, VCC);
|
||
_EQ033 = CTH0 & CTH1 & CTH2 & CTH3 & CTH4 & !SINC_H & !SINC_1
|
||
# CTH0 & CTH1 & CTH2 & CTH3 & CTH4 & SINC_1
|
||
# CTH0 & CTH1 & SINC_H & SINC_1;
|
||
|
||
-- Node name is 'SINC_2' = 'CTV8' from file "sp2_max.tdf" line 102, column 5
|
||
-- Equation name is 'SINC_2', location is LC043, type is bidir.
|
||
SINC_2 = TRI(CTV8, VCC);
|
||
CTV8 = DFFE( _EQ034 $ GND, SINC_H, VCC, VCC, VCC);
|
||
_EQ034 = CTV0 & CTV1 & CTV2 & CTV3 & CTV4 & CTV5 & CTV6 & CTV7 &
|
||
!SINC_2 & _X005
|
||
# SINC_2 & _X005 & _X025;
|
||
_X005 = EXP( CTV0 & CTV1 & SINC_V);
|
||
_X025 = EXP( CTV0 & CTV1 & CTV2 & CTV3 & CTV4 & CTV5 & CTV6 & CTV7);
|
||
|
||
-- Node name is 'STWG0' from file "sp2_max.tdf" line 114, column 6
|
||
-- Equation name is 'STWG0', location is LC024, type is buried.
|
||
STWG0 = TFFE( VCC, _EQ035, VCC, VCC, VCC);
|
||
_EQ035 = _X001 & _X002;
|
||
_X001 = EXP(!CLK_WG & !CT_WG);
|
||
_X002 = EXP( CLK_WG & CT_WG);
|
||
|
||
-- Node name is 'STWG1' from file "sp2_max.tdf" line 114, column 6
|
||
-- Equation name is 'STWG1', location is LC027, type is buried.
|
||
STWG1 = TFFE( STWG0, _EQ036, VCC, VCC, VCC);
|
||
_EQ036 = _X001 & _X002;
|
||
_X001 = EXP(!CLK_WG & !CT_WG);
|
||
_X002 = EXP( CLK_WG & CT_WG);
|
||
|
||
-- Node name is 'TG42_BUF' = ':161' from file "sp2_max.tdf" line 167, column 13
|
||
-- Equation name is 'TG42_BUF', type is output
|
||
TG42_BUF = LCELL(!TG42_IN $ GND);
|
||
|
||
-- Node name is 'TG42_OUT' = ':160' from file "sp2_max.tdf" line 164, column 14
|
||
-- Equation name is 'TG42_OUT', type is output
|
||
TG42_OUT = LCELL( TG42_BUF $ GND);
|
||
|
||
-- Node name is 'WDAT' = 'REG_P2' from file "sp2_max.tdf" line 119, column 7
|
||
-- Equation name is 'WDAT', location is LC008, type is output.
|
||
WDAT = DFFE( _EQ037 $ GND, !CT_WG, VCC, VCC, VCC);
|
||
_EQ037 = !LR_T0 & !LR_T1 & _X026;
|
||
_X026 = EXP( _X027);
|
||
_X027 = EXP( REG_P0 & !REG_P1);
|
||
|
||
-- Node name is 'WGR0' from file "sp2_max.tdf" line 116, column 5
|
||
-- Equation name is 'WGR0', location is LC042, type is buried.
|
||
WGR0 = TFFE( _EQ038, _EQ039, VCC, VCC, VCC);
|
||
_EQ038 = WGR0 & WGR1 & WGR2 & !WGR3
|
||
# !WGR0 & !WGR1 & !WGR2 & WGR3
|
||
# FDAT;
|
||
_EQ039 = _X018;
|
||
_X018 = EXP( _X013 & _X014);
|
||
_X013 = EXP( CT0 & !10K_D0);
|
||
_X014 = EXP( XCT1 & 10K_D0);
|
||
|
||
-- Node name is 'WGR1' from file "sp2_max.tdf" line 116, column 5
|
||
-- Equation name is 'WGR1', location is LC036, type is buried.
|
||
WGR1 = TFFE( _EQ040, _EQ041, VCC, VCC, VCC);
|
||
_EQ040 = FDAT & !WGR0 & !WGR1 & !WGR2 & !WGR3
|
||
# !FDAT & !WGR1 & WGR2 & !WGR3
|
||
# !FDAT & WGR1 & !WGR3
|
||
# FDAT & WGR0;
|
||
_EQ041 = _X018;
|
||
_X018 = EXP( _X013 & _X014);
|
||
_X013 = EXP( CT0 & !10K_D0);
|
||
_X014 = EXP( XCT1 & 10K_D0);
|
||
|
||
-- Node name is 'WGR2' from file "sp2_max.tdf" line 116, column 5
|
||
-- Equation name is 'WGR2', location is LC028, type is buried.
|
||
WGR2 = TFFE( _EQ042, _EQ043, VCC, VCC, VCC);
|
||
_EQ042 = !FDAT & WGR1 & WGR2 & !WGR3
|
||
# FDAT & WGR0 & WGR1
|
||
# !FDAT & !WGR2 & !WGR3;
|
||
_EQ043 = _X018;
|
||
_X018 = EXP( _X013 & _X014);
|
||
_X013 = EXP( CT0 & !10K_D0);
|
||
_X014 = EXP( XCT1 & 10K_D0);
|
||
|
||
-- Node name is 'WGR3' from file "sp2_max.tdf" line 116, column 5
|
||
-- Equation name is 'WGR3', location is LC032, type is buried.
|
||
WGR3 = TFFE( _EQ044, _EQ045, VCC, VCC, VCC);
|
||
_EQ044 = FDAT & WGR0 & WGR1 & WGR2 & WGR3
|
||
# WGR0 & WGR1 & WGR2 & !WGR3
|
||
# !FDAT & WGR1 & WGR2 & !WGR3;
|
||
_EQ045 = _X018;
|
||
_X018 = EXP( _X013 & _X014);
|
||
_X013 = EXP( CT0 & !10K_D0);
|
||
_X014 = EXP( XCT1 & 10K_D0);
|
||
|
||
-- Node name is 'WR_PDOS' = ':198' from file "sp2_max.tdf" line 426, column 13
|
||
-- Equation name is 'WR_PDOS', type is output
|
||
WR_PDOS = DFFE( _EQ046 $ VCC, 10K_CLK, VCC, FDD_C2, VCC);
|
||
_EQ046 = FDD_C0 & !FDD_C1 & !HDD_C0 & !HDD_C1 & !HDD_C2 & !HDD_C3;
|
||
|
||
-- Node name is 'XCT0' from file "sp2_max.tdf" line 94, column 5
|
||
-- Equation name is 'XCT0', location is LC049, type is buried.
|
||
XCT0 = TFFE( VCC, _EQ047, VCC, VCC, VCC);
|
||
_EQ047 = _X003 & _X004;
|
||
_X003 = EXP(!TG42_IN & XCT1);
|
||
_X004 = EXP( TG42_IN & !XCT1);
|
||
|
||
-- Node name is 'XHD_RD' = '~206~1' from file "sp2_max.tdf" line 460, column 27
|
||
-- Equation name is 'XHD_RD', location is LC115, type is output.
|
||
XHD_RD = DFFE( _EQ023 $ VCC, 10K_CLK, VCC, !_EQ024, VCC);
|
||
|
||
-- Node name is 'XHD_RES' = ':204' from file "sp2_max.tdf" line 447, column 27
|
||
-- Equation name is 'XHD_RES', type is output
|
||
XHD_RES = DFFE( PW_GOOD $ GND, SINC_V, EPM_RES, VCC, VCC);
|
||
|
||
-- Node name is 'XHD_WR' = ':205' from file "sp2_max.tdf" line 459, column 27
|
||
-- Equation name is 'XHD_WR', type is output
|
||
XHD_WR = DFFE( _EQ048 $ VCC, 10K_CLK, VCC, !_EQ049, VCC);
|
||
_EQ048 = !FDD_C1 & HDD_C0 & !HDD_C1 & HDD_C2;
|
||
_EQ049 = _X019;
|
||
_X019 = EXP( /CONF_X & HDD_C0);
|
||
|
||
-- Node name is 'XHD1_CS1' = ':207' from file "sp2_max.tdf" line 470, column 20
|
||
-- Equation name is 'XHD1_CS1', type is output
|
||
XHD1_CS1 = DFFE( _EQ050 $ VCC, TG42_IN, VCC, /CONF_X, VCC);
|
||
_EQ050 = /CONF_X & !HDD_C1 & HDD_C2 & !HDD_C3 & _X028 & _X029 & _X030 &
|
||
_X031;
|
||
_X028 = EXP( /CONF_X & _X029 & _X030 & _X032 & _X033);
|
||
_X029 = EXP( FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 &
|
||
HDD_C3);
|
||
_X030 = EXP( _X028 & _X031 & _X032 & _X033);
|
||
_X031 = EXP( FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 &
|
||
!HDD_C3);
|
||
_X032 = EXP( /CONF_X & _X028 & _X029 & _X030 & _X031);
|
||
_X033 = EXP(!FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 &
|
||
!HDD_C3);
|
||
|
||
-- Node name is 'XHD1_CS2' = ':208' from file "sp2_max.tdf" line 471, column 20
|
||
-- Equation name is 'XHD1_CS2', type is output
|
||
XHD1_CS2 = DFFE( _EQ051 $ VCC, TG42_IN, VCC, /CONF_X, VCC);
|
||
_EQ051 = /CONF_X & !HDD_C1 & HDD_C2 & HDD_C3 & _X028 & _X029 & _X030 &
|
||
_X031;
|
||
_X028 = EXP( /CONF_X & _X029 & _X030 & _X032 & _X033);
|
||
_X029 = EXP( FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 &
|
||
HDD_C3);
|
||
_X030 = EXP( _X028 & _X031 & _X032 & _X033);
|
||
_X031 = EXP( FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 &
|
||
!HDD_C3);
|
||
_X032 = EXP( /CONF_X & _X028 & _X029 & _X030 & _X031);
|
||
_X033 = EXP(!FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 &
|
||
!HDD_C3);
|
||
|
||
-- Node name is 'XHD2_CS1' = ':209' from file "sp2_max.tdf" line 475, column 20
|
||
-- Equation name is 'XHD2_CS1', type is output
|
||
XHD2_CS1 = DFFE( _EQ052 $ VCC, TG42_IN, VCC, /CONF_X, VCC);
|
||
_EQ052 = /CONF_X & !HDD_C1 & HDD_C2 & !HDD_C3 & _X029 & _X030 & _X032 &
|
||
_X033;
|
||
_X029 = EXP( FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 &
|
||
HDD_C3);
|
||
_X030 = EXP( _X028 & _X031 & _X032 & _X033);
|
||
_X032 = EXP( /CONF_X & _X028 & _X029 & _X030 & _X031);
|
||
_X033 = EXP(!FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 &
|
||
!HDD_C3);
|
||
_X028 = EXP( /CONF_X & _X029 & _X030 & _X032 & _X033);
|
||
_X031 = EXP( FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 &
|
||
!HDD_C3);
|
||
|
||
-- Node name is 'XHD2_CS2' = ':210' from file "sp2_max.tdf" line 476, column 20
|
||
-- Equation name is 'XHD2_CS2', type is output
|
||
XHD2_CS2 = DFFE( _EQ053 $ VCC, TG42_IN, VCC, /CONF_X, VCC);
|
||
_EQ053 = /CONF_X & !HDD_C1 & HDD_C2 & HDD_C3 & _X029 & _X030 & _X032 &
|
||
_X033;
|
||
_X029 = EXP( FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 &
|
||
HDD_C3);
|
||
_X030 = EXP( _X028 & _X031 & _X032 & _X033);
|
||
_X032 = EXP( /CONF_X & _X028 & _X029 & _X030 & _X031);
|
||
_X033 = EXP(!FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 &
|
||
!HDD_C3);
|
||
_X028 = EXP( /CONF_X & _X029 & _X030 & _X032 & _X033);
|
||
_X031 = EXP( FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 &
|
||
!HDD_C3);
|
||
|
||
-- Node name is '10K_CLK' = ':182' from file "sp2_max.tdf" line 322, column 13
|
||
-- Equation name is '10K_CLK', type is output
|
||
10K_CLK = DFFE( _EQ054 $ !CNF_OFF, TG42_IN, VCC, VCC, VCC);
|
||
_EQ054 = !CNF_OFF & !FDD_C2 & !HDD_C0
|
||
# CNF_OFF & WR_CNF;
|
||
|
||
-- Node name is '10K_D0' = ':183' from file "sp2_max.tdf" line 324, column 12
|
||
-- Equation name is '10K_D0', type is output
|
||
10K_D0 = DFFE( _EQ055 $ GND, 10K_CLK, !_EQ056, !_EQ057, VCC);
|
||
_EQ055 = CNF_OFF & D0
|
||
# !CNF_OFF & 10K_D0;
|
||
_EQ056 = !FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & !HDD_C1 & !HDD_C2 &
|
||
!HDD_C3;
|
||
_EQ057 = _X034;
|
||
_X034 = EXP( /CONF_X & _X035);
|
||
_X035 = EXP( FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & !HDD_C1 & !HDD_C2 &
|
||
!HDD_C3);
|
||
|
||
-- Node name is '/CONF_X' = '/RESET' from file "sp2_max.tdf" line 154, column 12
|
||
-- Equation name is '/CONF_X', location is LC085, type is bidir.
|
||
/CONF_X = OPNDRN(/RESET);
|
||
/RESET = DFFE( _EQ058 $ GND, !AUD, !_EQ059, VCC, VCC);
|
||
_EQ058 = EPM_RES & XHD_RES;
|
||
_EQ059 = !FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 &
|
||
HDD_C3;
|
||
|
||
-- Node name is '/WG_RD' = ':200' from file "sp2_max.tdf" line 428, column 12
|
||
-- Equation name is '/WG_RD', type is output
|
||
/WG_RD = DFFE( _EQ060 $ VCC, 10K_CLK, VCC, FDD_C2, VCC);
|
||
_EQ060 = !FDD_C0 & FDD_C1 & !HDD_C0 & !HDD_C1 & !HDD_C2 & !HDD_C3;
|
||
|
||
-- Node name is '/WG_WR' = ':199' from file "sp2_max.tdf" line 427, column 12
|
||
-- Equation name is '/WG_WR', type is output
|
||
/WG_WR = DFFE( _EQ061 $ VCC, 10K_CLK, VCC, FDD_C2, VCC);
|
||
_EQ061 = !FDD_C0 & !FDD_C1 & !HDD_C0 & !HDD_C1 & !HDD_C2 & !HDD_C3;
|
||
|
||
-- Node name is ':180' from file "sp2_max.tdf" line 309, column 28
|
||
-- Equation name is '_LC022', type is buried
|
||
_LC022 = DFFE( _EQ062 $ GND, _EQ063, VCC, VCC, VCC);
|
||
_EQ062 = _X016;
|
||
_X016 = EXP( _X012 & _X017);
|
||
_X012 = EXP( _X015 & _X016);
|
||
_X017 = EXP( RDAT & _X013 & _X014);
|
||
_X015 = EXP(!RDAT & _X013 & _X014);
|
||
_X013 = EXP( CT0 & !10K_D0);
|
||
_X014 = EXP( XCT1 & 10K_D0);
|
||
_EQ063 = _X018;
|
||
_X018 = EXP( _X013 & _X014);
|
||
_X013 = EXP( CT0 & !10K_D0);
|
||
_X014 = EXP( XCT1 & 10K_D0);
|
||
|
||
|
||
|
||
-- Shareable expanders that are duplicated in multiple LABs:
|
||
-- _X005 occurs in LABs C, G
|
||
-- _X013 occurs in LABs B, C
|
||
-- _X014 occurs in LABs B, C
|
||
-- _X018 occurs in LABs B, C
|
||
-- _X019 occurs in LABs E, H
|
||
|
||
|
||
|
||
|
||
Project Information c:\sprinter\src\altera\max\sp2_max.rpt
|
||
|
||
** TIMING ASSIGNMENTS **
|
||
|
||
|
||
INFORMATION: One or more paths have been found between register controlled by different clocks--can't calculate fmax for those paths
|
||
|
||
User Actual
|
||
Type Location Assignment Value Status Critical Path
|
||
|
||
fmax <default> 100.00 MHz 43.47 MHz Failed RSTB to register STWG2.Q to register STWG0.Q
|
||
fmax <default> 100.00 MHz 43.47 MHz Failed STE to register STWG2.Q to register STWG0.Q
|
||
fmax <default> 100.00 MHz 27.02 MHz Failed TG42_IN to register SINC_HT.Q to register /RESET.Q
|
||
fmax <default> 100.00 MHz 43.47 MHz Failed WSTB to register STWG2.Q to register STWG0.Q
|
||
|
||
|
||
Project Information c:\sprinter\src\altera\max\sp2_max.rpt
|
||
|
||
** COMPILATION SETTINGS & TIMES **
|
||
|
||
Processing Menu Commands
|
||
------------------------
|
||
|
||
Design Doctor = off
|
||
|
||
Logic Synthesis:
|
||
|
||
Synthesis Type Used = Standard
|
||
|
||
Default Synthesis Style = NORMAL
|
||
|
||
Logic option settings in 'NORMAL' style for 'MAX7000S' family
|
||
|
||
DECOMPOSE_GATES = on
|
||
DUPLICATE_LOGIC_EXTRACTION = on
|
||
MINIMIZATION = full
|
||
MULTI_LEVEL_FACTORING = on
|
||
NOT_GATE_PUSH_BACK = on
|
||
PARALLEL_EXPANDERS = off
|
||
REDUCE_LOGIC = on
|
||
REFACTORIZATION = on
|
||
REGISTER_OPTIMIZATION = on
|
||
RESYNTHESIZE_NETWORK = on
|
||
SLOW_SLEW_RATE = off
|
||
SOFT_BUFFER_INSERTION = on
|
||
SUBFACTOR_EXTRACTION = on
|
||
TURBO_BIT = on
|
||
XOR_SYNTHESIS = on
|
||
IGNORE_SOFT_BUFFERS = off
|
||
USE_LPM_FOR_AHDL_OPERATORS = off
|
||
|
||
Other logic synthesis settings:
|
||
|
||
Automatic Global Clock = off
|
||
Automatic Global Clear = off
|
||
Automatic Global Preset = on
|
||
Automatic Global Output Enable = on
|
||
Automatic Fast I/O = off
|
||
Automatic Register Packing = off
|
||
Automatic Open-Drain Pins = on
|
||
Automatic Implement in EAB = off
|
||
One-Hot State Machine Encoding = off
|
||
Optimize = 5
|
||
|
||
Default Timing Specifications:
|
||
|
||
fmax = 100MHz
|
||
|
||
Cut All Bidir Feedback Timing Paths = on
|
||
Cut All Clear & Preset Timing Paths = on
|
||
|
||
Ignore Timing Assignments = off
|
||
|
||
Functional SNF Extractor = off
|
||
|
||
Linked SNF Extractor = off
|
||
Timing SNF Extractor = on
|
||
Optimize Timing SNF = off
|
||
Generate AHDL TDO File = off
|
||
Fitter Settings = ADVANCED
|
||
Smart Recompile = off
|
||
Total Recompile = off
|
||
|
||
Interfaces Menu Commands
|
||
------------------------
|
||
|
||
EDIF Netlist Writer = off
|
||
Verilog Netlist Writer = off
|
||
VHDL Netlist Writer = off
|
||
|
||
Compilation Times
|
||
-----------------
|
||
|
||
Compiler Netlist Extractor 00:00:00
|
||
Database Builder 00:00:00
|
||
Logic Synthesizer 00:00:00
|
||
Partitioner 00:00:00
|
||
Fitter 00:00:01
|
||
Timing SNF Extractor 00:00:00
|
||
Assembler 00:00:00
|
||
-------------------------- --------
|
||
Total Time 00:00:01
|
||
|
||
|
||
Memory Allocated
|
||
-----------------
|
||
|
||
Peak memory allocated during compilation = 3,347K
|