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108 lines
8.5 KiB
Plaintext
108 lines
8.5 KiB
Plaintext
-- Copyright (C) 1991-2013 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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--
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-- This is a Quartus II output file. It is for reporting purposes only, and is
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-- not intended for use as a Quartus II input file. This file cannot be used
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-- to make Quartus II pin assignments - for instructions on how to make pin
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-- assignments, please see Quartus II help.
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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-- NC : No Connect. This pin has no internal connection to the device.
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-- DNU : Do Not Use. This pin MUST NOT be connected.
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-- VCC : Dedicated power pin, which MUST be connected to VCC.
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-- VCCIO : Dedicated power pin, which MUST be connected to VCC
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-- of its bank.
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-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
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-- It can also be used to report unused dedicated pins. The connection
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-- on the board for unused dedicated pins depends on whether this will
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-- be used in a future design. One example is device migration. When
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-- using device migration, refer to the device pin-tables. If it is a
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-- GND pin in the pin table or if it will not be used in a future design
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-- for another purpose the it MUST be connected to GND. If it is an unused
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-- dedicated pin, then it can be connected to a valid signal on the board
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-- (low, high, or toggling) if that signal is required for a different
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-- revision of the design.
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-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
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-- This pin should be connected to GND. It may also be connected to a
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-- valid signal on the board (low, high, or toggling) if that signal
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-- is required for a different revision of the design.
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-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
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-- or leave it unconnected.
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-- RESERVED : Unused I/O pin, which MUST be left unconnected.
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-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
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-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
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-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
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-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
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-- NON_MIGRATABLE: This pin cannot be migrated.
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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-- Pin directions (input, output or bidir) are based on device operating in user mode.
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---------------------------------------------------------------------------------
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Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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CHIP "OrionCOM-AY" ASSIGNED TO AN: EPM7064STC44-7
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Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
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-------------------------------------------------------------------------------------------------------------
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TDI : 1 : input : TTL : : : Y
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a[0] : 2 : input : TTL : : : Y
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a[1] : 3 : input : TTL : : : Y
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GND : 4 : gnd : : : :
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a[2] : 5 : input : TTL : : : Y
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a[3] : 6 : input : TTL : : : Y
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TMS : 7 : input : TTL : : : Y
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a[4] : 8 : input : TTL : : : Y
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VCC : 9 : power : : : :
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a[5] : 10 : input : TTL : : : Y
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a[6] : 11 : input : TTL : : : Y
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a[7] : 12 : input : TTL : : : Y
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irq4 : 13 : output : TTL : : : Y
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irq3 : 14 : output : TTL : : : Y
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a[8] : 15 : input : TTL : : : Y
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GND : 16 : gnd : : : :
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VCC : 17 : power : : : :
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a[9] : 18 : input : TTL : : : Y
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rd_n : 19 : input : TTL : : : Y
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wr_n : 20 : input : TTL : : : Y
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iorq_n : 21 : input : TTL : : : Y
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wait_n : 22 : input : TTL : : : Y
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m1_n : 23 : input : TTL : : : Y
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GND : 24 : gnd : : : :
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cs_vi_n : 25 : output : TTL : : : Y
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TCK : 26 : input : TTL : : : Y
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clk1 : 27 : output : TTL : : : Y
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w1 : 28 : output : TTL : : : Y
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VCC : 29 : power : : : :
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cs_vv2_n : 30 : output : TTL : : : Y
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rdy2 : 31 : input : TTL : : : Y
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TDO : 32 : output : TTL : : : Y
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debug : 33 : output : TTL : : : Y
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reset : 34 : output : TTL : : : Y
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cs_vv1_n : 35 : output : TTL : : : Y
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GND : 36 : gnd : : : :
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clk : 37 : input : TTL : : : Y
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rdy1 : 38 : input : TTL : : : Y
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reset_n : 39 : input : TTL : : : Y
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GND+ : 40 : : : : :
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VCC : 41 : power : : : :
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bc1 : 42 : output : TTL : : : Y
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bdir : 43 : output : TTL : : : Y
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clk2 : 44 : output : TTL : : : Y
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