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29 lines
611 B
Systemverilog
29 lines
611 B
Systemverilog
/*
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* Делитель частоты для формирования сигнала опроса джойстика Sega
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*/
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module ClockGenerator (
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input wire clk, // Input clock
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input wire reset,
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output reg sj_clk // Clock for sega joystick
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);
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reg [6:0] clk_ctr;
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localparam [6:0] divisor = 120;
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//assign sj_clk = clk_ctr[7];
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always_ff @ (posedge clk, posedge reset)
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if (reset) begin
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clk_ctr <= 7'h00;
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sj_clk <= 1'b0;
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end
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else begin
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if (clk_ctr == divisor) begin
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clk_ctr <= 7'h00;
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sj_clk <= !sj_clk;
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end
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else clk_ctr <= clk_ctr + 1'b1;
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end
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endmodule
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