mirror of
https://github.com/romychs/SprinterJoy.git
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131 lines
2.5 KiB
Systemverilog
131 lines
2.5 KiB
Systemverilog
/*
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* Модуль опроса джойстиков
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*/
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module SegaJoy(
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input reg clk,
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input wire reset,
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output reg sel1,
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output reg sel2,
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input wire [5:0] sj1,
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input wire [5:0] sj2,
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output reg [11:0] status1,
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output reg [11:0] status2,
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output reg [1:0] sj_type1,
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output reg [1:0] sj_type2
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);
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localparam [7:0] divisor = 180;
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reg [7:0] cycle;
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reg [5:0] s0;
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reg [5:0] s1;
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reg [5:0] s4;
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reg [5:0] s5;
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reg [5:0] s6;
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reg [11:0] combo;
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always_ff @ (posedge clk, posedge reset)
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if (reset) begin
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cycle <= 8'h00;
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sel1 <= 1'b0;
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sel2 <= 1'b0;
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status1 <= 12'h000;
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status2 <= 12'h000;
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end else begin
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case (cycle)
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// JOY 1
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0: sel1 <= 0;
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1: s0 <= sj1;
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2: sel1 <= 1;
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3: s1 <= sj1;
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4: sel1 <= 0;
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//8: s2 <= sj1;
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6: sel1 <= 1;
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//11: s3 <= sj1;
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8: sel1 <= 0;
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9: s4 <= sj1;
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10: sel1 <= 1;
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11: s5 <= sj1;
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12: sel1 <= 0;
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13: s6 <= sj1;
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14: begin
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//sj_dbg <= s4;
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combo <= ~({s5[3:0], s0[5:4], s1});
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if (s4[1:0] == 2'b00 && s6[3:0] == 4'b1111) sj_type1 <= 2'b10;
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else if (s6[3:2] == 2'b00) sj_type1 <= 2'b01;
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else sj_type1 <= 2'b00;
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end
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15:
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/* Все значения получены, фиксируем результаты */
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case (sj_type1)
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2'b10: status1 <= combo;
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2'b01: status1 <= {4'b0000, combo[7:0]};
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default:
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status1 <= {6'b000000, combo[5:0]};
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endcase
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// JOY 2
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16: sel2 <= 0;
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17: s0 <= sj2;
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18: sel2 <= 1;
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19: s1 <= sj2;
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20: sel2 <= 0;
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//8: s2 <= sj2;
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22: sel2 <= 1;
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//11: s3 <= sj2;
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24: sel2 <= 0;
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25: s4 <= sj2;
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26: sel2 <= 1;
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27: s5 <= sj2;
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28: sel2 <= 0;
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29: s6 <= sj2;
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30: begin
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//sj_dbg <= s4;
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combo <= ~({s5[3:0], s0[5:4], s1});
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if (s4[1:0] == 2'b00 && s6[3:0] == 4'b1111) sj_type2 <= 2'b10;
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else if (s6[3:2] == 2'b00) sj_type2 <= 2'b01;
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else sj_type2 <= 2'b00;
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end
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31:
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/* Все значения получены, фиксируем результаты */
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case (sj_type2)
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2'b10: status2 <= combo;
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2'b01: status2 <= {4'b0000, combo[7:0]};
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default:
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status2 <= {6'b000000, combo[5:0]};
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endcase
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endcase
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if (cycle == divisor) cycle <= 8'hff;
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else cycle <= cycle + 1'b1;
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end
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endmodule
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