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fix potential jumping issue with HV sync

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marqs 2024-05-25 11:15:02 +03:00
parent 353437ab87
commit 88026cafa2
1 changed files with 1 additions and 1 deletions
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rtl/tvp7002_frontend.v
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@ -201,7 +201,7 @@ always @(posedge PCLK_i) begin
// vsync leading edge processing per quadrant
if (VS_i_np_prev & ~VS_i_np) begin
if (h_cnt_ref < even_min_thold) begin
if ((HS_i_prev & ~HS_i) | (h_cnt_ref < even_min_thold)) begin
fid_next <= FID_ODD;
fid_next_ctr <= 2'h1;
end else if ((h_cnt_ref > even_max_thold) | ~interlace_flag) begin