RomanRom2/ossc
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first version booting from flash

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marqs committed 2025-03-26 23:30:42 +02:00
1 parent 429b0f7201
commit e74da07802
53 files changed
+5048 -4961
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ossc.qsf
+12 -9
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@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8
set_global_assignment -name TOP_LEVEL_ENTITY ossc
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03 MAY 17, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.1 Lite Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "24.1std.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -172,9 +172,8 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name INI_VARS "FIOMGR_ENABLE_SPI_TIMING=ON"
set_global_assignment -name SEARCH_PATH rtl
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
@@ -231,6 +230,12 @@ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[7]
set_global_assignment -name VERILOG_FILE rtl/videogen.v
set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v
set_global_assignment -name VERILOG_FILE rtl/ossc.v
@@ -249,10 +254,8 @@ set_global_assignment -name SDC_FILE ossc.sdc
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
set_global_assignment -name QIP_FILE rtl/char_array.qip
set_global_assignment -name SEARCH_PATH rtl
set_global_assignment -name SEARCH_PATH software/sys_controller/mem_init/
set_global_assignment -name SEARCH_PATH ip/ibex_qsys/rtl_extra
set_global_assignment -name VERILOG_MACRO "SYNTHESIS=<None>"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top