RomanRom2/ossc
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mirror of https://github.com/marqs85/ossc synced 2026-11-01 20:57:10 +03:00
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first version booting from flash

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marqs committed 2025-03-26 23:30:42 +02:00
1 parent 429b0f7201
commit e74da07802
53 files changed
+5048 -4961
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software/sys_controller_bsp/HAL/src/alt_busy_sleep.c
+23 -1
View File
@@ -49,7 +49,16 @@
#include "priv/alt_busy_sleep.h"
unsigned int alt_busy_sleep (unsigned int us)
#define TIMER_BASED_SLEEP
#ifdef TIMER_BASED_SLEEP
#include "altera_avalon_timer.h"
#include "sys/alt_timestamp.h"
#endif
unsigned int __attribute__((noinline, flatten, __section__(".text_bram"))) alt_busy_sleep (unsigned int us)
{
/*
* Only delay if ALT_SIM_OPTIMIZE is not defined; i.e., if software
@@ -57,6 +66,18 @@ unsigned int alt_busy_sleep (unsigned int us)
* skipped to speed up simulation.
*/
#ifndef ALT_SIM_OPTIMIZE
/*unsigned long i, loops;
// 1 loop >= 7 cyc
loops = ((ALT_CPU_FREQ/1000000)*us)/120;
for (i=7; i<loops; i++)
asm volatile ("nop");*/
#ifdef TIMER_BASED_SLEEP
alt_timestamp_type start_ts = alt_timestamp();
while (alt_timestamp() < start_ts + us*(TIMER_0_FREQ/1000000)) {}
#else
unsigned long i, loops;
// 1 loop >= 7 cyc
@@ -64,6 +85,7 @@ unsigned int alt_busy_sleep (unsigned int us)
for (i=7; i<loops; i++)
asm volatile ("nop");
#endif
#endif /* #ifndef ALT_SIM_OPTIMIZE */
return 0;
}
software/sys_controller_bsp/HAL/src/alt_load.c
+19 -9
View File
@@ -47,13 +47,15 @@
* Specifying __attribute__((section(".data"))) will force these
* in .data. (CASE:258384.)
*/
extern alt_u32 __flash_text_bram_start __attribute__((section(".data")));
extern alt_u32 __ram_text_start __attribute__((section(".data")));
extern alt_u32 __ram_text_end __attribute__((section(".data")));
extern alt_u32 __flash_rwdata_start __attribute__((section(".data")));
extern alt_u32 __ram_rwdata_start __attribute__((section(".data")));
extern alt_u32 __ram_rwdata_end __attribute__((section(".data")));
extern alt_u32 __flash_rodata_start __attribute__((section(".data")));
/*extern alt_u32 __flash_rodata_start __attribute__((section(".data")));
extern alt_u32 __ram_rodata_start __attribute__((section(".data")));
extern alt_u32 __ram_rodata_end __attribute__((section(".data")));
extern alt_u32 __ram_rodata_end __attribute__((section(".data")));*/
extern alt_u32 __flash_exceptions_start __attribute__((section(".data")));
extern alt_u32 __ram_exceptions_start __attribute__((section(".data")));
extern alt_u32 __ram_exceptions_end __attribute__((section(".data")));
@@ -66,6 +68,14 @@ extern alt_u32 __ram_exceptions_end __attribute__((section(".data")));
void alt_load (void)
{
/*
* Copy the .text_bram section.
*/
alt_load_section (&__flash_text_bram_start,
&__ram_text_start,
&__ram_text_end);
/*
* Copy the .rwdata section.
*/
@@ -78,22 +88,22 @@ void alt_load (void)
* Copy the exception handler.
*/
alt_load_section (&__flash_exceptions_start,
/*alt_load_section (&__flash_exceptions_start,
&__ram_exceptions_start,
&__ram_exceptions_end);
&__ram_exceptions_end);*/
/*
* Copy the .rodata section.
*/
alt_load_section (&__flash_rodata_start,
/*alt_load_section (&__flash_rodata_start,
&__ram_rodata_start,
&__ram_rodata_end);
&__ram_rodata_end);*/
/*
* Now ensure that the caches are in synch.
*/
alt_dcache_flush_all();
alt_icache_flush_all();
/*alt_dcache_flush_all();
alt_icache_flush_all();*/
}