marqs
ac0181a698
update to Quartus 23.1
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* add patch file to enforce LE use on small memory blocks
* utilize M9K freed from epcq_controller for restoring profile export function
2024-07-15 12:40:44 +03:00
marqs
10f1afd79c
tweak activity detection to fix auto input
2024-06-11 23:08:00 +03:00
marqs
83c33c41b9
restore original test pattern
2023-10-24 00:19:46 +03:00
marqs
31851f372d
restore hybrid scanlines and reverse LPF functions
2023-08-07 18:18:53 +03:00
marqs
2e1fdab16b
add support for v1.8 PCBs
2023-08-05 22:41:58 +03:00
marqs
ab6bd9fc8a
calculate hsync width on FPGA instead of reading TVP7002
2023-05-28 17:06:07 +03:00
marqs
df643ec742
improve TVP7002 frontend sync detection
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Store csync leading edge position so that field change timing can be calculated accurately upon VSYNC detection
2023-03-11 12:32:26 +02:00
marqs
804642bd98
integrate RTL from ossc_pro project
2023-02-28 19:39:59 +02:00
marqs
76da437125
integrate new tvp7002 frontend
2023-01-31 20:51:06 +02:00
marqs
9c5e7b5b83
advanced OSD implementation
2020-10-05 23:05:43 +03:00
marqs
0c55cc03bb
use LEDs for debug in latency tester mode
2020-02-09 21:35:50 +02:00
marqs
85c295c5e2
make pll_reconfig more robust
2019-10-12 22:56:10 +03:00
marqs
3a12592c53
fix linebuf read address timing bottleneck
2019-10-07 01:25:33 +03:00
marqs
9d496383c3
optimize clock network
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* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-06 23:54:32 +03:00
marqs
6266976114
first OSD implementation
2019-10-03 02:03:43 +03:00
marqs
9e81fb5922
Scanline updates and fixes
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* Enable overlay pattern customization
* Fix non-alternating mode with line4x interlace sources
* Add alternate interval option for pre-linedoubled sources
2019-03-23 00:09:46 +02:00
marqs
7914a2ee83
clean up and update README
2018-10-08 00:37:42 +03:00
marqs
4676cbd2f0
integrate zero-riscy
2018-10-06 13:19:12 +03:00
marqs
37650ca22b
misc improvements
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* add character LCD backlight timeout option
* increase h.mask range
* show accurate (fpga-calculated) timings on infoscreen
2018-03-28 20:09:40 +03:00
borti4938
45ca4e9268
undo changes as suggested in pull-request #21 comments
2018-03-07 09:43:37 +01:00
borti4938
5922e64f55
registered outputs to HDMI-TX after final mux
2018-03-06 13:08:47 +01:00
marqs
a24d6b0e3a
Update latency tester
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* Enable operation with all sources
* Measure strobe length on low-persistence displays
2017-10-28 12:10:54 +03:00
marqs
1bf279b2a7
Initial latency tester implementation
2017-10-22 22:45:29 +03:00
marqs
4f36278cb7
Sync processing rewritten and some issues fixed
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* add 480i/576i line3x/4x
* clean up RTL and SDC
* update AVI infoframe properly
* add HDMI IT content option
2017-05-18 23:36:37 +03:00
marqs
01b5fe20ee
Sync and masking improvements
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* detect VSM=1 properly
* increase mask brightness
* add L2 optimized modes
* fix internal vsync alignment
2017-05-18 23:36:37 +03:00
marqs
2c934c9dd0
Fix line3x 4:3 mode and VGA interlace detection
2017-02-09 23:14:24 +02:00
marqs
3b19b2843c
Preliminary Line5x implementation
2017-01-29 13:02:12 +02:00
marqs
d41c7522a0
Misc updates
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* Fix mask placement and make its brightness adjustable
* Line4x
2017-01-24 00:18:15 +02:00
marqs
434186d64e
Improve lo-res mode processing features
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* workaround for phase shift issue on optimized modes
* add hscale option for 256x240 opt Line3x mode
* distribute video modes to groups and allow passthru for all modes
2017-01-23 00:56:17 +02:00
marqs
d77c293b70
* Clean up some FPGA code
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* Wrap sampling phase setting
* Enable hal.enable_lightweight_device_driver_api to reduce CPU code size
2016-12-31 14:18:21 +02:00
marqs
f55e9a877e
SD SPI implementation finished
2016-10-21 01:19:53 +03:00
marqs
71d60144e8
Timer and SPI added.
2016-10-16 12:53:54 +03:00
marqs
827df7930f
* L3 optimized mode scanlines fixed
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* Advanced timing tweaker implemented
2016-08-16 22:45:23 +03:00
marqs
c8b542b917
* 480p/576p line2x
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* 480i/576i passthrough
* alternating scanlines for interlaced material
2016-07-09 23:12:35 +03:00
marqs
c83653c880
Release 0.69
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* Improved remote control handling code
* Fixed occasional mode change loop when switching to a non-interlace mode utilizing odd-field sync signal
* Fixed randomly missing blue channel at power-on when using DVI output mode
* Added H-PLL coast options
* Finer tuning range for scanline strength and mask
2016-04-15 22:05:53 +03:00
marqs
f502b2e46c
Release 0.67.
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- Code cleanup
- Some project files added
- PAL linetriple added
- FPGA PLL parameters optimized
- Reduced jitter on low video clock sources
2016-03-27 23:09:31 +03:00
marqs
388c464f63
Initial public release (FW 0.64)
2016-02-23 01:03:50 +02:00
