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Merge pull request #2034 from JoakimLarsson/cpu20

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Force CPU-20
This commit is contained in:
Joakim Larsson Edström 2017-02-01 15:14:39 +01:00 committed by GitHub
commit 41d1224bd7
4 changed files with 422 additions and 72 deletions
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256
src/devices/bus/vme/vme_fccpu20.cpp
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@ -117,7 +117,7 @@
* || || | | +-----------------------+ | * || || | | +-----------------------+ |
* ||||--|| +---+ (XTAL) | * ||||--|| +---+ (XTAL) |
* ||||--||------------------------------------------------------------+ * ||||--||------------------------------------------------------------+
* || * || NOTE: Variants also available with 2MB and/or DRAM
* *
* History of Force Computers * History of Force Computers
*--------------------------- *---------------------------
@ -166,13 +166,21 @@
* *
*--------------------------------------------------------------------------- *---------------------------------------------------------------------------
* TODO: * TODO:
* - Find accurate documentation and adjust memory map * - Find accurate documentation and adjust memory map for Y boards
* - Add PCB layout
* - Improve 68561 UART * - Improve 68561 UART
* - Improve hookup of 68230 PIT * - Improve hookup of 68230 PIT
* - Add variants of boards in the CPU-20 and CPU-21 family * - ABORT switch
* - Enable/Disable VME interrupts
* - Interrupts: Timer, ACFAIL, SYSFAIL and VMX irq
* - Memory config
* - Board ID
* - Add FGA, DUSCC devices and CPU-22 variants * - Add FGA, DUSCC devices and CPU-22 variants
* * - Add FLME bus for memory expansions and optional extra MPCC
* - Add VMX bus on the P2 connector
* - Enable FPU
* - Add user EPROM sockets as cartridge interface enabling softlists
* NOT PLANNED:
* - VME bus arbiter as MAME always gets the bus
****************************************************************************/ ****************************************************************************/
#include "emu.h" #include "emu.h"
#include "cpu/m68000/m68000.h" #include "cpu/m68000/m68000.h"
@ -212,23 +220,29 @@
//************************************************************************** //**************************************************************************
const device_type VME_FCCPU20 = &device_creator<vme_fccpu20_card_device>; const device_type VME_FCCPU20 = &device_creator<vme_fccpu20_card_device>;
const device_type VME_FCCPU21S = &device_creator<vme_fccpu21s_card_device>;
const device_type VME_FCCPU21 = &device_creator<vme_fccpu21_card_device>;
const device_type VME_FCCPU21A = &device_creator<vme_fccpu21a_card_device>;
const device_type VME_FCCPU21YA = &device_creator<vme_fccpu21ya_card_device>;
const device_type VME_FCCPU21B = &device_creator<vme_fccpu21b_card_device>;
const device_type VME_FCCPU21YB = &device_creator<vme_fccpu21yb_card_device>;
#define CPU_CLOCK XTAL_20MHz /* HCJ */ #define CLOCK50 XTAL_50MHz /* HCJ */
#define DUSCC_CLOCK XTAL_14_7456MHz /* HCJ */ #define CLOCK40 XTAL_40MHz /* HCJ */
#define CLOCK32 XTAL_32MHz /* HCJ */
static ADDRESS_MAP_START (cpu20_mem, AS_PROGRAM, 32, vme_fccpu20_card_device) static ADDRESS_MAP_START (cpu20_mem, AS_PROGRAM, 32, vme_fccpu20_device)
ADDRESS_MAP_UNMAP_HIGH ADDRESS_MAP_UNMAP_HIGH
AM_RANGE (0x00000000, 0x00000007) AM_ROM AM_READ (bootvect_r) /* ROM mirror just during reset */ AM_RANGE (0x00000000, 0x00000007) AM_ROM AM_READ (bootvect_r) /* ROM mirror just during reset */
AM_RANGE (0x00000000, 0x00000007) AM_RAM AM_WRITE (bootvect_w) /* After first write we act as RAM */ AM_RANGE (0x00000000, 0x00000007) AM_RAM AM_WRITE (bootvect_w) /* After first write we act as RAM */
AM_RANGE (0x00000008, 0x003fffff) AM_RAM /* RAM installed in machine start */ AM_RANGE (0x00000008, 0x0007ffff) AM_RAM /* Local SRAM */
AM_RANGE (0xff040000, 0xff04ffff) AM_RAM /* RAM installed in machine start */ AM_RANGE (0x00080000, 0x000fffff) AM_RAM /* SRAM-22 installed */
AM_RANGE (0xff040000, 0xff04ffff) AM_RAM
AM_RANGE (0xff000000, 0xff00ffff) AM_ROM AM_REGION("roms", 0x0000) AM_RANGE (0xff000000, 0xff00ffff) AM_ROM AM_REGION("roms", 0x0000)
AM_RANGE (0xff800000, 0xff80001f) AM_DEVREADWRITE8("mpcc", mpcc68561_device, read, write, 0xffffffff) AM_RANGE (0xff800000, 0xff80001f) AM_DEVREADWRITE8("mpcc", mpcc68561_device, read, write, 0xffffffff)
AM_RANGE (0xff800200, 0xff80021f) AM_DEVREADWRITE8("mpcc2", mpcc68561_device, read, write, 0xffffffff) AM_RANGE (0xff800200, 0xff80021f) AM_DEVREADWRITE8("mpcc2", mpcc68561_device, read, write, 0xffffffff)
// AM_RANGE (0xff800200, 0xff8003ff) AM_DEVREADWRITE8("pit2", pit68230_device, read, write, 0xff00ff00)
AM_RANGE (0xff800600, 0xff80061f) AM_DEVREADWRITE8("mpcc3", mpcc68561_device, read, write, 0xffffffff) AM_RANGE (0xff800600, 0xff80061f) AM_DEVREADWRITE8("mpcc3", mpcc68561_device, read, write, 0xffffffff)
AM_RANGE (0xff800800, 0xff80080f) AM_DEVREADWRITE8("bim", bim68153_device, read, write, 0xff00ff00) AM_RANGE (0xff800800, 0xff80080f) AM_DEVREADWRITE8("bim", bim68153_device, read, write, 0xff00ff00)
// AM_RANGE (0xff800a00, 0xff800a0f) AM_DEVREADWRITE8("rtc", rtc_device, read, write, 0x00ff00ff)
AM_RANGE (0xff800c00, 0xff800dff) AM_DEVREADWRITE8("pit", pit68230_device, read, write, 0xffffffff) AM_RANGE (0xff800c00, 0xff800dff) AM_DEVREADWRITE8("pit", pit68230_device, read, write, 0xffffffff)
ADDRESS_MAP_END ADDRESS_MAP_END
@ -237,20 +251,20 @@ ADDRESS_MAP_END
*/ */
static MACHINE_CONFIG_FRAGMENT (fccpu20) static MACHINE_CONFIG_FRAGMENT (fccpu20)
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD ("maincpu", M68020, XTAL_16MHz) /* Crytstal not verified */ MCFG_CPU_ADD ("maincpu", M68020, CLOCK50 / 3) /* Crytstal verified from picture HCI */
MCFG_CPU_PROGRAM_MAP (cpu20_mem) MCFG_CPU_PROGRAM_MAP (cpu20_mem)
MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("bim", bim68153_device, iack) MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("bim", bim68153_device, iack)
/* PIT Parallel Interface and Timer device, assumed strapped for on board clock */ /* PIT Parallel Interface and Timer device, assumed strapped for on board clock */
MCFG_DEVICE_ADD ("pit", PIT68230, XTAL_32MHz / 4) /* Crystal not verified */ MCFG_DEVICE_ADD ("pit", PIT68230, CLOCK32 / 4) /* Crystal not verified */
MCFG_PIT68230_PA_INPUT_CB(READ8(vme_fccpu20_card_device, pita_r)) MCFG_PIT68230_PA_INPUT_CB(READ8(vme_fccpu20_device, pita_r))
MCFG_PIT68230_PB_INPUT_CB(READ8(vme_fccpu20_card_device, pitb_r)) MCFG_PIT68230_PB_INPUT_CB(READ8(vme_fccpu20_device, pitb_r))
MCFG_PIT68230_PC_INPUT_CB(READ8(vme_fccpu20_card_device, pitc_r)) MCFG_PIT68230_PC_INPUT_CB(READ8(vme_fccpu20_device, pitc_r))
MCFG_PIT68230_TIMER_IRQ_CB(DEVWRITELINE("bim", bim68153_device, int2_w)) MCFG_PIT68230_TIMER_IRQ_CB(DEVWRITELINE("bim", bim68153_device, int2_w))
/* BIM */ /* BIM */
MCFG_MC68153_ADD("bim", XTAL_32MHz / 8) MCFG_MC68153_ADD("bim", CLOCK32 / 8)
MCFG_BIM68153_OUT_INT_CB(WRITELINE(vme_fccpu20_card_device, bim_irq_callback)) MCFG_BIM68153_OUT_INT_CB(WRITELINE(vme_fccpu20_device, bim_irq_callback))
/*INT0 - Abort switch */ /*INT0 - Abort switch */
/*INT1 - MPCC@8.064 MHz aswell */ /*INT1 - MPCC@8.064 MHz aswell */
/*INT2 - PI/T timer */ /*INT2 - PI/T timer */
@ -261,20 +275,22 @@ static MACHINE_CONFIG_FRAGMENT (fccpu20)
#define RS232P2_TAG "rs232p2" #define RS232P2_TAG "rs232p2"
#define RS232P3_TAG "rs232p3" #define RS232P3_TAG "rs232p3"
// MPCC // MPCC
MCFG_MPCC68561_ADD ("mpcc", XTAL_32MHz / 4, 0, 0) MCFG_MPCC68561_ADD ("mpcc", CLOCK32 / 4, 0, 0)
MCFG_MPCC_OUT_TXD_CB(DEVWRITELINE(RS232P1_TAG, rs232_port_device, write_txd)) MCFG_MPCC_OUT_TXD_CB(DEVWRITELINE(RS232P1_TAG, rs232_port_device, write_txd))
MCFG_MPCC_OUT_DTR_CB(DEVWRITELINE(RS232P1_TAG, rs232_port_device, write_dtr)) MCFG_MPCC_OUT_DTR_CB(DEVWRITELINE(RS232P1_TAG, rs232_port_device, write_dtr))
MCFG_MPCC_OUT_RTS_CB(DEVWRITELINE(RS232P1_TAG, rs232_port_device, write_rts)) MCFG_MPCC_OUT_RTS_CB(DEVWRITELINE(RS232P1_TAG, rs232_port_device, write_rts))
MCFG_MPCC_OUT_INT_CB(DEVWRITELINE("bim", bim68153_device, int1_w)) MCFG_MPCC_OUT_INT_CB(DEVWRITELINE("bim", bim68153_device, int1_w))
/* Additional MPCC sits on slave boards like SRAM-22 */
/* Additional MPCC sits on FLME boards like SRAM-22,
TODO: install MPCC2/MPCC3 in FLME slot device */
// MPCC2 // MPCC2
MCFG_MPCC68561_ADD ("mpcc2", XTAL_32MHz / 4, 0, 0) MCFG_MPCC68561_ADD ("mpcc2", CLOCK32 / 4, 0, 0)
MCFG_MPCC_OUT_TXD_CB(DEVWRITELINE(RS232P2_TAG, rs232_port_device, write_txd)) MCFG_MPCC_OUT_TXD_CB(DEVWRITELINE(RS232P2_TAG, rs232_port_device, write_txd))
MCFG_MPCC_OUT_DTR_CB(DEVWRITELINE(RS232P2_TAG, rs232_port_device, write_dtr)) MCFG_MPCC_OUT_DTR_CB(DEVWRITELINE(RS232P2_TAG, rs232_port_device, write_dtr))
MCFG_MPCC_OUT_RTS_CB(DEVWRITELINE(RS232P2_TAG, rs232_port_device, write_rts)) MCFG_MPCC_OUT_RTS_CB(DEVWRITELINE(RS232P2_TAG, rs232_port_device, write_rts))
MCFG_MPCC_OUT_INT_CB(DEVWRITELINE("bim", bim68153_device, int3_w)) MCFG_MPCC_OUT_INT_CB(DEVWRITELINE("bim", bim68153_device, int3_w))
// MPCC3 // MPCC3
MCFG_MPCC68561_ADD ("mpcc3", XTAL_32MHz / 4, 0, 0) MCFG_MPCC68561_ADD ("mpcc3", CLOCK32 / 4, 0, 0)
MCFG_MPCC_OUT_TXD_CB(DEVWRITELINE(RS232P3_TAG, rs232_port_device, write_txd)) MCFG_MPCC_OUT_TXD_CB(DEVWRITELINE(RS232P3_TAG, rs232_port_device, write_txd))
MCFG_MPCC_OUT_DTR_CB(DEVWRITELINE(RS232P3_TAG, rs232_port_device, write_dtr)) MCFG_MPCC_OUT_DTR_CB(DEVWRITELINE(RS232P3_TAG, rs232_port_device, write_dtr))
MCFG_MPCC_OUT_RTS_CB(DEVWRITELINE(RS232P3_TAG, rs232_port_device, write_rts)) MCFG_MPCC_OUT_RTS_CB(DEVWRITELINE(RS232P3_TAG, rs232_port_device, write_rts))
@ -296,16 +312,65 @@ static MACHINE_CONFIG_FRAGMENT (fccpu20)
MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("mpcc3", mpcc68561_device, cts_w)) MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("mpcc3", mpcc68561_device, cts_w))
MACHINE_CONFIG_END MACHINE_CONFIG_END
machine_config_constructor vme_fccpu20_card_device::device_mconfig_additions() const // SYS68K/CPU-21S Part No.1 01 041 - 68020 CPU board + FPU 68881 at 12.5 MHz, 512 KB RAM
static MACHINE_CONFIG_DERIVED( fccpu21s, fccpu20 )
MCFG_DEVICE_MODIFY("maincpu")
MCFG_DEVICE_CLOCK( CLOCK50 / 4)
MACHINE_CONFIG_END
// SYS68K/CPU-21 Part No.1 01 001 - 68020 CPU board (CPU-20) + FPU 68881 at 16.7 MHz, 512 KB RAM
static MACHINE_CONFIG_DERIVED( fccpu21, fccpu20 )
MCFG_DEVICE_MODIFY("maincpu")
MCFG_DEVICE_CLOCK( CLOCK50 / 3)
MACHINE_CONFIG_END
// SYS68K/CPU-21A Part No.1 01 011 - 68020 CPU board + FPU 68881 at 20 MHz, 512 KB RAM
static MACHINE_CONFIG_DERIVED( fccpu21a, fccpu20 )
MCFG_DEVICE_MODIFY("maincpu")
MCFG_DEVICE_CLOCK( CLOCK40 / 2)
MACHINE_CONFIG_END
// SYS68K/CPU-21YA Part No.1 01 061 - 68020 CPU board + FPU 68881 at 20 MHz, 2048 KB RAM
static MACHINE_CONFIG_DERIVED( fccpu21ya, fccpu20 )
MCFG_DEVICE_MODIFY("maincpu")
MCFG_DEVICE_CLOCK( CLOCK40 / 2)
MACHINE_CONFIG_END
// SYS68K/CPU-21B Part No.1 01 021 - 68020 CPU board + FPU 68881 at 25 MHz, 512 KB RAM
static MACHINE_CONFIG_DERIVED( fccpu21b, fccpu20 )
MCFG_DEVICE_MODIFY("maincpu")
MCFG_DEVICE_CLOCK( CLOCK50 / 2)
MACHINE_CONFIG_END
// SYS68K/CPU-21YB Part No.1 01 071 - 68020 CPU board + FPU 68881 at 25 MHz, 2048 KB RAM
static MACHINE_CONFIG_DERIVED( fccpu21yb, fccpu20 )
MCFG_DEVICE_MODIFY("maincpu")
MCFG_DEVICE_CLOCK( CLOCK50 / 2)
MACHINE_CONFIG_END
machine_config_constructor vme_fccpu20_device::device_mconfig_additions() const
{ {
LOG("%s %s\n", tag(), FUNCNAME); LOG("%s %s\n", tag(), FUNCNAME);
switch (m_board_id)
{
case cpu20: return MACHINE_CONFIG_NAME( fccpu20 ); break;
case cpu21a: return MACHINE_CONFIG_NAME( fccpu21a ); break;
case cpu21ya: return MACHINE_CONFIG_NAME( fccpu21ya ); break;
case cpu21b: return MACHINE_CONFIG_NAME( fccpu21b ); break;
case cpu21yb: return MACHINE_CONFIG_NAME( fccpu21yb ); break;
case cpu21s: return MACHINE_CONFIG_NAME( fccpu21s ); break;
case cpu21: return MACHINE_CONFIG_NAME( fccpu21 ); break;
default: logerror("Attempt to get config for unknown board type %02x, defaulting to CPU20\n", m_board_id);
return MACHINE_CONFIG_NAME( fccpu20 );
}
return MACHINE_CONFIG_NAME( fccpu20 ); return MACHINE_CONFIG_NAME( fccpu20 );
} }
//************************************************************************** //**************************************************************************
// LIVE DEVICE // Base Device
//************************************************************************** //**************************************************************************
vme_fccpu20_card_device::vme_fccpu20_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source) : vme_fccpu20_device::vme_fccpu20_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source, fc_board_t board_id) :
device_t(mconfig, type, name, tag, owner, clock, shortname, source) device_t(mconfig, type, name, tag, owner, clock, shortname, source)
, device_vme_card_interface(mconfig, *this) , device_vme_card_interface(mconfig, *this)
, m_maincpu (*this, "maincpu") , m_maincpu (*this, "maincpu")
@ -314,31 +379,72 @@ vme_fccpu20_card_device::vme_fccpu20_card_device(const machine_config &mconfig,
, m_mpcc (*this, "mpcc") , m_mpcc (*this, "mpcc")
, m_mpcc2 (*this, "mpcc2") , m_mpcc2 (*this, "mpcc2")
, m_mpcc3 (*this, "mpcc3") , m_mpcc3 (*this, "mpcc3")
, m_board_id(board_id)
{ {
LOG("%s\n", FUNCNAME); LOG("%s\n", FUNCNAME);
} }
vme_fccpu20_card_device::vme_fccpu20_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : //**************************************************************************
device_t(mconfig, VME_FCCPU20, "Force Computer SYS68K/CPU-20 CPU Board", tag, owner, clock, "fccpu20", __FILE__) // Card Devices
,device_vme_card_interface(mconfig, *this) //**************************************************************************
, m_maincpu (*this, "maincpu") vme_fccpu20_card_device::vme_fccpu20_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
, m_pit (*this, "pit") : vme_fccpu20_card_device( mconfig, VME_FCCPU20, "Force Computer SYS68K/CPU-20 CPU Board", tag, owner, clock, "fccpu20", __FILE__)
, m_bim (*this, "bim") {
, m_mpcc (*this, "mpcc") LOG("%s %s\n", tag, FUNCNAME);
, m_mpcc2 (*this, "mpcc2") }
, m_mpcc3 (*this, "mpcc3")
vme_fccpu21s_card_device::vme_fccpu21s_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu21s_card_device( mconfig, VME_FCCPU21S, "Force Computer SYS68K/CPU-21S CPU Board", tag, owner, clock, "fccpu21s", __FILE__)
{
LOG("%s %s\n", tag, FUNCNAME);
}
vme_fccpu21_card_device::vme_fccpu21_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu21_card_device( mconfig, VME_FCCPU21, "Force Computer SYS68K/CPU-21 CPU Board", tag, owner, clock, "fccpu21", __FILE__)
{
LOG("%s %s\n", tag, FUNCNAME);
}
vme_fccpu21a_card_device::vme_fccpu21a_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu21a_card_device( mconfig, VME_FCCPU21A, "Force Computer SYS68K/CPU-21A CPU Board", tag, owner, clock, "fccpu21a", __FILE__)
{
LOG("%s %s\n", tag, FUNCNAME);
}
// TODO: Change to 2MB on board RAM and move FLME memory and find/verify memory map
vme_fccpu21ya_card_device::vme_fccpu21ya_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu21ya_card_device( mconfig, VME_FCCPU21YA, "Force Computer SYS68K/CPU-21YA CPU Board", tag, owner, clock, "fccpu21ya", __FILE__)
{
LOG("%s %s\n", tag, FUNCNAME);
}
vme_fccpu21b_card_device::vme_fccpu21b_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu21b_card_device( mconfig, VME_FCCPU21B, "Force Computer SYS68K/CPU-21B CPU Board", tag, owner, clock, "fccpu21b", __FILE__)
{
LOG("%s %s\n", tag, FUNCNAME);
}
// TODO: Change to 2MB on board RAM and move FLME memory and find/verify memory map
vme_fccpu21yb_card_device::vme_fccpu21yb_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vme_fccpu21yb_card_device( mconfig, VME_FCCPU21B, "Force Computer SYS68K/CPU-21YB CPU Board", tag, owner, clock, "fccpu21yb", __FILE__)
{ {
LOG("%s %s\n", tag, FUNCNAME); LOG("%s %s\n", tag, FUNCNAME);
} }
/* Start it up */ /* Start it up */
void vme_fccpu20_card_device::device_start() void vme_fccpu20_device::device_start()
{ {
LOG("%s\n", FUNCNAME); LOG("%s\n", FUNCNAME);
set_vme_device(); set_vme_device();
save_pointer (NAME (m_sysrom), sizeof(m_sysrom)); save_pointer (NAME (m_sysrom), sizeof(m_sysrom));
save_pointer (NAME (m_sysram), sizeof(m_sysram)); save_pointer (NAME (m_sysram), sizeof(m_sysram));
// save_item(NAME(m_board_id)); // TODO: Save this "non base type" item
/* TODO: setup this RAM from (not yet) optional SRAM-2x board and also support 2MB versions */
//m_maincpu->space(AS_PROGRAM).install_ram(0x80000, m_ram->size() + 0x7ffff, m_ram->pointer());
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */ /* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
m_sysrom = (uint32_t*)(memregion ("roms")->base()); m_sysrom = (uint32_t*)(memregion ("roms")->base());
@ -353,25 +459,27 @@ void vme_fccpu20_card_device::device_start()
} }
void vme_fccpu20_card_device::device_reset() void vme_fccpu20_device::device_reset()
{ {
LOG("%s\n", FUNCNAME); LOG("%s\n", FUNCNAME);
} }
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/ /* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/
READ32_MEMBER (vme_fccpu20_card_device::bootvect_r){ READ32_MEMBER (vme_fccpu20_device::bootvect_r)
{
LOG("%s\n", FUNCNAME); LOG("%s\n", FUNCNAME);
return m_sysrom[offset]; return m_sysrom[offset];
} }
WRITE32_MEMBER (vme_fccpu20_card_device::bootvect_w){ WRITE32_MEMBER (vme_fccpu20_device::bootvect_w)
{
LOG("%s\n", FUNCNAME); LOG("%s\n", FUNCNAME);
m_sysram[offset % sizeof(m_sysram)] &= ~mem_mask; m_sysram[offset % sizeof(m_sysram)] &= ~mem_mask;
m_sysram[offset % sizeof(m_sysram)] |= (data & mem_mask); m_sysram[offset % sizeof(m_sysram)] |= (data & mem_mask);
m_sysrom = &m_sysram[0]; // redirect all upcomming accesses to masking RAM until reset. m_sysrom = &m_sysram[0]; // redirect all upcomming accesses to masking RAM until reset.
} }
WRITE_LINE_MEMBER(vme_fccpu20_card_device::bim_irq_callback) WRITE_LINE_MEMBER(vme_fccpu20_device::bim_irq_callback)
{ {
LOGINT("%s(%02x)\n", FUNCNAME, state); LOGINT("%s(%02x)\n", FUNCNAME, state);
@ -381,7 +489,7 @@ WRITE_LINE_MEMBER(vme_fccpu20_card_device::bim_irq_callback)
update_irq_to_maincpu(); update_irq_to_maincpu();
} }
void vme_fccpu20_card_device::update_irq_to_maincpu() void vme_fccpu20_device::update_irq_to_maincpu()
{ {
LOGINT("%s()\n", FUNCNAME); LOGINT("%s()\n", FUNCNAME);
LOGINT(" - bim_irq_level: %02x\n", bim_irq_level); LOGINT(" - bim_irq_level: %02x\n", bim_irq_level);
@ -411,45 +519,93 @@ void vme_fccpu20_card_device::update_irq_to_maincpu()
B6: Auto execute FF00C0000 B6: Auto execute FF00C0000
B7: memory size? B7: memory size?
*/ */
/* PIT Port definitions */
#define BR7N9600 0x01 #define BR7N9600 0x01
#define BR7N28800 0x02 #define BR7N28800 0x02
#define BR7N38400 0x06 #define BR7N38400 0x06
#define BR7N57600 0x03 #define BR7N57600 0x03
#define BR8N38400 0x08 #define BR8N38400 0x08
#define FORCEBUG 0x30 #define FORCEBUG 0x30
READ8_MEMBER (vme_fccpu20_card_device::pita_r){
LOG("%s\n", FUNCNAME);
READ8_MEMBER (vme_fccpu20_device::pita_r)
{
LOG("%s\n", FUNCNAME);
return FORCEBUG | BR7N9600; return FORCEBUG | BR7N9600;
} }
/* Enabling/Disabling of VME IRQ 1-7 */ /* Enabling/Disabling of VME IRQ 1-7 */
READ8_MEMBER (vme_fccpu20_card_device::pitb_r){ READ8_MEMBER (vme_fccpu20_device::pitb_r)
{
LOG("%s\n", FUNCNAME); LOG("%s\n", FUNCNAME);
return 0xff; return 0xff;
} }
/* VME bus release software settings (output) (ROR, RAT, RATAR, RATBCLR, RORAT, RORRAT */ /* VME board ID bit and bus release software settings (output) (ROR, RAT, RATAR, RATBCLR, RORAT, RORRAT */
READ8_MEMBER (vme_fccpu20_card_device::pitc_r){ READ8_MEMBER (vme_fccpu20_device::pitc_r)
LOG("%s\n", FUNCNAME); {
return 0xff; uint8_t board_id = 0;
LOG("%s Board id:%02x\n", FUNCNAME, m_board_id);
switch (m_board_id)
{
case cpu20:
board_id = CPU20;
break;
case cpu21a:
case cpu21ya:
case cpu21b:
case cpu21yb:
case cpu21s:
case cpu21:
board_id = CPU21;
break;
default: logerror("Attempt to set unknown board type %02x, defaulting to CPU20\n", board_id);
board_id = CPU20;
}
return board_id | 0xbf;
} }
/* ROM definitions */ /* ROM definitions */
ROM_START (fccpu20) /* This is an original rom dump */ ROM_START (fccpu20) /* This is an original rom dump */
ROM_REGION32_BE(0x10000, "roms", 0) ROM_REGION32_BE(0x10000, "roms", 0)
// Boots with Board ID set to: 0x36 (FGA002 BOOT on terminal P4, "Wait until harddisk is up to speed " on terminal P1)
ROM_LOAD32_BYTE("L.BIN", 0x000002, 0x4000, CRC (174ab801) SHA1 (0d7b8ed29d5fdd4bd2073005008120c5f20128dd)) ROM_LOAD32_BYTE("L.BIN", 0x000002, 0x4000, CRC (174ab801) SHA1 (0d7b8ed29d5fdd4bd2073005008120c5f20128dd))
ROM_LOAD32_BYTE("LL.BIN", 0x000003, 0x4000, CRC (9fd9e3e4) SHA1 (e5a7c87021e6be412dd5a8166d9f62b681169eda)) ROM_LOAD32_BYTE("LL.BIN", 0x000003, 0x4000, CRC (9fd9e3e4) SHA1 (e5a7c87021e6be412dd5a8166d9f62b681169eda))
ROM_LOAD32_BYTE("U.BIN", 0x000001, 0x4000, CRC (d1afe4c0) SHA1 (b5baf9798d73632f7bb843cbc4b306c8c03f4296)) ROM_LOAD32_BYTE("U.BIN", 0x000001, 0x4000, CRC (d1afe4c0) SHA1 (b5baf9798d73632f7bb843cbc4b306c8c03f4296))
ROM_LOAD32_BYTE("UU.BIN", 0x000000, 0x4000, CRC (b54d623b) SHA1 (49b272184a04570b09004de71fae0ed0d1bf5929)) ROM_LOAD32_BYTE("UU.BIN", 0x000000, 0x4000, CRC (b54d623b) SHA1 (49b272184a04570b09004de71fae0ed0d1bf5929))
ROM_END ROM_END
const tiny_rom_entry *vme_fccpu20_card_device::device_rom_region() const ROM_START (nodump)
ROM_REGION32_BE(0x900000, "roms", 0)
ROM_LOAD("rom.bin", 0x800000, 0x10000, NO_DUMP)
ROM_END
/* These cpu-21 boards are supported by the latest cpu-20 rom */
#define rom_fccpu21s rom_fccpu20
#define rom_fccpu21 rom_fccpu20
#define rom_fccpu21a rom_fccpu20
#define rom_fccpu21ya rom_fccpu20
#define rom_fccpu21b rom_fccpu20
#define rom_fccpu21yb rom_fccpu20
const tiny_rom_entry *vme_fccpu20_device::device_rom_region() const
{ {
LOG("%s\n", FUNCNAME); LOG("%s\n", FUNCNAME);
switch (m_board_id)
{
case cpu20: return ROM_NAME( fccpu20 ); break;
case cpu21a: return ROM_NAME( fccpu21a ); break;
case cpu21ya: return ROM_NAME( fccpu21ya ); break;
case cpu21b: return ROM_NAME( fccpu21b ); break;
case cpu21yb: return ROM_NAME( fccpu21yb ); break;
case cpu21s: return ROM_NAME( fccpu21s ); break;
case cpu21: return ROM_NAME( fccpu21 ); break;
default: logerror("Attempt to get rom set for unknown board type %02x, defaulting to CPU20\n", m_board_id);
return ROM_NAME( fccpu20 ); return ROM_NAME( fccpu20 );
} }
}
/* /*
* System ROM information * System ROM information

96
src/devices/bus/vme/vme_fccpu20.h
View File

@ -12,21 +12,42 @@
#include "bus/vme/vme.h" #include "bus/vme/vme.h"
extern const device_type VME_FCCPU20; extern const device_type VME_FCCPU20;
extern const device_type VME_FCCPU21S;
extern const device_type VME_FCCPU21;
extern const device_type VME_FCCPU21A;
extern const device_type VME_FCCPU21YA;
extern const device_type VME_FCCPU21B;
extern const device_type VME_FCCPU21YB;
class vme_fccpu20_card_device : // PIT port C Board ID bits
public device_t #define CPU20 0x40
,public device_vme_card_interface #define CPU21 0x00
/* Board types */
enum fc_board_t {
cpu20,
cpu21,
cpu21a,
cpu21ya,
cpu21b,
cpu21yb,
cpu21s
};
//**************************************************************************
// Base Device declaration
//**************************************************************************
class vme_fccpu20_device : public device_t, public device_vme_card_interface
{ {
public: public:
vme_fccpu20_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source); vme_fccpu20_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source, fc_board_t board_id);
vme_fccpu20_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
// optional information overrides // optional information overrides
virtual machine_config_constructor device_mconfig_additions() const override; virtual machine_config_constructor device_mconfig_additions() const override;
virtual const tiny_rom_entry *device_rom_region() const override; virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_start() override;
// Below are duplicated declarations from src/mame/drivers/fccpu20.cpp // Below are duplicated declarations from src/mame/drivers/fccpu20.cpp
DECLARE_READ32_MEMBER (bootvect_r); DECLARE_READ32_MEMBER (bootvect_r);
DECLARE_WRITE32_MEMBER (bootvect_w); DECLARE_WRITE32_MEMBER (bootvect_w);
@ -51,11 +72,72 @@ private:
uint32_t *m_sysrom; uint32_t *m_sysrom;
uint32_t m_sysram[2]; uint32_t m_sysram[2];
void update_irq_to_maincpu(); void update_irq_to_maincpu();
fc_board_t m_board_id;
// Below replaces machine_start and machine_reset from src/mame/drivers/fccpu20.cpp // Below replaces machine_start and machine_reset from src/mame/drivers/fccpu20.cpp
protected: protected:
virtual void device_start() override;
virtual void device_reset() override; virtual void device_reset() override;
}; };
//**************************************************************************
// Board Device declarations
//**************************************************************************
class vme_fccpu20_card_device : public vme_fccpu20_device
{
public :
vme_fccpu20_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
vme_fccpu20_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source)
: vme_fccpu20_device( mconfig, type, name, tag, owner, clock, shortname, source, cpu20) { }
};
class vme_fccpu21s_card_device : public vme_fccpu20_device
{
public :
vme_fccpu21s_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
vme_fccpu21s_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source)
: vme_fccpu20_device( mconfig, type, name, tag, owner, clock, shortname, source, cpu21s) { }
};
class vme_fccpu21_card_device : public vme_fccpu20_device
{
public :
vme_fccpu21_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
vme_fccpu21_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source)
: vme_fccpu20_device( mconfig, type, name, tag, owner, clock, shortname, source, cpu21) { }
};
class vme_fccpu21a_card_device : public vme_fccpu20_device
{
public :
vme_fccpu21a_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
vme_fccpu21a_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source)
: vme_fccpu20_device( mconfig, type, name, tag, owner, clock, shortname, source, cpu21a) { }
};
class vme_fccpu21ya_card_device : public vme_fccpu20_device
{
public :
vme_fccpu21ya_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
vme_fccpu21ya_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source)
: vme_fccpu20_device( mconfig, type, name, tag, owner, clock, shortname, source, cpu21ya) { }
};
class vme_fccpu21b_card_device : public vme_fccpu20_device
{
public :
vme_fccpu21b_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
vme_fccpu21b_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source)
: vme_fccpu20_device( mconfig, type, name, tag, owner, clock, shortname, source, cpu21b) { }
};
class vme_fccpu21yb_card_device : public vme_fccpu20_device
{
public :
vme_fccpu21yb_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
vme_fccpu21yb_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source)
: vme_fccpu20_device( mconfig, type, name, tag, owner, clock, shortname, source, cpu21yb) { }
};
#endif // VME_FCCPU20_H #endif // VME_FCCPU20_H

118
src/mame/drivers/fccpu20.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Joakim Larsson Edstrom // copyright-holders:Joakim Larsson Edstrom
/*************************************************************************** /***************************************************************************
* *
* Force SYS68K CPU-20 VME SBC drivers * Force SYS68K CPU-20 and CPU-21 VME SBC drivers
* *
* The only purpose of this driver is to be able to start the VME board as * The only purpose of this driver is to be able to start the VME board as
* a single board computer and not as a slot device. It allows the board to * a single board computer and not as a slot device. It allows the board to
@ -64,31 +64,137 @@
#include "bus/vme/vme.h" #include "bus/vme/vme.h"
#include "bus/vme/vme_fccpu20.h" #include "bus/vme/vme_fccpu20.h"
//**************************************************************************
// CONFIGURABLE LOGGING
//**************************************************************************
#define LOG_GENERAL (1U << 0)
#define LOG_SETUP (1U << 1)
//#define VERBOSE (LOG_GENERAL | LOG_SETUP)
//#define LOG_OUTPUT_FUNC printf
#include "logmacro.h"
#define LOGSETUP(...) LOGMASKED(LOG_SETUP, __VA_ARGS__)
//**************************************************************************
// MACROS / CONSTANTS
//**************************************************************************
#ifdef _MSC_VER
#define FUNCNAME __func__
#else
#define FUNCNAME __PRETTY_FUNCTION__
#endif
class cpu20_state : public driver_device class cpu20_state : public driver_device
{ {
public: public:
cpu20_state(const machine_config &mconfig, device_type type, const char *tag) cpu20_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device (mconfig, type, tag) { } : driver_device (mconfig, type, tag)
{
}
DECLARE_DRIVER_INIT(cpu21s) { LOGSETUP("%s\n", FUNCNAME); }
DECLARE_DRIVER_INIT(cpu21) { LOGSETUP("%s\n", FUNCNAME); }
DECLARE_DRIVER_INIT(cpu21a) { LOGSETUP("%s\n", FUNCNAME); }
DECLARE_DRIVER_INIT(cpu21ya) { LOGSETUP("%s\n", FUNCNAME); }
DECLARE_DRIVER_INIT(cpu21b) { LOGSETUP("%s\n", FUNCNAME); }
DECLARE_DRIVER_INIT(cpu21yb) { LOGSETUP("%s\n", FUNCNAME); }
}; };
/* Input ports */ /* Input ports */
static INPUT_PORTS_START (cpu20) static INPUT_PORTS_START (cpu20)
INPUT_PORTS_END INPUT_PORTS_END
/* Slot interfaces */
static SLOT_INTERFACE_START(cpu20_vme_cards) static SLOT_INTERFACE_START(cpu20_vme_cards)
SLOT_INTERFACE("fccpu20", VME_FCCPU20) SLOT_INTERFACE("fccpu20", VME_FCCPU20)
SLOT_INTERFACE_END SLOT_INTERFACE_END
/* Machine configuration */ static SLOT_INTERFACE_START(cpu21s_vme_cards)
SLOT_INTERFACE("fccpu21s", VME_FCCPU21S)
SLOT_INTERFACE_END
static SLOT_INTERFACE_START(cpu21_vme_cards)
SLOT_INTERFACE("fccpu21", VME_FCCPU21)
SLOT_INTERFACE_END
static SLOT_INTERFACE_START(cpu21a_vme_cards)
SLOT_INTERFACE("fccpu21a", VME_FCCPU21A)
SLOT_INTERFACE_END
static SLOT_INTERFACE_START(cpu21ya_vme_cards)
SLOT_INTERFACE("fccpu21ya", VME_FCCPU21YA)
SLOT_INTERFACE_END
static SLOT_INTERFACE_START(cpu21b_vme_cards)
SLOT_INTERFACE("fccpu21b", VME_FCCPU21B)
SLOT_INTERFACE_END
static SLOT_INTERFACE_START(cpu21yb_vme_cards)
SLOT_INTERFACE("fccpu21yb", VME_FCCPU21YB)
SLOT_INTERFACE_END
/* Machine configurations */
MACHINE_CONFIG_START (cpu20, cpu20_state) MACHINE_CONFIG_START (cpu20, cpu20_state)
MCFG_VME_DEVICE_ADD("vme") MCFG_VME_DEVICE_ADD("vme")
MCFG_VME_SLOT_ADD ("vme", "slot1", cpu20_vme_cards, "fccpu20") MCFG_VME_SLOT_ADD ("vme", "slot1", cpu20_vme_cards, "fccpu20")
MACHINE_CONFIG_END MACHINE_CONFIG_END
/* ROM configuration */ MACHINE_CONFIG_START (cpu21s, cpu20_state)
ROM_START(fccpu20sbc) MCFG_VME_DEVICE_ADD("vme")
ROM_END MCFG_VME_SLOT_ADD ("vme", "slot1", cpu21s_vme_cards, "fccpu21s")
MACHINE_CONFIG_END
MACHINE_CONFIG_START (cpu21, cpu20_state)
MCFG_VME_DEVICE_ADD("vme")
MCFG_VME_SLOT_ADD ("vme", "slot1", cpu21_vme_cards, "fccpu21")
MACHINE_CONFIG_END
MACHINE_CONFIG_START (cpu21a, cpu20_state)
MCFG_VME_DEVICE_ADD("vme")
MCFG_VME_SLOT_ADD ("vme", "slot1", cpu21a_vme_cards, "fccpu21a")
MACHINE_CONFIG_END
MACHINE_CONFIG_START (cpu21ya, cpu20_state)
MCFG_VME_DEVICE_ADD("vme")
MCFG_VME_SLOT_ADD ("vme", "slot1", cpu21ya_vme_cards, "fccpu21ya")
MACHINE_CONFIG_END
MACHINE_CONFIG_START (cpu21b, cpu20_state)
MCFG_VME_DEVICE_ADD("vme")
MCFG_VME_SLOT_ADD ("vme", "slot1", cpu21b_vme_cards, "fccpu21b")
MACHINE_CONFIG_END
MACHINE_CONFIG_START (cpu21yb, cpu20_state)
MCFG_VME_DEVICE_ADD("vme")
MCFG_VME_SLOT_ADD ("vme", "slot1", cpu21yb_vme_cards, "fccpu21yb")
MACHINE_CONFIG_END
/* ROM configurations */
ROM_START(fccpu20sbc) ROM_END
ROM_START(fccpu21ssbc) ROM_END
ROM_START(fccpu21sbc) ROM_END
ROM_START(fccpu21asbc) ROM_END
ROM_START(fccpu21yasbc) ROM_END
ROM_START(fccpu21bsbc) ROM_END
ROM_START(fccpu21ybsbc) ROM_END
/* Boards supported by same rom set, need to do like this to avoid need for multi named rom sets */
#define rom_fccpu21ssbc rom_fccpu20sbc
#define rom_fccpu21sbc rom_fccpu20sbc
#define rom_fccpu21asbc rom_fccpu20sbc
#define rom_fccpu21yasbc rom_fccpu20sbc
#define rom_fccpu21bsbc rom_fccpu20sbc
#define rom_fccpu21ybsbc rom_fccpu20sbc
/* Driver */ /* Driver */
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */ /* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP (1986, fccpu20sbc, 0, 0, cpu20, cpu20, driver_device, 0, "Force Computers Gmbh", "SYS68K/CPU-20", MACHINE_NO_SOUND_HW | MACHINE_TYPE_COMPUTER ) COMP (1986, fccpu20sbc, 0, 0, cpu20, cpu20, driver_device, 0, "Force Computers Gmbh", "SYS68K/CPU-20", MACHINE_NO_SOUND_HW | MACHINE_TYPE_COMPUTER )
COMP (1986, fccpu21ssbc, fccpu20sbc, 0, cpu21s, cpu20, cpu20_state, cpu21s, "Force Computers Gmbh", "SYS68K/CPU-21S", MACHINE_NO_SOUND_HW | MACHINE_TYPE_COMPUTER )
COMP (1986, fccpu21sbc, fccpu20sbc, 0, cpu21, cpu20, cpu20_state, cpu21, "Force Computers Gmbh", "SYS68K/CPU-21", MACHINE_NO_SOUND_HW | MACHINE_TYPE_COMPUTER )
COMP (1986, fccpu21asbc, fccpu20sbc, 0, cpu21a, cpu20, cpu20_state, cpu21a, "Force Computers Gmbh", "SYS68K/CPU-21A", MACHINE_NO_SOUND_HW | MACHINE_TYPE_COMPUTER )
COMP (1986, fccpu21yasbc, fccpu20sbc, 0, cpu21ya, cpu20, cpu20_state, cpu21ya, "Force Computers Gmbh", "SYS68K/CPU-21YA", MACHINE_NO_SOUND_HW | MACHINE_TYPE_COMPUTER )
COMP (1986, fccpu21bsbc, fccpu20sbc, 0, cpu21b, cpu20, cpu20_state, cpu21b, "Force Computers Gmbh", "SYS68K/CPU-21B", MACHINE_NO_SOUND_HW | MACHINE_TYPE_COMPUTER )
COMP (1986, fccpu21ybsbc, fccpu20sbc, 0, cpu21yb, cpu20, cpu20_state, cpu21yb, "Force Computers Gmbh", "SYS68K/CPU-21YB", MACHINE_NO_SOUND_HW | MACHINE_TYPE_COMPUTER )

6
src/mame/mame.lst
View File

@ -12228,6 +12228,12 @@ fc100 //
@source:fccpu20.cpp @source:fccpu20.cpp
fccpu20sbc fccpu20sbc
fccpu21ssbc
fccpu21sbc
fccpu21asbc
fccpu21yasbc
fccpu21bsbc
fccpu21ybsbc
@source:fccpu30.cpp @source:fccpu30.cpp
fccpu30 fccpu30