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tms34010: Modernised cpu core. (nw)

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This commit is contained in:
Wilbert Pol 2014-07-03 20:28:08 +00:00
parent ceeb8ee0a5
commit 642010acae
27 changed files with 3976 additions and 3883 deletions
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428
src/emu/cpu/tms34010/34010fld.c
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@ -13,182 +13,182 @@
FIELD WRITE FUNCTIONS
***************************************************************************/
static void wfield_01(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_01(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0x01,16);
WFIELDMAC(0x01,16);
}
static void wfield_02(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_02(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0x03,15);
WFIELDMAC(0x03,15);
}
static void wfield_03(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_03(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0x07,14);
WFIELDMAC(0x07,14);
}
static void wfield_04(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_04(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0x0f,13);
WFIELDMAC(0x0f,13);
}
static void wfield_05(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_05(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0x1f,12);
WFIELDMAC(0x1f,12);
}
static void wfield_06(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_06(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0x3f,11);
WFIELDMAC(0x3f,11);
}
static void wfield_07(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_07(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0x7f,10);
WFIELDMAC(0x7f,10);
}
static void wfield_08(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_08(offs_t offset, UINT32 data)
{
WFIELDMAC_8(tms);
WFIELDMAC_8();
}
static void wfield_09(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_09(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0x1ff,8);
WFIELDMAC(0x1ff,8);
}
static void wfield_10(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_10(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0x3ff,7);
WFIELDMAC(0x3ff,7);
}
static void wfield_11(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_11(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0x7ff,6);
WFIELDMAC(0x7ff,6);
}
static void wfield_12(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_12(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0xfff,5);
WFIELDMAC(0xfff,5);
}
static void wfield_13(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_13(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0x1fff,4);
WFIELDMAC(0x1fff,4);
}
static void wfield_14(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_14(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0x3fff,3);
WFIELDMAC(0x3fff,3);
}
static void wfield_15(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_15(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0x7fff,2);
WFIELDMAC(0x7fff,2);
}
static void wfield_16(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_16(offs_t offset, UINT32 data)
{
if (offset & 0x0f)
{
WFIELDMAC(tms,0xffff,1);
WFIELDMAC(0xffff,1);
}
else
{
TMS34010_WRMEM_WORD(tms,TOBYTE(offset),data);
TMS34010_WRMEM_WORD(TOBYTE(offset),data);
}
}
static void wfield_17(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_17(offs_t offset, UINT32 data)
{
WFIELDMAC(tms,0x1ffff,0);
WFIELDMAC(0x1ffff,0);
}
static void wfield_18(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_18(offs_t offset, UINT32 data)
{
WFIELDMAC_BIG(tms,0x3ffff,15);
WFIELDMAC_BIG(0x3ffff,15);
}
static void wfield_19(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_19(offs_t offset, UINT32 data)
{
WFIELDMAC_BIG(tms,0x7ffff,14);
WFIELDMAC_BIG(0x7ffff,14);
}
static void wfield_20(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_20(offs_t offset, UINT32 data)
{
WFIELDMAC_BIG(tms,0xfffff,13);
WFIELDMAC_BIG(0xfffff,13);
}
static void wfield_21(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_21(offs_t offset, UINT32 data)
{
WFIELDMAC_BIG(tms,0x1fffff,12);
WFIELDMAC_BIG(0x1fffff,12);
}
static void wfield_22(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_22(offs_t offset, UINT32 data)
{
WFIELDMAC_BIG(tms,0x3fffff,11);
WFIELDMAC_BIG(0x3fffff,11);
}
static void wfield_23(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_23(offs_t offset, UINT32 data)
{
WFIELDMAC_BIG(tms,0x7fffff,10);
WFIELDMAC_BIG(0x7fffff,10);
}
static void wfield_24(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_24(offs_t offset, UINT32 data)
{
WFIELDMAC_BIG(tms,0xffffff,9);
WFIELDMAC_BIG(0xffffff,9);
}
static void wfield_25(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_25(offs_t offset, UINT32 data)
{
WFIELDMAC_BIG(tms,0x1ffffff,8);
WFIELDMAC_BIG(0x1ffffff,8);
}
static void wfield_26(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_26(offs_t offset, UINT32 data)
{
WFIELDMAC_BIG(tms,0x3ffffff,7);
WFIELDMAC_BIG(0x3ffffff,7);
}
static void wfield_27(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_27(offs_t offset, UINT32 data)
{
WFIELDMAC_BIG(tms,0x7ffffff,6);
WFIELDMAC_BIG(0x7ffffff,6);
}
static void wfield_28(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_28(offs_t offset, UINT32 data)
{
WFIELDMAC_BIG(tms,0xfffffff,5);
WFIELDMAC_BIG(0xfffffff,5);
}
static void wfield_29(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_29(offs_t offset, UINT32 data)
{
WFIELDMAC_BIG(tms,0x1fffffff,4);
WFIELDMAC_BIG(0x1fffffff,4);
}
static void wfield_30(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_30(offs_t offset, UINT32 data)
{
WFIELDMAC_BIG(tms,0x3fffffff,3);
WFIELDMAC_BIG(0x3fffffff,3);
}
static void wfield_31(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_31(offs_t offset, UINT32 data)
{
WFIELDMAC_BIG(tms,0x7fffffff,2);
WFIELDMAC_BIG(0x7fffffff,2);
}
static void wfield_32(tms34010_state *tms, offs_t offset, UINT32 data)
void tms340x0_device::wfield_32(offs_t offset, UINT32 data)
{
WFIELDMAC_32(tms);
WFIELDMAC_32();
}
static void (*const tms34010_wfield_functions[32])(tms34010_state *tms, offs_t offset, UINT32 data) =
const tms340x0_device::wfield_func tms340x0_device::s_wfield_functions[32] =
{
wfield_32, wfield_01, wfield_02, wfield_03, wfield_04, wfield_05,
wfield_06, wfield_07, wfield_08, wfield_09, wfield_10, wfield_11,
wfield_12, wfield_13, wfield_14, wfield_15, wfield_16, wfield_17,
wfield_18, wfield_19, wfield_20, wfield_21, wfield_22, wfield_23,
wfield_24, wfield_25, wfield_26, wfield_27, wfield_28, wfield_29,
wfield_30, wfield_31
&tms340x0_device::wfield_32, &tms340x0_device::wfield_01, &tms340x0_device::wfield_02, &tms340x0_device::wfield_03, &tms340x0_device::wfield_04, &tms340x0_device::wfield_05,
&tms340x0_device::wfield_06, &tms340x0_device::wfield_07, &tms340x0_device::wfield_08, &tms340x0_device::wfield_09, &tms340x0_device::wfield_10, &tms340x0_device::wfield_11,
&tms340x0_device::wfield_12, &tms340x0_device::wfield_13, &tms340x0_device::wfield_14, &tms340x0_device::wfield_15, &tms340x0_device::wfield_16, &tms340x0_device::wfield_17,
&tms340x0_device::wfield_18, &tms340x0_device::wfield_19, &tms340x0_device::wfield_20, &tms340x0_device::wfield_21, &tms340x0_device::wfield_22, &tms340x0_device::wfield_23,
&tms340x0_device::wfield_24, &tms340x0_device::wfield_25, &tms340x0_device::wfield_26, &tms340x0_device::wfield_27, &tms340x0_device::wfield_28, &tms340x0_device::wfield_29,
&tms340x0_device::wfield_30, &tms340x0_device::wfield_31
};
@ -197,232 +197,232 @@ static void (*const tms34010_wfield_functions[32])(tms34010_state *tms, offs_t o
FIELD READ FUNCTIONS (ZERO-EXTEND)
***************************************************************************/
static UINT32 rfield_z_01(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_01(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x01,16);
RFIELDMAC(0x01,16);
return ret;
}
static UINT32 rfield_z_02(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_02(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x03,15);
RFIELDMAC(0x03,15);
return ret;
}
static UINT32 rfield_z_03(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_03(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x07,14);
RFIELDMAC(0x07,14);
return ret;
}
static UINT32 rfield_z_04(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_04(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x0f,13);
RFIELDMAC(0x0f,13);
return ret;
}
static UINT32 rfield_z_05(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_05(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x1f,12);
RFIELDMAC(0x1f,12);
return ret;
}
static UINT32 rfield_z_06(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_06(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x3f,11);
RFIELDMAC(0x3f,11);
return ret;
}
static UINT32 rfield_z_07(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_07(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x7f,10);
RFIELDMAC(0x7f,10);
return ret;
}
static UINT32 rfield_z_08(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_08(offs_t offset)
{
UINT32 ret;
RFIELDMAC_8(tms);
RFIELDMAC_8();
return ret;
}
static UINT32 rfield_z_09(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_09(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x1ff,8);
RFIELDMAC(0x1ff,8);
return ret;
}
static UINT32 rfield_z_10(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_10(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x3ff,7);
RFIELDMAC(0x3ff,7);
return ret;
}
static UINT32 rfield_z_11(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_11(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x7ff,6);
RFIELDMAC(0x7ff,6);
return ret;
}
static UINT32 rfield_z_12(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_12(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0xfff,5);
RFIELDMAC(0xfff,5);
return ret;
}
static UINT32 rfield_z_13(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_13(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x1fff,4);
RFIELDMAC(0x1fff,4);
return ret;
}
static UINT32 rfield_z_14(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_14(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x3fff,3);
RFIELDMAC(0x3fff,3);
return ret;
}
static UINT32 rfield_z_15(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_15(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x7fff,2);
RFIELDMAC(0x7fff,2);
return ret;
}
static UINT32 rfield_z_16(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_16(offs_t offset)
{
UINT32 ret;
if (offset & 0x0f)
{
RFIELDMAC(tms,0xffff,1);
RFIELDMAC(0xffff,1);
}
else
ret = TMS34010_RDMEM_WORD(tms,TOBYTE(offset));
ret = TMS34010_RDMEM_WORD(TOBYTE(offset));
return ret;
}
static UINT32 rfield_z_17(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_17(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x1ffff,0);
RFIELDMAC(0x1ffff,0);
return ret;
}
static UINT32 rfield_z_18(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_18(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x3ffff,15);
RFIELDMAC_BIG(0x3ffff,15);
return ret;
}
static UINT32 rfield_z_19(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_19(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x7ffff,14);
RFIELDMAC_BIG(0x7ffff,14);
return ret;
}
static UINT32 rfield_z_20(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_20(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0xfffff,13);
RFIELDMAC_BIG(0xfffff,13);
return ret;
}
static UINT32 rfield_z_21(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_21(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x1fffff,12);
RFIELDMAC_BIG(0x1fffff,12);
return ret;
}
static UINT32 rfield_z_22(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_22(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x3fffff,11);
RFIELDMAC_BIG(0x3fffff,11);
return ret;
}
static UINT32 rfield_z_23(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_23(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x7fffff,10);
RFIELDMAC_BIG(0x7fffff,10);
return ret;
}
static UINT32 rfield_z_24(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_24(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0xffffff,9);
RFIELDMAC_BIG(0xffffff,9);
return ret;
}
static UINT32 rfield_z_25(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_25(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x1ffffff,8);
RFIELDMAC_BIG(0x1ffffff,8);
return ret;
}
static UINT32 rfield_z_26(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_26(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x3ffffff,7);
RFIELDMAC_BIG(0x3ffffff,7);
return ret;
}
static UINT32 rfield_z_27(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_27(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x7ffffff,6);
RFIELDMAC_BIG(0x7ffffff,6);
return ret;
}
static UINT32 rfield_z_28(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_28(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0xfffffff,5);
RFIELDMAC_BIG(0xfffffff,5);
return ret;
}
static UINT32 rfield_z_29(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_29(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x1fffffff,4);
RFIELDMAC_BIG(0x1fffffff,4);
return ret;
}
static UINT32 rfield_z_30(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_30(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x3fffffff,3);
RFIELDMAC_BIG(0x3fffffff,3);
return ret;
}
static UINT32 rfield_z_31(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_z_31(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x7fffffff,2);
RFIELDMAC_BIG(0x7fffffff,2);
return ret;
}
static UINT32 rfield_32(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_32(offs_t offset)
{
RFIELDMAC_32(tms);
RFIELDMAC_32();
}
@ -430,250 +430,250 @@ static UINT32 rfield_32(tms34010_state *tms, offs_t offset)
FIELD READ FUNCTIONS (SIGN-EXTEND)
***************************************************************************/
static UINT32 rfield_s_01(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_01(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x01,16);
RFIELDMAC(0x01,16);
return ((INT32)(ret << 31)) >> 31;
}
static UINT32 rfield_s_02(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_02(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x03,15);
RFIELDMAC(0x03,15);
return ((INT32)(ret << 30)) >> 30;
}
static UINT32 rfield_s_03(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_03(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x07,14);
RFIELDMAC(0x07,14);
return ((INT32)(ret << 29)) >> 29;
}
static UINT32 rfield_s_04(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_04(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x0f,13);
RFIELDMAC(0x0f,13);
return ((INT32)(ret << 28)) >> 28;
}
static UINT32 rfield_s_05(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_05(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x1f,12);
RFIELDMAC(0x1f,12);
return ((INT32)(ret << 27)) >> 27;
}
static UINT32 rfield_s_06(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_06(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x3f,11);
RFIELDMAC(0x3f,11);
return ((INT32)(ret << 26)) >> 26;
}
static UINT32 rfield_s_07(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_07(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x7f,10);
RFIELDMAC(0x7f,10);
return ((INT32)(ret << 25)) >> 25;
}
static UINT32 rfield_s_08(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_08(offs_t offset)
{
UINT32 ret;
if (offset & 0x07)
{
RFIELDMAC(tms,0xff,9);
RFIELDMAC(0xff,9);
}
else
ret = TMS34010_RDMEM(tms,TOBYTE(offset));
ret = TMS34010_RDMEM(TOBYTE(offset));
return (INT32)(INT8)ret;
}
static UINT32 rfield_s_09(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_09(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x1ff,8);
RFIELDMAC(0x1ff,8);
return ((INT32)(ret << 23)) >> 23;
}
static UINT32 rfield_s_10(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_10(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x3ff,7);
RFIELDMAC(0x3ff,7);
return ((INT32)(ret << 22)) >> 22;
}
static UINT32 rfield_s_11(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_11(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x7ff,6);
RFIELDMAC(0x7ff,6);
return ((INT32)(ret << 21)) >> 21;
}
static UINT32 rfield_s_12(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_12(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0xfff,5);
RFIELDMAC(0xfff,5);
return ((INT32)(ret << 20)) >> 20;
}
static UINT32 rfield_s_13(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_13(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x1fff,4);
RFIELDMAC(0x1fff,4);
return ((INT32)(ret << 19)) >> 19;
}
static UINT32 rfield_s_14(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_14(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x3fff,3);
RFIELDMAC(0x3fff,3);
return ((INT32)(ret << 18)) >> 18;
}
static UINT32 rfield_s_15(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_15(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x7fff,2);
RFIELDMAC(0x7fff,2);
return ((INT32)(ret << 17)) >> 17;
}
static UINT32 rfield_s_16(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_16(offs_t offset)
{
UINT32 ret;
if (offset & 0x0f)
{
RFIELDMAC(tms,0xffff,1);
RFIELDMAC(0xffff,1);
}
else
{
ret = TMS34010_RDMEM_WORD(tms,TOBYTE(offset));
ret = TMS34010_RDMEM_WORD(TOBYTE(offset));
}
return (INT32)(INT16)ret;
}
static UINT32 rfield_s_17(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_17(offs_t offset)
{
UINT32 ret;
RFIELDMAC(tms,0x1ffff,0);
RFIELDMAC(0x1ffff,0);
return ((INT32)(ret << 15)) >> 15;
}
static UINT32 rfield_s_18(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_18(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x3ffff,15);
RFIELDMAC_BIG(0x3ffff,15);
return ((INT32)(ret << 14)) >> 14;
}
static UINT32 rfield_s_19(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_19(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x7ffff,14);
RFIELDMAC_BIG(0x7ffff,14);
return ((INT32)(ret << 13)) >> 13;
}
static UINT32 rfield_s_20(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_20(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0xfffff,13);
RFIELDMAC_BIG(0xfffff,13);
return ((INT32)(ret << 12)) >> 12;
}
static UINT32 rfield_s_21(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_21(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x1fffff,12);
RFIELDMAC_BIG(0x1fffff,12);
return ((INT32)(ret << 11)) >> 11;
}
static UINT32 rfield_s_22(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_22(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x3fffff,11);
RFIELDMAC_BIG(0x3fffff,11);
return ((INT32)(ret << 10)) >> 10;
}
static UINT32 rfield_s_23(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_23(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x7fffff,10);
RFIELDMAC_BIG(0x7fffff,10);
return ((INT32)(ret << 9)) >> 9;
}
static UINT32 rfield_s_24(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_24(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0xffffff,9);
RFIELDMAC_BIG(0xffffff,9);
return ((INT32)(ret << 8)) >> 8;
}
static UINT32 rfield_s_25(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_25(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x1ffffff,8);
RFIELDMAC_BIG(0x1ffffff,8);
return ((INT32)(ret << 7)) >> 7;
}
static UINT32 rfield_s_26(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_26(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x3ffffff,7);
RFIELDMAC_BIG(0x3ffffff,7);
return ((INT32)(ret << 6)) >> 6;
}
static UINT32 rfield_s_27(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_27(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x7ffffff,6);
RFIELDMAC_BIG(0x7ffffff,6);
return ((INT32)(ret << 5)) >> 5;
}
static UINT32 rfield_s_28(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_28(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0xfffffff,5);
RFIELDMAC_BIG(0xfffffff,5);
return ((INT32)(ret << 4)) >> 4;
}
static UINT32 rfield_s_29(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_29(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x1fffffff,4);
RFIELDMAC_BIG(0x1fffffff,4);
return ((INT32)(ret << 3)) >> 3;
}
static UINT32 rfield_s_30(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_30(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x3fffffff,3);
RFIELDMAC_BIG(0x3fffffff,3);
return ((INT32)(ret << 2)) >> 2;
}
static UINT32 rfield_s_31(tms34010_state *tms, offs_t offset)
UINT32 tms340x0_device::rfield_s_31(offs_t offset)
{
UINT32 ret;
RFIELDMAC_BIG(tms,0x7fffffff,2);
RFIELDMAC_BIG(0x7fffffff,2);
return ((INT32)(ret << 1)) >> 1;
}
static UINT32 (*const tms34010_rfield_functions[64])(tms34010_state *tms, offs_t offset) =
const tms340x0_device::rfield_func tms340x0_device::s_rfield_functions[64] =
{
rfield_32 , rfield_z_01, rfield_z_02, rfield_z_03, rfield_z_04, rfield_z_05,
rfield_z_06, rfield_z_07, rfield_z_08, rfield_z_09, rfield_z_10, rfield_z_11,
rfield_z_12, rfield_z_13, rfield_z_14, rfield_z_15, rfield_z_16, rfield_z_17,
rfield_z_18, rfield_z_19, rfield_z_20, rfield_z_21, rfield_z_22, rfield_z_23,
rfield_z_24, rfield_z_25, rfield_z_26, rfield_z_27, rfield_z_28, rfield_z_29,
rfield_z_30, rfield_z_31,
rfield_32 , rfield_s_01, rfield_s_02, rfield_s_03, rfield_s_04, rfield_s_05,
rfield_s_06, rfield_s_07, rfield_s_08, rfield_s_09, rfield_s_10, rfield_s_11,
rfield_s_12, rfield_s_13, rfield_s_14, rfield_s_15, rfield_s_16, rfield_s_17,
rfield_s_18, rfield_s_19, rfield_s_20, rfield_s_21, rfield_s_22, rfield_s_23,
rfield_s_24, rfield_s_25, rfield_s_26, rfield_s_27, rfield_s_28, rfield_s_29,
rfield_s_30, rfield_s_31
&tms340x0_device::rfield_32 , &tms340x0_device::rfield_z_01, &tms340x0_device::rfield_z_02, &tms340x0_device::rfield_z_03, &tms340x0_device::rfield_z_04, &tms340x0_device::rfield_z_05,
&tms340x0_device::rfield_z_06, &tms340x0_device::rfield_z_07, &tms340x0_device::rfield_z_08, &tms340x0_device::rfield_z_09, &tms340x0_device::rfield_z_10, &tms340x0_device::rfield_z_11,
&tms340x0_device::rfield_z_12, &tms340x0_device::rfield_z_13, &tms340x0_device::rfield_z_14, &tms340x0_device::rfield_z_15, &tms340x0_device::rfield_z_16, &tms340x0_device::rfield_z_17,
&tms340x0_device::rfield_z_18, &tms340x0_device::rfield_z_19, &tms340x0_device::rfield_z_20, &tms340x0_device::rfield_z_21, &tms340x0_device::rfield_z_22, &tms340x0_device::rfield_z_23,
&tms340x0_device::rfield_z_24, &tms340x0_device::rfield_z_25, &tms340x0_device::rfield_z_26, &tms340x0_device::rfield_z_27, &tms340x0_device::rfield_z_28, &tms340x0_device::rfield_z_29,
&tms340x0_device::rfield_z_30, &tms340x0_device::rfield_z_31,
&tms340x0_device::rfield_32 , &tms340x0_device::rfield_s_01, &tms340x0_device::rfield_s_02, &tms340x0_device::rfield_s_03, &tms340x0_device::rfield_s_04, &tms340x0_device::rfield_s_05,
&tms340x0_device::rfield_s_06, &tms340x0_device::rfield_s_07, &tms340x0_device::rfield_s_08, &tms340x0_device::rfield_s_09, &tms340x0_device::rfield_s_10, &tms340x0_device::rfield_s_11,
&tms340x0_device::rfield_s_12, &tms340x0_device::rfield_s_13, &tms340x0_device::rfield_s_14, &tms340x0_device::rfield_s_15, &tms340x0_device::rfield_s_16, &tms340x0_device::rfield_s_17,
&tms340x0_device::rfield_s_18, &tms340x0_device::rfield_s_19, &tms340x0_device::rfield_s_20, &tms340x0_device::rfield_s_21, &tms340x0_device::rfield_s_22, &tms340x0_device::rfield_s_23,
&tms340x0_device::rfield_s_24, &tms340x0_device::rfield_s_25, &tms340x0_device::rfield_s_26, &tms340x0_device::rfield_s_27, &tms340x0_device::rfield_s_28, &tms340x0_device::rfield_s_29,
&tms340x0_device::rfield_s_30, &tms340x0_device::rfield_s_31
};

1497
src/emu/cpu/tms34010/34010gfx.c
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2186
src/emu/cpu/tms34010/34010ops.c
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98
src/emu/cpu/tms34010/34010ops.h
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@ -19,29 +19,29 @@
MEMORY I/O MACROS
***************************************************************************/
#define TMS34010_RDMEM(T,A) ((unsigned)(T)->program->read_byte (A))
#define TMS34010_RDMEM_WORD(T,A) ((unsigned)(T)->program->read_word (A))
INLINE UINT32 TMS34010_RDMEM_DWORD(tms34010_state *tms, offs_t A)
#define TMS34010_RDMEM(A) ((unsigned)m_program->read_byte (A))
#define TMS34010_RDMEM_WORD(A) ((unsigned)m_program->read_word (A))
inline UINT32 tms340x0_device::TMS34010_RDMEM_DWORD(offs_t A)
{
UINT32 result = tms->program->read_word(A);
return result | (tms->program->read_word(A+2)<<16);
UINT32 result = m_program->read_word(A);
return result | (m_program->read_word(A+2)<<16);
}
#define TMS34010_WRMEM(T,A,V) ((T)->program->write_byte(A,V))
#define TMS34010_WRMEM_WORD(T,A,V) ((T)->program->write_word(A,V))
INLINE void TMS34010_WRMEM_DWORD(tms34010_state *tms, offs_t A,UINT32 V)
#define TMS34010_WRMEM(A,V) (m_program->write_byte(A,V))
#define TMS34010_WRMEM_WORD(A,V) (m_program->write_word(A,V))
inline void tms340x0_device::TMS34010_WRMEM_DWORD(offs_t A, UINT32 V)
{
tms->program->write_word(A,V);
tms->program->write_word(A+2,V>>16);
m_program->write_word(A,V);
m_program->write_word(A+2,V>>16);
}
/* IO registers accessor */
#define IOREG(T,reg) ((T)->IOregs[reg])
#define SMART_IOREG(T,reg) ((T)->IOregs[(T)->is_34020 ? (int)REG020_##reg : (int)REG_##reg])
#define PBH(T) (IOREG(T, REG_CONTROL) & 0x0100)
#define PBV(T) (IOREG(T, REG_CONTROL) & 0x0200)
#define IOREG(reg) (m_IOregs[reg])
#define SMART_IOREG(reg) (m_IOregs[m_is_34020 ? (int)REG020_##reg : (int)REG_##reg])
#define PBH() (IOREG(REG_CONTROL) & 0x0100)
#define PBV() (IOREG(REG_CONTROL) & 0x0200)
@ -49,7 +49,7 @@ INLINE void TMS34010_WRMEM_DWORD(tms34010_state *tms, offs_t A,UINT32 V)
FIELD WRITE MACROS
***************************************************************************/
#define WFIELDMAC(T,MASK,MAX) \
#define WFIELDMAC(MASK,MAX) \
UINT32 shift = offset & 0x0f; \
UINT32 masked_data = data & (MASK); \
UINT32 old; \
@ -58,89 +58,95 @@ INLINE void TMS34010_WRMEM_DWORD(tms34010_state *tms, offs_t A,UINT32 V)
\
if (shift >= MAX) \
{ \
old = (UINT32)TMS34010_RDMEM_DWORD(T, offset) & ~((MASK) << shift); \
TMS34010_WRMEM_DWORD(T, offset, (masked_data << shift) | old); \
old = (UINT32)TMS34010_RDMEM_DWORD(offset) & ~((MASK) << shift); \
TMS34010_WRMEM_DWORD(offset, (masked_data << shift) | old); \
} \
else \
{ \
old = (UINT32)TMS34010_RDMEM_WORD(T, offset) & ~((MASK) << shift); \
TMS34010_WRMEM_WORD(T, offset, ((masked_data & (MASK)) << shift) | old); \
old = (UINT32)TMS34010_RDMEM_WORD(offset) & ~((MASK) << shift); \
TMS34010_WRMEM_WORD(offset, ((masked_data & (MASK)) << shift) | old); \
}
#define WFIELDMAC_BIG(T,MASK,MAX) \
#define WFIELDMAC_BIG(MASK,MAX) \
UINT32 shift = offset & 0x0f; \
UINT32 masked_data = data & (MASK); \
UINT32 old; \
\
offset = TOBYTE(offset & 0xfffffff0); \
\
old = (UINT32)TMS34010_RDMEM_DWORD(T, offset) & ~(UINT32)((MASK) << shift); \
TMS34010_WRMEM_DWORD(T, offset, (UINT32)(masked_data << shift) | old); \
old = (UINT32)TMS34010_RDMEM_DWORD(offset) & ~(UINT32)((MASK) << shift); \
TMS34010_WRMEM_DWORD(offset, (UINT32)(masked_data << shift) | old); \
if (shift >= MAX) \
{ \
shift = 32 - shift; \
old = (UINT32)TMS34010_RDMEM_WORD(T, offset + 4) & ~((MASK) >> shift); \
TMS34010_WRMEM_WORD(T, offset, (masked_data >> shift) | old); \
old = (UINT32)TMS34010_RDMEM_WORD(offset + 4) & ~((MASK) >> shift); \
TMS34010_WRMEM_WORD(offset, (masked_data >> shift) | old); \
}
#define WFIELDMAC_8(T) \
#define WFIELDMAC_8() \
if (offset & 0x07) \
{ \
WFIELDMAC(T,0xff,9); \
WFIELDMAC(0xff,9); \
} \
else \
TMS34010_WRMEM(T, TOBYTE(offset), data);
#define RFIELDMAC_8(T) \
TMS34010_WRMEM(TOBYTE(offset), data);
#define RFIELDMAC_8() \
if (offset & 0x07) \
{ \
RFIELDMAC(T,0xff,9); \
RFIELDMAC(0xff,9); \
} \
else \
return TMS34010_RDMEM(T, TOBYTE(offset));
#define WFIELDMAC_32(T) \
return TMS34010_RDMEM(TOBYTE(offset));
#define WFIELDMAC_32() \
if (offset & 0x0f) \
{ \
UINT32 shift = offset&0x0f; \
UINT32 old; \
UINT32 hiword; \
offset &= 0xfffffff0; \
old = ((UINT32) TMS34010_RDMEM_DWORD (T, TOBYTE(offset ))&(0xffffffff>>(0x20-shift))); \
hiword = ((UINT32) TMS34010_RDMEM_DWORD (T, TOBYTE(offset+0x20))&(0xffffffff<<shift)); \
TMS34010_WRMEM_DWORD(T, TOBYTE(offset ),(data<< shift) |old); \
TMS34010_WRMEM_DWORD(T, TOBYTE(offset+0x20),(data>>(0x20-shift))|hiword); \
old = ((UINT32) TMS34010_RDMEM_DWORD (TOBYTE(offset ))&(0xffffffff>>(0x20-shift))); \
hiword = ((UINT32) TMS34010_RDMEM_DWORD (TOBYTE(offset+0x20))&(0xffffffff<<shift)); \
TMS34010_WRMEM_DWORD(TOBYTE(offset ),(data<< shift) |old); \
TMS34010_WRMEM_DWORD(TOBYTE(offset+0x20),(data>>(0x20-shift))|hiword); \
} \
else \
TMS34010_WRMEM_DWORD(T, TOBYTE(offset),data);
TMS34010_WRMEM_DWORD(TOBYTE(offset),data);
/***************************************************************************
FIELD READ MACROS
***************************************************************************/
#define RFIELDMAC(T,MASK,MAX) \
#define RFIELDMAC(MASK,MAX) \
UINT32 shift = offset & 0x0f; \
offset = TOBYTE(offset & 0xfffffff0); \
\
if (shift >= MAX) \
ret = (TMS34010_RDMEM_DWORD(T, offset) >> shift) & (MASK); \
ret = (TMS34010_RDMEM_DWORD(offset) >> shift) & (MASK); \
else \
ret = (TMS34010_RDMEM_WORD(T, offset) >> shift) & (MASK);
#define RFIELDMAC_BIG(T,MASK,MAX) \
ret = (TMS34010_RDMEM_WORD(offset) >> shift) & (MASK);
#define RFIELDMAC_BIG(MASK,MAX) \
UINT32 shift = offset & 0x0f; \
offset = TOBYTE(offset & 0xfffffff0); \
\
ret = (UINT32)TMS34010_RDMEM_DWORD(T, offset) >> shift; \
ret = (UINT32)TMS34010_RDMEM_DWORD(offset) >> shift; \
if (shift >= MAX) \
ret |= (TMS34010_RDMEM_WORD(T, offset + 4) << (32 - shift)); \
ret |= (TMS34010_RDMEM_WORD(offset + 4) << (32 - shift)); \
ret &= MASK;
#define RFIELDMAC_32(T) \
#define RFIELDMAC_32() \
if (offset&0x0f) \
{ \
UINT32 shift = offset&0x0f; \
offset &= 0xfffffff0; \
return (((UINT32)TMS34010_RDMEM_DWORD (T, TOBYTE(offset ))>> shift) | \
(TMS34010_RDMEM_DWORD (T, TOBYTE(offset+0x20))<<(0x20-shift)));\
return (((UINT32)TMS34010_RDMEM_DWORD (TOBYTE(offset ))>> shift) | \
(TMS34010_RDMEM_DWORD (TOBYTE(offset+0x20))<<(0x20-shift)));\
} \
else \
return TMS34010_RDMEM_DWORD(T, TOBYTE(offset));
return TMS34010_RDMEM_DWORD(TOBYTE(offset));
#endif /* __34010OPS_H__ */

1413
src/emu/cpu/tms34010/34010tbl.c
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1320
src/emu/cpu/tms34010/tms34010.c
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803
src/emu/cpu/tms34010/tms34010.h
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@ -188,7 +188,7 @@ struct tms34010_display_params
};
struct tms34010_config
struct tms340x0_config
{
UINT8 halt_on_reset; /* /HCS pin, which determines HALT state after reset */
const char *screen_tag; /* the screen operated on */
@ -202,34 +202,811 @@ struct tms34010_config
};
/* PUBLIC FUNCTIONS - 34010 */
void tms34010_get_display_params(device_t *cpu, tms34010_display_params *params);
#define MCFG_TMS340X0_CONFIG(_config) \
tms340x0_device::set_tms340x0_config(*device, &_config);
class tms34010_device : public legacy_cpu_device
class tms340x0_device : public cpu_device
{
public:
tms34010_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
tms34010_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func get_info);
// construction/destruction
tms340x0_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname);
static void set_tms340x0_config(device_t &device, const tms340x0_config *config) { downcast<tms340x0_device &>(device).m_config = config; }
void get_display_params(tms34010_display_params *params);
void tms34010_state_postload();
UINT32 tms340x0_ind16(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
UINT32 tms340x0_rgb32(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
/* Reads & writes to the 34010 I/O registers; place at 0xc0000000 */
DECLARE_WRITE16_MEMBER( io_register_w );
DECLARE_READ16_MEMBER( io_register_r );
virtual DECLARE_WRITE16_MEMBER(io_register_w) = 0;
virtual DECLARE_READ16_MEMBER(io_register_r) = 0;
DECLARE_WRITE16_MEMBER(host_w);
DECLARE_READ16_MEMBER(host_r);
TIMER_CALLBACK_MEMBER(internal_interrupt_callback);
TIMER_CALLBACK_MEMBER(scanline_callback);
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
// device_execute_interface overrides
virtual UINT32 execute_min_cycles() const { return 1; }
virtual UINT32 execute_max_cycles() const { return 10000; }
virtual UINT32 execute_input_lines() const { return 2; }
virtual void execute_run();
virtual void execute_set_input(int inputnum, int state);
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
// device_state_interface overrides
virtual void state_string_export(const device_state_entry &entry, astring &string);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
virtual UINT32 disasm_max_opcode_bytes() const { return 10; }
typedef void (tms340x0_device::*pixel_write_func)(offs_t offset, UINT32 data);
typedef UINT32 (tms340x0_device::*pixel_read_func)(offs_t offset);
typedef UINT32 (tms340x0_device::*raster_op_func)(UINT32 newpix, UINT32 oldpix);
typedef void (tms340x0_device::*wfield_func)(offs_t offset, UINT32 data);
typedef UINT32 (tms340x0_device::*rfield_func)(offs_t offset);
typedef void (tms340x0_device::*opcode_func)(UINT16 op);
typedef UINT32 (tms340x0_device::*pixel_op_func)(UINT32, UINT32, UINT32);
typedef void (tms340x0_device::*pixblt_op_func)(int, int);
typedef void (tms340x0_device::*pixblt_b_op_func)(int);
typedef void (tms340x0_device::*word_write_func)(address_space &space, offs_t offset,UINT16 data);
typedef UINT16 (tms340x0_device::*word_read_func)(address_space &space, offs_t offset);
static const wfield_func s_wfield_functions[32];
static const rfield_func s_rfield_functions[64];
static const opcode_func s_opcode_table[65536 >> 4];
static const pixel_op_func s_pixel_op_table[32];
static const UINT8 s_pixel_op_timing_table[33];
static const pixblt_op_func s_pixblt_op_table[];
static const pixblt_op_func s_pixblt_r_op_table[];
static const pixblt_b_op_func s_pixblt_b_op_table[];
static const pixblt_b_op_func s_fill_op_table[];
static const pixel_write_func s_pixel_write_ops[4][6];
static const pixel_read_func s_pixel_read_ops[6];
static const raster_op_func s_raster_ops[32];
address_space_config m_program_config;
UINT32 m_pc;
UINT32 m_ppc;
UINT32 m_st;
pixel_write_func m_pixel_write;
pixel_read_func m_pixel_read;
raster_op_func m_raster_op;
pixel_op_func m_pixel_op;
UINT32 m_pixel_op_timing;
UINT32 m_convsp;
UINT32 m_convdp;
UINT32 m_convmp;
INT32 m_gfxcycles;
UINT8 m_pixelshift;
UINT8 m_is_34020;
UINT8 m_reset_deferred;
UINT8 m_hblank_stable;
UINT8 m_external_host_access;
UINT8 m_executing;
address_space *m_program;
direct_read_data *m_direct;
const tms340x0_config *m_config;
screen_device *m_screen;
emu_timer *m_scantimer;
int m_icount;
struct XY
{
#ifdef LSB_FIRST
INT16 x;
INT16 y;
#else
INT16 y;
INT16 x;
#endif
};
/* A registers 0-15 map to regs[0]-regs[15] */
/* B registers 0-15 map to regs[30]-regs[15] */
union
{
INT32 reg;
XY xy;
} m_regs[31];
UINT16 m_IOregs[64];
UINT16 m_shiftreg[(8 * 512 * sizeof(UINT16))/2];
UINT32 TMS34010_RDMEM_DWORD(offs_t A);
void TMS34010_WRMEM_DWORD(offs_t A, UINT32 V);
void SET_ST(UINT32 st);
void RESET_ST();
UINT32 ROPCODE();
INT16 PARAM_WORD();
INT32 PARAM_LONG();
INT16 PARAM_WORD_NO_INC();
INT32 PARAM_LONG_NO_INC();
UINT32 RBYTE(offs_t offset);
void WBYTE(offs_t offset, UINT32 data);
UINT32 RLONG(offs_t offset);
void WLONG(offs_t offset, UINT32 data);
void PUSH(UINT32 data);
INT32 POP();
UINT32 read_pixel_1(offs_t offset);
UINT32 read_pixel_2(offs_t offset);
UINT32 read_pixel_4(offs_t offset);
UINT32 read_pixel_8(offs_t offset);
UINT32 read_pixel_16(offs_t offset);
UINT32 read_pixel_32(offs_t offset);
UINT32 read_pixel_shiftreg(offs_t offset);
void write_pixel_1(offs_t offset, UINT32 data);
void write_pixel_2(offs_t offset, UINT32 data);
void write_pixel_4(offs_t offset, UINT32 data);
void write_pixel_8(offs_t offset, UINT32 data);
void write_pixel_16(offs_t offset, UINT32 data);
void write_pixel_32(offs_t offset, UINT32 data);
void write_pixel_t_1(offs_t offset, UINT32 data);
void write_pixel_t_2(offs_t offset, UINT32 data);
void write_pixel_t_4(offs_t offset, UINT32 data);
void write_pixel_t_8(offs_t offset, UINT32 data);
void write_pixel_t_16(offs_t offset, UINT32 data);
void write_pixel_t_32(offs_t offset, UINT32 data);
void write_pixel_r_1(offs_t offset, UINT32 data);
void write_pixel_r_2(offs_t offset, UINT32 data);
void write_pixel_r_4(offs_t offset, UINT32 data);
void write_pixel_r_8(offs_t offset, UINT32 data);
void write_pixel_r_16(offs_t offset, UINT32 data);
void write_pixel_r_32(offs_t offset, UINT32 data);
void write_pixel_r_t_1(offs_t offset, UINT32 data);
void write_pixel_r_t_2(offs_t offset, UINT32 data);
void write_pixel_r_t_4(offs_t offset, UINT32 data);
void write_pixel_r_t_8(offs_t offset, UINT32 data);
void write_pixel_r_t_16(offs_t offset, UINT32 data);
void write_pixel_r_t_32(offs_t offset, UINT32 data);
void write_pixel_shiftreg(offs_t offset, UINT32 data);
UINT32 raster_op_1(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_2(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_3(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_4(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_5(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_6(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_7(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_8(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_9(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_10(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_11(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_12(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_13(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_14(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_15(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_16(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_17(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_18(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_19(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_20(UINT32 newpix, UINT32 oldpix);
UINT32 raster_op_21(UINT32 newpix, UINT32 oldpix);
void wfield_01(offs_t offset, UINT32 data);
void wfield_02(offs_t offset, UINT32 data);
void wfield_03(offs_t offset, UINT32 data);
void wfield_04(offs_t offset, UINT32 data);
void wfield_05(offs_t offset, UINT32 data);
void wfield_06(offs_t offset, UINT32 data);
void wfield_07(offs_t offset, UINT32 data);
void wfield_08(offs_t offset, UINT32 data);
void wfield_09(offs_t offset, UINT32 data);
void wfield_10(offs_t offset, UINT32 data);
void wfield_11(offs_t offset, UINT32 data);
void wfield_12(offs_t offset, UINT32 data);
void wfield_13(offs_t offset, UINT32 data);
void wfield_14(offs_t offset, UINT32 data);
void wfield_15(offs_t offset, UINT32 data);
void wfield_16(offs_t offset, UINT32 data);
void wfield_17(offs_t offset, UINT32 data);
void wfield_18(offs_t offset, UINT32 data);
void wfield_19(offs_t offset, UINT32 data);
void wfield_20(offs_t offset, UINT32 data);
void wfield_21(offs_t offset, UINT32 data);
void wfield_22(offs_t offset, UINT32 data);
void wfield_23(offs_t offset, UINT32 data);
void wfield_24(offs_t offset, UINT32 data);
void wfield_25(offs_t offset, UINT32 data);
void wfield_26(offs_t offset, UINT32 data);
void wfield_27(offs_t offset, UINT32 data);
void wfield_28(offs_t offset, UINT32 data);
void wfield_29(offs_t offset, UINT32 data);
void wfield_30(offs_t offset, UINT32 data);
void wfield_31(offs_t offset, UINT32 data);
void wfield_32(offs_t offset, UINT32 data);
UINT32 rfield_z_01(offs_t offset);
UINT32 rfield_z_02(offs_t offset);
UINT32 rfield_z_03(offs_t offset);
UINT32 rfield_z_04(offs_t offset);
UINT32 rfield_z_05(offs_t offset);
UINT32 rfield_z_06(offs_t offset);
UINT32 rfield_z_07(offs_t offset);
UINT32 rfield_z_08(offs_t offset);
UINT32 rfield_z_09(offs_t offset);
UINT32 rfield_z_10(offs_t offset);
UINT32 rfield_z_11(offs_t offset);
UINT32 rfield_z_12(offs_t offset);
UINT32 rfield_z_13(offs_t offset);
UINT32 rfield_z_14(offs_t offset);
UINT32 rfield_z_15(offs_t offset);
UINT32 rfield_z_16(offs_t offset);
UINT32 rfield_z_17(offs_t offset);
UINT32 rfield_z_18(offs_t offset);
UINT32 rfield_z_19(offs_t offset);
UINT32 rfield_z_20(offs_t offset);
UINT32 rfield_z_21(offs_t offset);
UINT32 rfield_z_22(offs_t offset);
UINT32 rfield_z_23(offs_t offset);
UINT32 rfield_z_24(offs_t offset);
UINT32 rfield_z_25(offs_t offset);
UINT32 rfield_z_26(offs_t offset);
UINT32 rfield_z_27(offs_t offset);
UINT32 rfield_z_28(offs_t offset);
UINT32 rfield_z_29(offs_t offset);
UINT32 rfield_z_30(offs_t offset);
UINT32 rfield_z_31(offs_t offset);
UINT32 rfield_32(offs_t offset);
UINT32 rfield_s_01(offs_t offset);
UINT32 rfield_s_02(offs_t offset);
UINT32 rfield_s_03(offs_t offset);
UINT32 rfield_s_04(offs_t offset);
UINT32 rfield_s_05(offs_t offset);
UINT32 rfield_s_06(offs_t offset);
UINT32 rfield_s_07(offs_t offset);
UINT32 rfield_s_08(offs_t offset);
UINT32 rfield_s_09(offs_t offset);
UINT32 rfield_s_10(offs_t offset);
UINT32 rfield_s_11(offs_t offset);
UINT32 rfield_s_12(offs_t offset);
UINT32 rfield_s_13(offs_t offset);
UINT32 rfield_s_14(offs_t offset);
UINT32 rfield_s_15(offs_t offset);
UINT32 rfield_s_16(offs_t offset);
UINT32 rfield_s_17(offs_t offset);
UINT32 rfield_s_18(offs_t offset);
UINT32 rfield_s_19(offs_t offset);
UINT32 rfield_s_20(offs_t offset);
UINT32 rfield_s_21(offs_t offset);
UINT32 rfield_s_22(offs_t offset);
UINT32 rfield_s_23(offs_t offset);
UINT32 rfield_s_24(offs_t offset);
UINT32 rfield_s_25(offs_t offset);
UINT32 rfield_s_26(offs_t offset);
UINT32 rfield_s_27(offs_t offset);
UINT32 rfield_s_28(offs_t offset);
UINT32 rfield_s_29(offs_t offset);
UINT32 rfield_s_30(offs_t offset);
UINT32 rfield_s_31(offs_t offset);
void unimpl(UINT16 op);
void pixblt_l_l(UINT16 op); /* 0f00 */
void pixblt_l_xy(UINT16 op); /* 0f20 */
void pixblt_xy_l(UINT16 op); /* 0f40 */
void pixblt_xy_xy(UINT16 op); /* 0f60 */
void pixblt_b_l(UINT16 op); /* 0f80 */
void pixblt_b_xy(UINT16 op); /* 0fa0 */
void fill_l(UINT16 op); /* 0fc0 */
void fill_xy(UINT16 op); /* 0fe0 */
void line(UINT16 op); /* df10/df90 */
void add_xy_a(UINT16 op); /* e000/e100 */
void add_xy_b(UINT16 op); /* e000/e100 */
void sub_xy_a(UINT16 op); /* e200/e300 */
void sub_xy_b(UINT16 op); /* e200/e300 */
void cmp_xy_a(UINT16 op); /* e400/e500 */
void cmp_xy_b(UINT16 op); /* e400/e500 */
void cpw_a(UINT16 op); /* e600/e700 */
void cpw_b(UINT16 op); /* e600/e700 */
void cvxyl_a(UINT16 op); /* e800/e900 */
void cvxyl_b(UINT16 op); /* e800/e900 */
void movx_a(UINT16 op); /* ec00/ed00 */
void movx_b(UINT16 op); /* ec00/ed00 */
void movy_a(UINT16 op); /* ee00/ef00 */
void movy_b(UINT16 op); /* ee00/ef00 */
void pixt_ri_a(UINT16 op); /* f800/f900 */
void pixt_ri_b(UINT16 op); /* f800/f900 */
void pixt_rixy_a(UINT16 op); /* f000/f100 */
void pixt_rixy_b(UINT16 op); /* f000/f100 */
void pixt_ir_a(UINT16 op); /* fa00/fb00 */
void pixt_ir_b(UINT16 op); /* fa00/fb00 */
void pixt_ii_a(UINT16 op); /* fc00/fd00 */
void pixt_ii_b(UINT16 op); /* fc00/fd00 */
void pixt_ixyr_a(UINT16 op); /* f200/f300 */
void pixt_ixyr_b(UINT16 op); /* f200/f300 */
void pixt_ixyixy_a(UINT16 op); /* f400/f500 */
void pixt_ixyixy_b(UINT16 op); /* f400/f500 */
void drav_a(UINT16 op); /* f600/f700 */
void drav_b(UINT16 op); /* f600/f700 */
void abs_a(UINT16 op); /* 0380 */
void abs_b(UINT16 op); /* 0390 */
void add_a(UINT16 op); /* 4000/4100 */
void add_b(UINT16 op); /* 4000/4100 */
void addc_a(UINT16 op); /* 4200/4200 */
void addc_b(UINT16 op); /* 4200/4200 */
void addi_w_a(UINT16 op); /* 0b00 */
void addi_w_b(UINT16 op); /* 0b10 */
void addi_l_a(UINT16 op); /* 0b20 */
void addi_l_b(UINT16 op); /* 0b30 */
void addk_a(UINT16 op); /* 1000-1300 */
void addk_b(UINT16 op); /* 1000-1300 */
void and_a(UINT16 op); /* 5000/5100 */
void and_b(UINT16 op); /* 5000/5100 */
void andi_a(UINT16 op); /* 0b80 */
void andi_b(UINT16 op); /* 0b90 */
void andn_a(UINT16 op); /* 5200-5300 */
void andn_b(UINT16 op); /* 5200-5300 */
void btst_k_a(UINT16 op); /* 1c00-1f00 */
void btst_k_b(UINT16 op); /* 1c00-1f00 */
void btst_r_a(UINT16 op); /* 4a00-4b00 */
void btst_r_b(UINT16 op); /* 4a00-4b00 */
void clrc(UINT16 op); /* 0320 */
void cmp_a(UINT16 op); /* 4800/4900 */
void cmp_b(UINT16 op); /* 4800/4900 */
void cmpi_w_a(UINT16 op); /* 0b40 */
void cmpi_w_b(UINT16 op); /* 0b50 */
void cmpi_l_a(UINT16 op); /* 0b60 */
void cmpi_l_b(UINT16 op); /* 0b70 */
void dint(UINT16 op);
void divs_a(UINT16 op); /* 5800/5900 */
void divs_b(UINT16 op); /* 5800/5900 */
void divu_a(UINT16 op); /* 5a00/5b00 */
void divu_b(UINT16 op); /* 5a00/5b00 */
void eint(UINT16 op);
void exgf0_a(UINT16 op); /* d500 */
void exgf0_b(UINT16 op); /* d510 */
void exgf1_a(UINT16 op); /* d700 */
void exgf1_b(UINT16 op); /* d710 */
void lmo_a(UINT16 op); /* 6a00/6b00 */
void lmo_b(UINT16 op); /* 6a00/6b00 */
void mmfm_a(UINT16 op); /* 09a0 */
void mmfm_b(UINT16 op); /* 09b0 */
void mmtm_a(UINT16 op); /* 0980 */
void mmtm_b(UINT16 op); /* 0990 */
void mods_a(UINT16 op); /* 6c00/6d00 */
void mods_b(UINT16 op); /* 6c00/6d00 */
void modu_a(UINT16 op); /* 6e00/6f00 */
void modu_b(UINT16 op); /* 6e00/6f00 */
void mpys_a(UINT16 op); /* 5c00/5d00 */
void mpys_b(UINT16 op); /* 5c00/5d00 */
void mpyu_a(UINT16 op); /* 5e00/5e00 */
void mpyu_b(UINT16 op); /* 5e00/5f00 */
void neg_a(UINT16 op); /* 03a0 */
void neg_b(UINT16 op); /* 03b0 */
void negb_a(UINT16 op); /* 03c0 */
void negb_b(UINT16 op); /* 03d0 */
void nop(UINT16 op); /* 0300 */
void not_a(UINT16 op); /* 03e0 */
void not_b(UINT16 op); /* 03f0 */
void or_a(UINT16 op); /* 5400-5500 */
void or_b(UINT16 op); /* 5400-5500 */
void ori_a(UINT16 op); /* 0ba0 */
void ori_b(UINT16 op); /* 0bb0 */
void rl_k_a(UINT16 op); /* 3000-3300 */
void rl_k_b(UINT16 op); /* 3000-3300 */
void rl_r_a(UINT16 op); /* 6800/6900 */
void rl_r_b(UINT16 op); /* 6800/6900 */
void setc(UINT16 op); /* 0de0 */
void setf0(UINT16 op);
void setf1(UINT16 op);
void sext0_a(UINT16 op); /* 0500 */
void sext0_b(UINT16 op); /* 0510 */
void sext1_a(UINT16 op); /* 0700 */
void sext1_b(UINT16 op); /* 0710 */
void sla_k_a(UINT16 op); /* 2000-2300 */
void sla_k_b(UINT16 op); /* 2000-2300 */
void sla_r_a(UINT16 op); /* 6000/6100 */
void sla_r_b(UINT16 op); /* 6000/6100 */
void sll_k_a(UINT16 op); /* 2400-2700 */
void sll_k_b(UINT16 op); /* 2400-2700 */
void sll_r_a(UINT16 op); /* 6200/6300 */
void sll_r_b(UINT16 op); /* 6200/6300 */
void sra_k_a(UINT16 op); /* 2800-2b00 */
void sra_k_b(UINT16 op); /* 2800-2b00 */
void sra_r_a(UINT16 op); /* 6400/6500 */
void sra_r_b(UINT16 op); /* 6400/6500 */
void srl_k_a(UINT16 op); /* 2c00-2f00 */
void srl_k_b(UINT16 op); /* 2c00-2f00 */
void srl_r_a(UINT16 op); /* 6600/6700 */
void srl_r_b(UINT16 op); /* 6600/6700 */
void sub_a(UINT16 op); /* 4400/4500 */
void sub_b(UINT16 op); /* 4400/4500 */
void subb_a(UINT16 op); /* 4600/4700 */
void subb_b(UINT16 op); /* 4600/4700 */
void subi_w_a(UINT16 op); /* 0be0 */
void subi_w_b(UINT16 op); /* 0bf0 */
void subi_l_a(UINT16 op); /* 0d00 */
void subi_l_b(UINT16 op); /* 0d10 */
void subk_a(UINT16 op); /* 1400-1700 */
void subk_b(UINT16 op); /* 1400-1700 */
void xor_a(UINT16 op); /* 5600-5700 */
void xor_b(UINT16 op); /* 5600-5700 */
void xori_a(UINT16 op); /* 0bc0 */
void xori_b(UINT16 op); /* 0bd0 */
void zext0_a(UINT16 op); /* 0520 */
void zext0_b(UINT16 op); /* 0530 */
void zext1_a(UINT16 op); /* 0720 */
void zext1_b(UINT16 op); /* 0720 */
void movi_w_a(UINT16 op);
void movi_w_b(UINT16 op);
void movi_l_a(UINT16 op);
void movi_l_b(UINT16 op);
void movk_a(UINT16 op);
void movk_b(UINT16 op);
void movb_rn_a(UINT16 op); /* 8c00-8d00 */
void movb_rn_b(UINT16 op); /* 8c00-8d00 */
void movb_nr_a(UINT16 op); /* 8e00-8f00 */
void movb_nr_b(UINT16 op); /* 8e00-8f00 */
void movb_nn_a(UINT16 op); /* 9c00-9d00 */
void movb_nn_b(UINT16 op); /* 9c00-9d00 */
void movb_r_no_a(UINT16 op); /* ac00-ad00 */
void movb_r_no_b(UINT16 op); /* ac00-ad00 */
void movb_no_r_a(UINT16 op); /* ae00-af00 */
void movb_no_r_b(UINT16 op); /* ae00-af00 */
void movb_no_no_a(UINT16 op); /* bc00-bd00 */
void movb_no_no_b(UINT16 op); /* bc00-bd00 */
void movb_ra_a(UINT16 op);
void movb_ra_b(UINT16 op);
void movb_ar_a(UINT16 op);
void movb_ar_b(UINT16 op);
void movb_aa(UINT16 op);
void move_rr_a(UINT16 op); /* 4c00/d00 */
void move_rr_b(UINT16 op); /* 4c00/d00 */
void move_rr_ax(UINT16 op); /* 4e00/f00 */
void move_rr_bx(UINT16 op); /* 4e00/f00 */
void move0_rn_a(UINT16 op); /* 8000 */
void move0_rn_b(UINT16 op);
void move1_rn_a(UINT16 op);
void move1_rn_b(UINT16 op);
void move0_r_dn_a(UINT16 op); /* a000 */
void move0_r_dn_b(UINT16 op);
void move1_r_dn_a(UINT16 op);
void move1_r_dn_b(UINT16 op);
void move0_r_ni_a(UINT16 op); /* 9000 */
void move0_r_ni_b(UINT16 op);
void move1_r_ni_a(UINT16 op);
void move1_r_ni_b(UINT16 op);
void move0_nr_a(UINT16 op); /* 8400-500 */
void move0_nr_b(UINT16 op); /* 8400-500 */
void move1_nr_a(UINT16 op); /* 8600-700 */
void move1_nr_b(UINT16 op); /* 8600-700 */
void move0_dn_r_a(UINT16 op); /* A400-500 */
void move0_dn_r_b(UINT16 op); /* A400-500 */
void move1_dn_r_a(UINT16 op); /* A600-700 */
void move1_dn_r_b(UINT16 op); /* A600-700 */
void move0_ni_r_a(UINT16 op); /* 9400-500 */
void move0_ni_r_b(UINT16 op); /* 9400-500 */
void move1_ni_r_a(UINT16 op); /* 9600-700 */
void move1_ni_r_b(UINT16 op); /* 9600-700 */
void move0_nn_a(UINT16 op); /* 8800 */
void move0_nn_b(UINT16 op);
void move1_nn_a(UINT16 op);
void move1_nn_b(UINT16 op);
void move0_dn_dn_a(UINT16 op); /* a800 */
void move0_dn_dn_b(UINT16 op);
void move1_dn_dn_a(UINT16 op);
void move1_dn_dn_b(UINT16 op);
void move0_ni_ni_a(UINT16 op); /* 9800 */
void move0_ni_ni_b(UINT16 op);
void move1_ni_ni_a(UINT16 op);
void move1_ni_ni_b(UINT16 op);
void move0_r_no_a(UINT16 op); /* b000 */
void move0_r_no_b(UINT16 op);
void move1_r_no_a(UINT16 op);
void move1_r_no_b(UINT16 op);
void move0_no_r_a(UINT16 op); /* b400 */
void move0_no_r_b(UINT16 op);
void move1_no_r_a(UINT16 op);
void move1_no_r_b(UINT16 op);
void move0_no_ni_a(UINT16 op); /* d000 */
void move0_no_ni_b(UINT16 op);
void move1_no_ni_a(UINT16 op);
void move1_no_ni_b(UINT16 op);
void move0_no_no_a(UINT16 op); /* b800 */
void move0_no_no_b(UINT16 op);
void move1_no_no_a(UINT16 op);
void move1_no_no_b(UINT16 op);
void move0_ra_a(UINT16 op);
void move0_ra_b(UINT16 op);
void move1_ra_a(UINT16 op);
void move1_ra_b(UINT16 op);
void move0_ar_a(UINT16 op);
void move0_ar_b(UINT16 op);
void move1_ar_a(UINT16 op);
void move1_ar_b(UINT16 op);
void move0_a_ni_a(UINT16 op); /* d400 */
void move0_a_ni_b(UINT16 op); /* d410 */
void move1_a_ni_a(UINT16 op); /* d600 */
void move1_a_ni_b(UINT16 op); /* d610 */
void move0_aa(UINT16 op); /* 05c0 */
void move1_aa(UINT16 op); /* 07c0 */
void call_a(UINT16 op); /* 0920 */
void call_b(UINT16 op); /* 0930 */
void callr(UINT16 op); /* 0d3f */
void calla(UINT16 op); /* 0d5f */
void dsj_a(UINT16 op); /* 0d80 */
void dsj_b(UINT16 op); /* 0d90 */
void dsjeq_a(UINT16 op); /* 0da0 */
void dsjeq_b(UINT16 op); /* 0db0 */
void dsjne_a(UINT16 op); /* 0dc0 */
void dsjne_b(UINT16 op); /* 0dd0 */
void dsjs_a(UINT16 op);
void dsjs_b(UINT16 op);
void emu(UINT16 op); /* 0100 */
void exgpc_a(UINT16 op); /* 0120 */
void exgpc_b(UINT16 op); /* 0130 */
void getpc_a(UINT16 op); /* 0140 */
void getpc_b(UINT16 op); /* 0150 */
void getst_a(UINT16 op); /* 0180 */
void getst_b(UINT16 op); /* 0190 */
void j_UC_0(UINT16 op);
void j_UC_8(UINT16 op);
void j_UC_x(UINT16 op);
void j_P_0(UINT16 op);
void j_P_8(UINT16 op);
void j_P_x(UINT16 op);
void j_LS_0(UINT16 op);
void j_LS_8(UINT16 op);
void j_LS_x(UINT16 op);
void j_HI_0(UINT16 op);
void j_HI_8(UINT16 op);
void j_HI_x(UINT16 op);
void j_LT_0(UINT16 op);
void j_LT_8(UINT16 op);
void j_LT_x(UINT16 op);
void j_GE_0(UINT16 op);
void j_GE_8(UINT16 op);
void j_GE_x(UINT16 op);
void j_LE_0(UINT16 op);
void j_LE_8(UINT16 op);
void j_LE_x(UINT16 op);
void j_GT_0(UINT16 op);
void j_GT_8(UINT16 op);
void j_GT_x(UINT16 op);
void j_C_0(UINT16 op);
void j_C_8(UINT16 op);
void j_C_x(UINT16 op);
void j_NC_0(UINT16 op);
void j_NC_8(UINT16 op);
void j_NC_x(UINT16 op);
void j_EQ_0(UINT16 op);
void j_EQ_8(UINT16 op);
void j_EQ_x(UINT16 op);
void j_NE_0(UINT16 op);
void j_NE_8(UINT16 op);
void j_NE_x(UINT16 op);
void j_V_0(UINT16 op);
void j_V_8(UINT16 op);
void j_V_x(UINT16 op);
void j_NV_0(UINT16 op);
void j_NV_8(UINT16 op);
void j_NV_x(UINT16 op);
void j_N_0(UINT16 op);
void j_N_8(UINT16 op);
void j_N_x(UINT16 op);
void j_NN_0(UINT16 op);
void j_NN_8(UINT16 op);
void j_NN_x(UINT16 op);
void jump_a(UINT16 op); /* 0160 */
void jump_b(UINT16 op); /* 0170 */
void popst(UINT16 op); /* 01c0 */
void pushst(UINT16 op); /* 01e0 */
void putst_a(UINT16 op); /* 01a0 */
void putst_b(UINT16 op); /* 01b0 */
void reti(UINT16 op); /* 0940 */
void rets(UINT16 op); /* 0960/70 */
void rev_a(UINT16 op); /* 0020 */
void rev_b(UINT16 op); /* 0030 */
void trap(UINT16 op); /* 0900/10 */
void addxyi_a(UINT16 op);
void addxyi_b(UINT16 op);
void blmove(UINT16 op);
void cexec_l(UINT16 op);
void cexec_s(UINT16 op);
void clip(UINT16 op);
void cmovcg_a(UINT16 op);
void cmovcg_b(UINT16 op);
void cmovcm_f(UINT16 op);
void cmovcm_b(UINT16 op);
void cmovgc_a(UINT16 op);
void cmovgc_b(UINT16 op);
void cmovgc_a_s(UINT16 op);
void cmovgc_b_s(UINT16 op);
void cmovmc_f(UINT16 op);
void cmovmc_f_va(UINT16 op);
void cmovmc_f_vb(UINT16 op);
void cmovmc_b(UINT16 op);
void cmp_k_a(UINT16 op);
void cmp_k_b(UINT16 op);
void cvdxyl_a(UINT16 op);
void cvdxyl_b(UINT16 op);
void cvmxyl_a(UINT16 op);
void cvmxyl_b(UINT16 op);
void cvsxyl_a(UINT16 op);
void cvsxyl_b(UINT16 op);
void exgps_a(UINT16 op);
void exgps_b(UINT16 op);
void fline(UINT16 op);
void fpixeq(UINT16 op);
void fpixne(UINT16 op);
void getps_a(UINT16 op);
void getps_b(UINT16 op);
void idle(UINT16 op);
void linit(UINT16 op);
void mwait(UINT16 op);
void pfill_xy(UINT16 op);
void pixblt_l_m_l(UINT16 op);
void retm(UINT16 op);
void rmo_a(UINT16 op);
void rmo_b(UINT16 op);
void rpix_a(UINT16 op);
void rpix_b(UINT16 op);
void setcdp(UINT16 op);
void setcmp(UINT16 op);
void setcsp(UINT16 op);
void swapf_a(UINT16 op);
void swapf_b(UINT16 op);
void tfill_xy(UINT16 op);
void trapl(UINT16 op);
void vblt_b_l(UINT16 op);
void vfill_l(UINT16 op);
void vlcol(UINT16 op);
int apply_window(const char *inst_name,int srcbpp, UINT32 *srcaddr, XY *dst, int *dx, int *dy);
int compute_fill_cycles(int left_partials, int right_partials, int full_words, int op_timing);
int compute_pixblt_cycles(int left_partials, int right_partials, int full_words, int op_timing);
int compute_pixblt_b_cycles(int left_partials, int right_partials, int full_words, int rows, int op_timing, int bpp);
void memory_w(address_space &space, offs_t offset,UINT16 data);
UINT16 memory_r(address_space &space, offs_t offset);
void shiftreg_w(address_space &space, offs_t offset, UINT16 data);
UINT16 shiftreg_r(address_space &space, offs_t offset);
UINT16 dummy_shiftreg_r(address_space &space, offs_t offset);
UINT32 pixel_op00(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op01(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op02(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op03(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op04(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op05(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op06(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op07(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op08(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op09(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op10(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op11(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op12(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op13(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op14(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op15(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op16(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op17(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op18(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op19(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op20(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
UINT32 pixel_op21(UINT32 dstpix, UINT32 mask, UINT32 srcpix);
void pixblt_1_op0(int src_is_linear, int dst_is_linear);
void pixblt_2_op0(int src_is_linear, int dst_is_linear);
void pixblt_4_op0(int src_is_linear, int dst_is_linear);
void pixblt_8_op0(int src_is_linear, int dst_is_linear);
void pixblt_16_op0(int src_is_linear, int dst_is_linear);
void pixblt_r_1_op0(int src_is_linear, int dst_is_linear);
void pixblt_r_2_op0(int src_is_linear, int dst_is_linear);
void pixblt_r_4_op0(int src_is_linear, int dst_is_linear);
void pixblt_r_8_op0(int src_is_linear, int dst_is_linear);
void pixblt_r_16_op0(int src_is_linear, int dst_is_linear);
void pixblt_b_1_op0(int dst_is_linear);
void pixblt_b_2_op0(int dst_is_linear);
void pixblt_b_4_op0(int dst_is_linear);
void pixblt_b_8_op0(int dst_is_linear);
void pixblt_b_16_op0(int dst_is_linear);
void fill_1_op0(int dst_is_linear);
void fill_2_op0(int dst_is_linear);
void fill_4_op0(int dst_is_linear);
void fill_8_op0(int dst_is_linear);
void fill_16_op0(int dst_is_linear);
void pixblt_1_op0_trans(int src_is_linear, int dst_is_linear);
void pixblt_2_op0_trans(int src_is_linear, int dst_is_linear);
void pixblt_4_op0_trans(int src_is_linear, int dst_is_linear);
void pixblt_8_op0_trans(int src_is_linear, int dst_is_linear);
void pixblt_16_op0_trans(int src_is_linear, int dst_is_linear);
void pixblt_r_1_op0_trans(int src_is_linear, int dst_is_linear);
void pixblt_r_2_op0_trans(int src_is_linear, int dst_is_linear);
void pixblt_r_4_op0_trans(int src_is_linear, int dst_is_linear);
void pixblt_r_8_op0_trans(int src_is_linear, int dst_is_linear);
void pixblt_r_16_op0_trans(int src_is_linear, int dst_is_linear);
void pixblt_b_1_op0_trans(int dst_is_linear);
void pixblt_b_2_op0_trans(int dst_is_linear);
void pixblt_b_4_op0_trans(int dst_is_linear);
void pixblt_b_8_op0_trans(int dst_is_linear);
void pixblt_b_16_op0_trans(int dst_is_linear);
void fill_1_op0_trans(int dst_is_linear);
void fill_2_op0_trans(int dst_is_linear);
void fill_4_op0_trans(int dst_is_linear);
void fill_8_op0_trans(int dst_is_linear);
void fill_16_op0_trans(int dst_is_linear);
void pixblt_1_opx(int src_is_linear, int dst_is_linear);
void pixblt_2_opx(int src_is_linear, int dst_is_linear);
void pixblt_4_opx(int src_is_linear, int dst_is_linear);
void pixblt_8_opx(int src_is_linear, int dst_is_linear);
void pixblt_16_opx(int src_is_linear, int dst_is_linear);
void pixblt_r_1_opx(int src_is_linear, int dst_is_linear);
void pixblt_r_2_opx(int src_is_linear, int dst_is_linear);
void pixblt_r_4_opx(int src_is_linear, int dst_is_linear);
void pixblt_r_8_opx(int src_is_linear, int dst_is_linear);
void pixblt_r_16_opx(int src_is_linear, int dst_is_linear);
void pixblt_b_1_opx(int dst_is_linear);
void pixblt_b_2_opx(int dst_is_linear);
void pixblt_b_4_opx(int dst_is_linear);
void pixblt_b_8_opx(int dst_is_linear);
void pixblt_b_16_opx(int dst_is_linear);
void fill_1_opx(int dst_is_linear);
void fill_2_opx(int dst_is_linear);
void fill_4_opx(int dst_is_linear);
void fill_8_opx(int dst_is_linear);
void fill_16_opx(int dst_is_linear);
void pixblt_1_opx_trans(int src_is_linear, int dst_is_linear);
void pixblt_2_opx_trans(int src_is_linear, int dst_is_linear);
void pixblt_4_opx_trans(int src_is_linear, int dst_is_linear);
void pixblt_8_opx_trans(int src_is_linear, int dst_is_linear);
void pixblt_16_opx_trans(int src_is_linear, int dst_is_linear);
void pixblt_r_1_opx_trans(int src_is_linear, int dst_is_linear);
void pixblt_r_2_opx_trans(int src_is_linear, int dst_is_linear);
void pixblt_r_4_opx_trans(int src_is_linear, int dst_is_linear);
void pixblt_r_8_opx_trans(int src_is_linear, int dst_is_linear);
void pixblt_r_16_opx_trans(int src_is_linear, int dst_is_linear);
void pixblt_b_1_opx_trans(int dst_is_linear);
void pixblt_b_2_opx_trans(int dst_is_linear);
void pixblt_b_4_opx_trans(int dst_is_linear);
void pixblt_b_8_opx_trans(int dst_is_linear);
void pixblt_b_16_opx_trans(int dst_is_linear);
void fill_1_opx_trans(int dst_is_linear);
void fill_2_opx_trans(int dst_is_linear);
void fill_4_opx_trans(int dst_is_linear);
void fill_8_opx_trans(int dst_is_linear);
void fill_16_opx_trans(int dst_is_linear);
void check_interrupt();
void set_pixel_function();
void set_raster_op();
};
class tms34010_device : public tms340x0_device
{
public:
tms34010_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
/* Reads & writes to the 34010 I/O registers; place at 0xc0000000 */
virtual DECLARE_WRITE16_MEMBER( io_register_w );
virtual DECLARE_READ16_MEMBER( io_register_r );
protected:
virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 8 - 1) / 8; }
virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 8); }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
};
extern const device_type TMS34010;
class tms34020_device : public tms34010_device
class tms34020_device : public tms340x0_device
{
public:
tms34020_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
tms34020_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
/* Reads & writes to the 34010 I/O registers; place at 0xc0000000 */
DECLARE_WRITE16_MEMBER( io_register_w );
DECLARE_READ16_MEMBER( io_register_r );
virtual DECLARE_WRITE16_MEMBER( io_register_w );
virtual DECLARE_READ16_MEMBER( io_register_r );
protected:
virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 4 - 1) / 4; }
virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 4); }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
};
extern const device_type TMS34020;

4
src/mame/drivers/artmagic.c
View File

@ -475,7 +475,7 @@ ADDRESS_MAP_END
*
*************************************/
static const tms34010_config tms_config =
static const tms340x0_config tms_config =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
@ -827,7 +827,7 @@ static MACHINE_CONFIG_START( artmagic, artmagic_state )
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_CPU_ADD("tms", TMS34010, MASTER_CLOCK_40MHz)
MCFG_CPU_CONFIG(tms_config)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(tms_map)
MCFG_QUANTUM_TIME(attotime::from_hz(6000))

4
src/mame/drivers/btoads.c
View File

@ -299,7 +299,7 @@ INPUT_PORTS_END
*
*************************************/
static const tms34010_config tms_config =
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -323,7 +323,7 @@ static const tms34010_config tms_config =
static MACHINE_CONFIG_START( btoads, btoads_state )
MCFG_CPU_ADD("maincpu", TMS34020, CPU_CLOCK/2)
MCFG_CPU_CONFIG(tms_config)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_CPU_ADD("audiocpu", Z80, SOUND_CLOCK/4)

8
src/mame/drivers/coolpool.c
View File

@ -794,7 +794,7 @@ INPUT_PORTS_END
*
*************************************/
static const tms34010_config tms_config_amerdart =
static const tms340x0_config tms_config_amerdart =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -808,7 +808,7 @@ static const tms34010_config tms_config_amerdart =
};
static const tms34010_config tms_config_coolpool =
static const tms340x0_config tms_config_coolpool =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -833,7 +833,7 @@ static MACHINE_CONFIG_START( amerdart, coolpool_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
MCFG_CPU_CONFIG(tms_config_amerdart)
MCFG_TMS340X0_CONFIG(tms_config_amerdart)
MCFG_CPU_PROGRAM_MAP(amerdart_map)
MCFG_CPU_ADD("dsp", TMS32015, XTAL_40MHz/2)
@ -864,7 +864,7 @@ static MACHINE_CONFIG_START( coolpool, coolpool_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
MCFG_CPU_CONFIG(tms_config_coolpool)
MCFG_TMS340X0_CONFIG(tms_config_coolpool)
MCFG_CPU_PROGRAM_MAP(coolpool_map)
MCFG_CPU_ADD("dsp", TMS32026,XTAL_40MHz)

8
src/mame/drivers/exterm.c
View File

@ -400,7 +400,7 @@ INPUT_PORTS_END
*
*************************************/
static const tms34010_config master_config =
static const tms340x0_config master_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -413,7 +413,7 @@ static const tms34010_config master_config =
exterm_from_shiftreg_master /* read from shiftreg function */
};
static const tms34010_config slave_config =
static const tms340x0_config slave_config =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
@ -438,11 +438,11 @@ static MACHINE_CONFIG_START( exterm, exterm_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, 40000000)
MCFG_CPU_CONFIG(master_config)
MCFG_TMS340X0_CONFIG(master_config)
MCFG_CPU_PROGRAM_MAP(master_map)
MCFG_CPU_ADD("slave", TMS34010, 40000000)
MCFG_CPU_CONFIG(slave_config)
MCFG_TMS340X0_CONFIG(slave_config)
MCFG_CPU_PROGRAM_MAP(slave_map)
MCFG_CPU_ADD("audiocpu", M6502, 2000000)

18
src/mame/drivers/harddriv.c
View File

@ -338,7 +338,7 @@ Notes:
*************************************/
/* used on the medium-resolution driver boards */
static const tms34010_config gsp_config_driver =
static const tms340x0_config gsp_config_driver =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
@ -353,7 +353,7 @@ static const tms34010_config gsp_config_driver =
/* used on the low-resolution multisync boards for harddrivc, racedrivc, steeltal */
static const tms34010_config gsp_config_multisync =
static const tms340x0_config gsp_config_multisync =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
@ -368,7 +368,7 @@ static const tms34010_config gsp_config_multisync =
/* used on the low-resolution multisync board for stunrun */
static const tms34010_config gsp_config_multisync_stunrun =
static const tms340x0_config gsp_config_multisync_stunrun =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
@ -382,7 +382,7 @@ static const tms34010_config gsp_config_multisync_stunrun =
};
static const tms34010_config msp_config =
static const tms340x0_config msp_config =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
@ -1296,7 +1296,7 @@ static MACHINE_CONFIG_START( driver_nomsp, harddriv_state )
MCFG_CPU_ADD("gsp", TMS34010, HARDDRIV_GSP_CLOCK)
MCFG_CPU_PROGRAM_MAP(driver_gsp_map)
MCFG_CPU_CONFIG(gsp_config_driver)
MCFG_TMS340X0_CONFIG(gsp_config_driver)
MCFG_QUANTUM_TIME(attotime::from_hz(30000))
@ -1328,7 +1328,7 @@ static MACHINE_CONFIG_DERIVED( driver_msp, driver_nomsp )
/* basic machine hardware */
MCFG_CPU_ADD("msp", TMS34010, XTAL_50MHz)
MCFG_CPU_PROGRAM_MAP(driver_msp_map)
MCFG_CPU_CONFIG(msp_config)
MCFG_TMS340X0_CONFIG(msp_config)
MACHINE_CONFIG_END
@ -1340,7 +1340,7 @@ static MACHINE_CONFIG_DERIVED( multisync_nomsp, driver_nomsp )
MCFG_CPU_PROGRAM_MAP(multisync_68k_map)
MCFG_CPU_MODIFY("gsp")
MCFG_CPU_CONFIG(gsp_config_multisync)
MCFG_TMS340X0_CONFIG(gsp_config_multisync)
MCFG_CPU_PROGRAM_MAP(multisync_gsp_map)
/* video hardware */
@ -1355,7 +1355,7 @@ static MACHINE_CONFIG_DERIVED( multisync_msp, multisync_nomsp )
/* basic machine hardware */
MCFG_CPU_ADD("msp", TMS34010, XTAL_50MHz)
MCFG_CPU_PROGRAM_MAP(driver_msp_map)
MCFG_CPU_CONFIG(msp_config)
MCFG_TMS340X0_CONFIG(msp_config)
MACHINE_CONFIG_END
@ -1530,7 +1530,7 @@ static MACHINE_CONFIG_DERIVED( stunrun, multisync_nomsp )
/* basic machine hardware */ /* multisync board without MSP */
MCFG_CPU_MODIFY("gsp")
MCFG_CPU_CONFIG(gsp_config_multisync_stunrun)
MCFG_TMS340X0_CONFIG(gsp_config_multisync_stunrun)
MCFG_FRAGMENT_ADD( adsp ) /* ADSP board */
/* video hardware */

4
src/mame/drivers/jpmimpct.c
View File

@ -826,7 +826,7 @@ static void jpmimpct_tms_irq(device_t *device, int state)
drvstate->update_irqs();
}
static const tms34010_config tms_config =
static const tms340x0_config tms_config =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
@ -851,7 +851,7 @@ static MACHINE_CONFIG_START( jpmimpct, jpmimpct_state )
MCFG_CPU_PROGRAM_MAP(m68k_program_map)
MCFG_CPU_ADD("dsp", TMS34010, 40000000)
MCFG_CPU_CONFIG(tms_config)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(tms_program_map)
MCFG_QUANTUM_TIME(attotime::from_hz(30000))

8
src/mame/drivers/lethalj.c
View File

@ -629,7 +629,7 @@ INPUT_PORTS_END
*
*************************************/
static const tms34010_config tms_config =
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -641,7 +641,7 @@ static const tms34010_config tms_config =
NULL /* read from shiftreg function */
};
static const tms34010_config tms_config_lethalj =
static const tms340x0_config tms_config_lethalj =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -665,7 +665,7 @@ static MACHINE_CONFIG_START( gameroom, lethalj_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, MASTER_CLOCK)
MCFG_CPU_CONFIG(tms_config)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(lethalj_map)
MCFG_TICKET_DISPENSER_ADD("ticket", attotime::from_msec(200), TICKET_MOTOR_ACTIVE_HIGH, TICKET_STATUS_ACTIVE_HIGH)
@ -695,7 +695,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( lethalj, gameroom )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_CONFIG(tms_config_lethalj)
MCFG_TMS340X0_CONFIG(tms_config_lethalj)
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_RAW_PARAMS(VIDEO_CLOCK_LETHALJ, 689, 0, 512, 259, 0, 236)

4
src/mame/drivers/metalmx.c
View File

@ -688,7 +688,7 @@ INPUT_PORTS_END
*
*************************************/
static const tms34010_config gsp_config =
static const tms340x0_config gsp_config =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
@ -715,7 +715,7 @@ static MACHINE_CONFIG_START( metalmx, metalmx_state )
MCFG_CPU_DATA_MAP(adsp_data_map)
MCFG_CPU_ADD("gsp", TMS34020, 40000000) /* Unverified */
MCFG_CPU_CONFIG(gsp_config)
MCFG_TMS340X0_CONFIG(gsp_config)
MCFG_CPU_PROGRAM_MAP(gsp_map)
MCFG_CPU_ADD("dsp32c_1", DSP32C, 40000000) /* Unverified */

4
src/mame/drivers/micro3d.c
View File

@ -286,7 +286,7 @@ ADDRESS_MAP_END
*
*************************************/
static const tms34010_config vgb_config =
static const tms340x0_config vgb_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -312,7 +312,7 @@ static MACHINE_CONFIG_START( micro3d, micro3d_state )
MCFG_CPU_VBLANK_INT_DRIVER("screen", micro3d_state, micro3d_vblank)
MCFG_CPU_ADD("vgb", TMS34010, XTAL_40MHz)
MCFG_CPU_CONFIG(vgb_config)
MCFG_TMS340X0_CONFIG(vgb_config)
MCFG_CPU_PROGRAM_MAP(vgbmem)
MCFG_CPU_ADD("drmath", AM29000, XTAL_32MHz / 2)

4
src/mame/drivers/midtunit.c
View File

@ -579,7 +579,7 @@ INPUT_PORTS_END
*
*************************************/
static const tms34010_config tms_config =
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -604,7 +604,7 @@ static MACHINE_CONFIG_START( tunit_core, midtunit_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, CPU_CLOCK)
MCFG_CPU_CONFIG(tms_config)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_MACHINE_RESET_OVERRIDE(midtunit_state,midtunit)

4
src/mame/drivers/midwunit.c
View File

@ -615,7 +615,7 @@ INPUT_PORTS_END
*
*************************************/
static const tms34010_config tms_config =
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -639,7 +639,7 @@ static const tms34010_config tms_config =
static MACHINE_CONFIG_START( wunit, midwunit_state )
MCFG_CPU_ADD("maincpu", TMS34010, 50000000)
MCFG_CPU_CONFIG(tms_config)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_MACHINE_RESET_OVERRIDE(midwunit_state,midwunit)

4
src/mame/drivers/midxunit.c
View File

@ -239,7 +239,7 @@ INPUT_PORTS_END
*
*************************************/
static const tms34010_config tms_config =
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -264,7 +264,7 @@ static MACHINE_CONFIG_START( midxunit, midxunit_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34020, 40000000)
MCFG_CPU_CONFIG(tms_config)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_MACHINE_RESET_OVERRIDE(midxunit_state,midxunit)

8
src/mame/drivers/midyunit.c
View File

@ -1066,7 +1066,7 @@ INPUT_PORTS_END
*
*************************************/
static const tms34010_config zunit_tms_config =
static const tms340x0_config zunit_tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -1079,7 +1079,7 @@ static const tms34010_config zunit_tms_config =
midyunit_from_shiftreg /* read from shiftreg function */
};
static const tms34010_config yunit_tms_config =
static const tms340x0_config yunit_tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -1104,7 +1104,7 @@ static MACHINE_CONFIG_START( zunit, midyunit_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, FAST_MASTER_CLOCK)
MCFG_CPU_CONFIG(zunit_tms_config)
MCFG_TMS340X0_CONFIG(zunit_tms_config)
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_MACHINE_RESET_OVERRIDE(midyunit_state,midyunit)
@ -1140,7 +1140,7 @@ static MACHINE_CONFIG_START( yunit_core, midyunit_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, SLOW_MASTER_CLOCK)
MCFG_CPU_CONFIG(yunit_tms_config)
MCFG_TMS340X0_CONFIG(yunit_tms_config)
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_MACHINE_RESET_OVERRIDE(midyunit_state,midyunit)

4
src/mame/drivers/potgoldu.c
View File

@ -64,7 +64,7 @@ static INPUT_PORTS_START( potgold )
INPUT_PORTS_END
static const tms34010_config tms_config =
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -82,7 +82,7 @@ static MACHINE_CONFIG_START( potgold, potgold_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
MCFG_CPU_CONFIG(tms_config)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(potgold_map)

4
src/mame/drivers/skeetsht.c
View File

@ -219,7 +219,7 @@ INPUT_PORTS_END
*
*************************************/
static const tms34010_config tms_config =
static const tms340x0_config tms_config =
{
TRUE, /* halt on reset */
"screen", /* the screen operated on */
@ -248,7 +248,7 @@ static MACHINE_CONFIG_START( skeetsht, skeetsht_state )
MCFG_MC68HC11_CONFIG( 0, 0x100, 0x01 ) // And 512 bytes EEPROM? (68HC11A1)
MCFG_CPU_ADD("tms", TMS34010, 48000000)
MCFG_CPU_CONFIG(tms_config)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(tms_program_map)

4
src/mame/drivers/skimaxx.c
View File

@ -467,7 +467,7 @@ static void skimaxx_tms_irq(device_t *device, int state)
// TODO
}
static const tms34010_config tms_config =
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -508,7 +508,7 @@ static MACHINE_CONFIG_START( skimaxx, skimaxx_state )
/* video hardware */
MCFG_CPU_ADD("tms", TMS34010, XTAL_50MHz)
MCFG_CPU_CONFIG(tms_config)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(tms_program_map)
MCFG_SCREEN_ADD("screen", RASTER)

10
src/mame/drivers/tickee.c
View File

@ -735,7 +735,7 @@ INPUT_PORTS_END
*
*************************************/
static const tms34010_config tms_config =
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -749,7 +749,7 @@ static const tms34010_config tms_config =
};
static const tms34010_config rapidfir_tms_config =
static const tms340x0_config rapidfir_tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -774,7 +774,7 @@ static MACHINE_CONFIG_START( tickee, tickee_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
MCFG_CPU_CONFIG(tms_config)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(tickee_map)
MCFG_MACHINE_RESET_OVERRIDE(tickee_state,tickee)
@ -819,7 +819,7 @@ static MACHINE_CONFIG_START( rapidfir, tickee_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, XTAL_50MHz)
MCFG_CPU_CONFIG(rapidfir_tms_config)
MCFG_TMS340X0_CONFIG(rapidfir_tms_config)
MCFG_CPU_PROGRAM_MAP(rapidfir_map)
MCFG_MACHINE_RESET_OVERRIDE(tickee_state,rapidfir)
@ -846,7 +846,7 @@ static MACHINE_CONFIG_START( mouseatk, tickee_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
MCFG_CPU_CONFIG(tms_config)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(mouseatk_map)
MCFG_MACHINE_RESET_OVERRIDE(tickee_state,tickee)

4
src/mame/drivers/xtheball.c
View File

@ -322,7 +322,7 @@ INPUT_PORTS_END
*
*************************************/
static const tms34010_config tms_config =
static const tms340x0_config tms_config =
{
FALSE, /* halt on reset */
"screen", /* the screen operated on */
@ -346,7 +346,7 @@ static const tms34010_config tms_config =
static MACHINE_CONFIG_START( xtheball, xtheball_state )
MCFG_CPU_ADD("maincpu", TMS34010, 40000000)
MCFG_CPU_CONFIG(tms_config)
MCFG_TMS340X0_CONFIG(tms_config)
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_CPU_PERIODIC_INT_DRIVER(xtheball_state, irq1_line_hold, 15000)

4
src/mame/machine/inder_vid.c
View File

@ -90,7 +90,7 @@ static void m68k_gen_int(device_t *device, int state)
}
static const tms34010_config tms_config_megaphx =
static const tms340x0_config tms_config_megaphx =
{
TRUE, /* halt on reset */
"inder_vid:inder_screen", /* the screen operated on */
@ -110,7 +110,7 @@ ADDRESS_MAP_END
static MACHINE_CONFIG_FRAGMENT( inder_vid )
MCFG_CPU_ADD("tms", TMS34010, XTAL_40MHz)
MCFG_CPU_CONFIG(tms_config_megaphx)
MCFG_TMS340X0_CONFIG(tms_config_megaphx)
MCFG_CPU_PROGRAM_MAP(megaphx_tms_map)
MCFG_SCREEN_ADD("inder_screen", RASTER)

2
src/mame/video/exterm.c
View File

@ -79,7 +79,7 @@ void exterm_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int sca
int x;
/* get parameters for the slave CPU */
tms34010_get_display_params(state->m_slave, &fgparams);
state->m_slave->get_display_params(&fgparams);
/* compute info about the slave vram */
if (fgparams.enabled && scanline >= fgparams.veblnk && scanline < fgparams.vsblnk && fgparams.heblnk < fgparams.hsblnk)