CPU cores are now enabled on a per cpu core family basis instead of per cpu core variant. As a result CPUDEFS is no longer needed in the makefile.

This commit is contained in:
Wilbert Pol 2009-03-25 19:39:41 +00:00
parent 2e94113cb6
commit a35ef58b54
35 changed files with 49 additions and 907 deletions

View File

@ -492,7 +492,7 @@ include $(SRC)/build/build.mak
include $(SRC)/tools/tools.mak include $(SRC)/tools/tools.mak
# combine the various definitions to one # combine the various definitions to one
CDEFS = $(DEFS) $(COREDEFS) $(CPUDEFS) $(SOUNDDEFS) CDEFS = $(DEFS) $(COREDEFS) $(SOUNDDEFS)

View File

@ -525,7 +525,6 @@ static void jz(alpha8201_state *cpustate) { UINT8 i=M_RDMEM_OPCODE(cpustate); if
static void jc(alpha8201_state *cpustate) { UINT8 i=M_RDMEM_OPCODE(cpustate); if ( cpustate->cf) M_JMP(cpustate, i);} static void jc(alpha8201_state *cpustate) { UINT8 i=M_RDMEM_OPCODE(cpustate); if ( cpustate->cf) M_JMP(cpustate, i);}
static void jmp(alpha8201_state *cpustate) { M_JMP(cpustate, M_RDMEM_OPCODE(cpustate) ); } static void jmp(alpha8201_state *cpustate) { M_JMP(cpustate, M_RDMEM_OPCODE(cpustate) ); }
#if (HAS_ALPHA8201)
static const s_opcode opcode_8201[256]= static const s_opcode opcode_8201[256]=
{ {
{C1, nop },{C1,rora },{C1, rola },{C1,inc_b },{C1,dec_b },{C1, inc_a },{C1, dec_a },{C1, cpl }, {C1, nop },{C1,rora },{C1, rola },{C1,inc_b },{C1,dec_b },{C1, inc_a },{C1, dec_a },{C1, cpl },
@ -566,9 +565,7 @@ static const s_opcode opcode_8201[256]=
{C1, undefined },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined}, {C1, undefined },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
{C1, undefined },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined } {C1, undefined },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined }
}; };
#endif
#if (HAS_ALPHA8301)
/* ALPHA 8301 : added instruction */ /* ALPHA 8301 : added instruction */
static void exg_a_ix0(alpha8201_state *cpustate) { UINT8 t=cpustate->A; cpustate->A = cpustate->IX0; cpustate->IX0 = t; } static void exg_a_ix0(alpha8201_state *cpustate) { UINT8 t=cpustate->A; cpustate->A = cpustate->IX0; cpustate->IX0 = t; }
@ -663,7 +660,6 @@ static const s_opcode opcode_8301[256]=
{C1,exg_ix0_ix1},{C1,exg_ix0_ix2},{C1,op_rep_ld_ix2_b},{C1, op_rep_ld_b_ix0},{C1, save_zc},{C1, rest_zc},{C1, ld_rxb_a },{C1, ld_a_rxb }, {C1,exg_ix0_ix1},{C1,exg_ix0_ix2},{C1,op_rep_ld_ix2_b},{C1, op_rep_ld_b_ix0},{C1, save_zc},{C1, rest_zc},{C1, ld_rxb_a },{C1, ld_a_rxb },
{C1, cmp_a_rxb },{C1, xor_a_rxb},{C1, add_a_cf },{C1, sub_a_cf },{C1, tst_a },{C1, clr_a },{C1, ld_a_ix0_a},{C1, ret } {C1, cmp_a_rxb },{C1, xor_a_rxb},{C1, add_a_cf },{C1, sub_a_cf },{C1, tst_a },{C1, clr_a },{C1, ld_a_ix0_a},{C1, ret }
}; };
#endif
/**************************************************************************** /****************************************************************************
* Initialize emulation * Initialize emulation
@ -814,13 +810,9 @@ mame_printf_debug("alpha8201: cpustate->PC = %03x, opcode = %02x\n", cpustate-
return cycles - cpustate->icount; return cycles - cpustate->icount;
} }
#if (HAS_ALPHA8201)
static CPU_EXECUTE( alpha8201 ) { return alpha8xxx_execute(device,opcode_8201,cycles); } static CPU_EXECUTE( alpha8201 ) { return alpha8xxx_execute(device,opcode_8201,cycles); }
#endif
#if (HAS_ALPHA8301)
static CPU_EXECUTE( ALPHA8301 ) { return alpha8xxx_execute(device,opcode_8301,cycles); } static CPU_EXECUTE( ALPHA8301 ) { return alpha8xxx_execute(device,opcode_8301,cycles); }
#endif
/**************************************************************************** /****************************************************************************
* Set IRQ line state * Set IRQ line state
@ -980,7 +972,6 @@ static CPU_GET_INFO( alpha8xxx )
case CPUINFO_STR_REGISTER + ALPHA8201_R7: sprintf(info->s, "R7:%02X", RD_REG(7)); break; case CPUINFO_STR_REGISTER + ALPHA8201_R7: sprintf(info->s, "R7:%02X", RD_REG(7)); break;
} }
} }
#if (HAS_ALPHA8201)
CPU_GET_INFO( alpha8201 ) CPU_GET_INFO( alpha8201 )
{ {
switch (state) switch (state)
@ -992,9 +983,7 @@ CPU_GET_INFO( alpha8201 )
CPU_GET_INFO_CALL(alpha8xxx); CPU_GET_INFO_CALL(alpha8xxx);
} }
} }
#endif
#if (HAS_ALPHA8301)
CPU_GET_INFO( alpha8301 ) CPU_GET_INFO( alpha8301 )
{ {
switch (state) switch (state)
@ -1006,4 +995,3 @@ CPU_GET_INFO( alpha8301 )
CPU_GET_INFO_CALL(alpha8xxx); CPU_GET_INFO_CALL(alpha8xxx);
} }
} }
#endif

View File

@ -78,9 +78,6 @@ $(DRCOBJ): $(DRCDEPS)
# Acorn ARM series # Acorn ARM series
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_ARM=$(if $(filter ARM,$(CPUS)),1,0)
CPUDEFS += -DHAS_ARM7=$(if $(filter ARM7,$(CPUS)),1,0)
ifneq ($(filter ARM,$(CPUS)),) ifneq ($(filter ARM,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/arm OBJDIRS += $(CPUOBJ)/arm
CPUOBJS += $(CPUOBJ)/arm/arm.o CPUOBJS += $(CPUOBJ)/arm/arm.o
@ -107,8 +104,6 @@ $(CPUOBJ)/arm7/arm7.o: $(CPUSRC)/arm7/arm7.c \
# Advanced Digital Chips SE3208 # Advanced Digital Chips SE3208
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_SE3208=$(if $(filter SE3208,$(CPUS)),1,0)
ifneq ($(filter SE3208,$(CPUS)),) ifneq ($(filter SE3208,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/se3208 OBJDIRS += $(CPUOBJ)/se3208
CPUOBJS += $(CPUOBJ)/se3208/se3208.o CPUOBJS += $(CPUOBJ)/se3208/se3208.o
@ -124,10 +119,7 @@ $(CPUOBJ)/se3208/se3208.o: $(CPUSRC)/se3208/se3208.c \
# Alpha 8201 # Alpha 8201
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_ALPHA8201=$(if $(filter ALPHA8201,$(CPUS)),1,0) ifneq ($(filter ALPHA8201,$(CPUS)),)
CPUDEFS += -DHAS_ALPHA8301=$(if $(filter ALPHA8301,$(CPUS)),1,0)
ifneq ($(filter ALPHA8201 ALPHA8301,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/alph8201 OBJDIRS += $(CPUOBJ)/alph8201
CPUOBJS += $(CPUOBJ)/alph8201/alph8201.o CPUOBJS += $(CPUOBJ)/alph8201/alph8201.o
DBGOBJS += $(CPUOBJ)/alph8201/8201dasm.o DBGOBJS += $(CPUOBJ)/alph8201/8201dasm.o
@ -142,8 +134,6 @@ $(CPUOBJ)/alph8201/alph8201.o: $(CPUSRC)/alph8201/alph8201.c \
# Analog Devices ADSP21xx series # Analog Devices ADSP21xx series
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_ADSP21XX=$(if $(filter ADSP21XX,$(CPUS)),1,0)
ifneq ($(filter ADSP21XX,$(CPUS)),) ifneq ($(filter ADSP21XX,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/adsp2100 OBJDIRS += $(CPUOBJ)/adsp2100
CPUOBJS += $(CPUOBJ)/adsp2100/adsp2100.o CPUOBJS += $(CPUOBJ)/adsp2100/adsp2100.o
@ -160,8 +150,6 @@ $(CPUOBJ)/adsp2100/adsp2100.o: $(CPUSRC)/adsp2100/adsp2100.c \
# Analog Devices "Sharc" ADSP21062 # Analog Devices "Sharc" ADSP21062
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_ADSP21062=$(if $(filter ADSP21062,$(CPUS)),1,0)
ifneq ($(filter ADSP21062,$(CPUS)),) ifneq ($(filter ADSP21062,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/sharc OBJDIRS += $(CPUOBJ)/sharc
CPUOBJS += $(CPUOBJ)/sharc/sharc.o CPUOBJS += $(CPUOBJ)/sharc/sharc.o
@ -184,8 +172,6 @@ $(CPUOBJ)/sharc/sharc.o: $(CPUSRC)/sharc/sharc.c \
# APEXC # APEXC
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_APEXC=$(if $(filter APEXC,$(CPUS)),1,0)
ifneq ($(filter APEXC,$(CPUS)),) ifneq ($(filter APEXC,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/apexc OBJDIRS += $(CPUOBJ)/apexc
CPUOBJS += $(CPUOBJ)/apexc/apexc.o CPUOBJS += $(CPUOBJ)/apexc/apexc.o
@ -201,8 +187,6 @@ $(CPUOBJ)/apexc/apexc.o: $(CPUSRC)/apexc/apexc.c \
# AT&T DSP32C # AT&T DSP32C
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_DSP32C=$(if $(filter DSP32C,$(CPUS)),1,0)
ifneq ($(filter DSP32C,$(CPUS)),) ifneq ($(filter DSP32C,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/dsp32 OBJDIRS += $(CPUOBJ)/dsp32
CPUOBJS += $(CPUOBJ)/dsp32/dsp32.o CPUOBJS += $(CPUOBJ)/dsp32/dsp32.o
@ -218,8 +202,6 @@ $(CPUOBJ)/dsp32/dsp32.o: $(CPUSRC)/dsp32/dsp32.c \
# Atari custom RISC processor # Atari custom RISC processor
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_ASAP=$(if $(filter ASAP,$(CPUS)),1,0)
ifneq ($(filter ASAP,$(CPUS)),) ifneq ($(filter ASAP,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/asap OBJDIRS += $(CPUOBJ)/asap
CPUOBJS += $(CPUOBJ)/asap/asap.o CPUOBJS += $(CPUOBJ)/asap/asap.o
@ -235,8 +217,6 @@ $(CPUOBJ)/asap/asap.o: $(CPUSRC)/asap/asap.c \
# Atari Jaguar custom DSPs # Atari Jaguar custom DSPs
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_JAGUAR=$(if $(filter JAGUAR,$(CPUS)),1,0)
ifneq ($(filter JAGUAR,$(CPUS)),) ifneq ($(filter JAGUAR,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/jaguar OBJDIRS += $(CPUOBJ)/jaguar
CPUOBJS += $(CPUOBJ)/jaguar/jaguar.o CPUOBJS += $(CPUOBJ)/jaguar/jaguar.o
@ -252,8 +232,6 @@ $(CPUOBJ)/jaguar/jaguar.o: $(CPUSRC)/jaguar/jaguar.c \
# Simutrek Cube Quest bit-sliced CPUs # Simutrek Cube Quest bit-sliced CPUs
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_CUBEQCPU=$(if $(filter CUBEQCPU,$(CPUS)),1,0)
ifneq ($(filter CUBEQCPU,$(CPUS)),) ifneq ($(filter CUBEQCPU,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/cubeqcpu OBJDIRS += $(CPUOBJ)/cubeqcpu
CPUOBJS += $(CPUOBJ)/cubeqcpu/cubeqcpu.o CPUOBJS += $(CPUOBJ)/cubeqcpu/cubeqcpu.o
@ -269,8 +247,6 @@ $(CPUOBJ)/cubeqcpu/cubeqcpu.o: $(CPUSRC)/cubeqcpu/cubeqcpu.c \
# Entertainment Sciences AM29116-based RIP # Entertainment Sciences AM29116-based RIP
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_ESRIP=$(if $(filter ESRIP,$(CPUS)),1,0)
ifneq ($(filter ESRIP,$(CPUS)),) ifneq ($(filter ESRIP,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/esrip OBJDIRS += $(CPUOBJ)/esrip
CPUOBJS += $(CPUOBJ)/esrip/esrip.o CPUOBJS += $(CPUOBJ)/esrip/esrip.o
@ -286,8 +262,6 @@ $(CPUOBJ)/esrip/esrip.o: $(CPUSRC)/esrip/esrip.c \
# RCA CDP1802 # RCA CDP1802
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_CDP1802=$(if $(filter CDP1802,$(CPUS)),1,0)
ifneq ($(filter CDP1802,$(CPUS)),) ifneq ($(filter CDP1802,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/cdp1802 OBJDIRS += $(CPUOBJ)/cdp1802
CPUOBJS += $(CPUOBJ)/cdp1802/cdp1802.o CPUOBJS += $(CPUOBJ)/cdp1802/cdp1802.o
@ -303,8 +277,6 @@ $(CPUOBJ)/cdp1802/cdp1802.o: $(CPUSRC)/cdp1802/cdp1802.c \
# National Semiconductor COP400 family # National Semiconductor COP400 family
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_COP400=$(if $(filter COP400,$(CPUS)),1,0)
ifneq ($(filter COP400,$(CPUS)),) ifneq ($(filter COP400,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/cop400 OBJDIRS += $(CPUOBJ)/cop400
CPUOBJS += $(CPUOBJ)/cop400/cop400.o CPUOBJS += $(CPUOBJ)/cop400/cop400.o
@ -323,8 +295,6 @@ $(CPUOBJ)/cop400/cop400.o: $(CPUSRC)/cop400/cop400.c \
# CP1610 # CP1610
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_CP1610=$(if $(filter CP1610,$(CPUS)),1,0)
ifneq ($(filter CP1610,$(CPUS)),) ifneq ($(filter CP1610,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/cp1610 OBJDIRS += $(CPUOBJ)/cp1610
CPUOBJS += $(CPUOBJ)/cp1610/cp1610.o CPUOBJS += $(CPUOBJ)/cp1610/cp1610.o
@ -340,8 +310,6 @@ $(CPUOBJ)/cp1610/cp1610.o: $(CPUSRC)/cp1610/cp1610.c \
# Cinematronics vector "CPU" # Cinematronics vector "CPU"
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_CCPU=$(if $(filter CCPU,$(CPUS)),1,0)
ifneq ($(filter CCPU,$(CPUS)),) ifneq ($(filter CCPU,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/ccpu OBJDIRS += $(CPUOBJ)/ccpu
CPUOBJS += $(CPUOBJ)/ccpu/ccpu.o CPUOBJS += $(CPUOBJ)/ccpu/ccpu.o
@ -357,8 +325,6 @@ $(CPUOBJ)/ccpu/ccpu.o: $(CPUSRC)/ccpu/ccpu.c \
# DEC T-11 # DEC T-11
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_T11=$(if $(filter T11,$(CPUS)),1,0)
ifneq ($(filter T11,$(CPUS)),) ifneq ($(filter T11,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/t11 OBJDIRS += $(CPUOBJ)/t11
CPUOBJS += $(CPUOBJ)/t11/t11.o CPUOBJS += $(CPUOBJ)/t11/t11.o
@ -376,8 +342,6 @@ $(CPUOBJ)/t11/t11.o: $(CPUSRC)/t11/t11.c \
# F8 # F8
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_F8=$(if $(filter F8,$(CPUS)),1,0)
ifneq ($(filter F8,$(CPUS)),) ifneq ($(filter F8,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/f8 OBJDIRS += $(CPUOBJ)/f8
CPUOBJS += $(CPUOBJ)/f8/f8.o CPUOBJS += $(CPUOBJ)/f8/f8.o
@ -393,8 +357,6 @@ $(CPUOBJ)/f8/f8.o: $(CPUSRC)/f8/f8.c \
# G65816 # G65816
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_G65816=$(if $(filter G65816,$(CPUS)),1,0)
ifneq ($(filter G65816,$(CPUS)),) ifneq ($(filter G65816,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/g65816 OBJDIRS += $(CPUOBJ)/g65816
CPUOBJS += \ CPUOBJS += \
@ -436,8 +398,6 @@ $(CPUOBJ)/g65816/g65816o4.o: $(CPUSRC)/g65816/g65816o4.c \
# Hitachi 6309 # Hitachi 6309
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_HD6309=$(if $(filter HD6309,$(CPUS)),1,0)
ifneq ($(filter HD6309,$(CPUS)),) ifneq ($(filter HD6309,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/hd6309 OBJDIRS += $(CPUOBJ)/hd6309
CPUOBJS += $(CPUOBJ)/hd6309/hd6309.o CPUOBJS += $(CPUOBJ)/hd6309/hd6309.o
@ -454,8 +414,6 @@ $(CPUOBJ)/hd6309/hd6309.o: $(CPUSRC)/hd6309/hd6309.c \
# Hitachi H8/30xx (16/32-bit H8/3xx series) # Hitachi H8/30xx (16/32-bit H8/3xx series)
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_H83002=$(if $(filter H83002,$(CPUS)),1,0)
ifneq ($(filter H83002,$(CPUS)),) ifneq ($(filter H83002,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/h83002 OBJDIRS += $(CPUOBJ)/h83002
CPUOBJS += $(CPUOBJ)/h83002/h8_16.o $(CPUOBJ)/h83002/h8periph.o CPUOBJS += $(CPUOBJ)/h83002/h8_16.o $(CPUOBJ)/h83002/h8periph.o
@ -477,8 +435,6 @@ $(CPUOBJ)/h83002/h8periph.o: $(CPUSRC)/h83002/h8periph.c \
# Hitachi H8/3334 (8/16-bit H8/3xx series) # Hitachi H8/3334 (8/16-bit H8/3xx series)
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_H83334=$(if $(filter H83334,$(CPUS)),1,0)
ifneq ($(filter H83334,$(CPUS)),) ifneq ($(filter H83334,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/h83002 OBJDIRS += $(CPUOBJ)/h83002
CPUOBJS += $(CPUOBJ)/h83002/h8_8.o $(CPUOBJ)/h83002/h8periph.o CPUOBJS += $(CPUOBJ)/h83002/h8_8.o $(CPUOBJ)/h83002/h8periph.o
@ -499,16 +455,6 @@ $(CPUOBJ)/h83002/h8periph.o: $(CPUSRC)/h83002/h8periph.c \
# Hitachi SH1/SH2 # Hitachi SH1/SH2
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_SH1=$(if $(filter SH1,$(CPUS)),1,0)
ifneq ($(filter SH1,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/sh2
CPUOBJS += $(CPUOBJ)/sh2/sh2.o $(CPUOBJ)/sh2/sh2comn.o $(CPUOBJ)/sh2/sh2drc.o $(CPUOBJ)/sh2/sh2fe.o $(DRCOBJ)
DBGOBJS += $(CPUOBJ)/sh2/sh2dasm.o
endif
CPUDEFS += -DHAS_SH2=$(if $(filter SH2,$(CPUS)),1,0)
ifneq ($(filter SH2,$(CPUS)),) ifneq ($(filter SH2,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/sh2 OBJDIRS += $(CPUOBJ)/sh2
CPUOBJS += $(CPUOBJ)/sh2/sh2.o $(CPUOBJ)/sh2/sh2comn.o $(CPUOBJ)/sh2/sh2drc.o $(CPUOBJ)/sh2/sh2fe.o $(DRCOBJ) CPUOBJS += $(CPUOBJ)/sh2/sh2.o $(CPUOBJ)/sh2/sh2comn.o $(CPUOBJ)/sh2/sh2drc.o $(CPUOBJ)/sh2/sh2fe.o $(DRCOBJ)
@ -535,8 +481,6 @@ $(CPUOBJ)/sh2/sh2fe.o: $(CPUSRC)/sh2/sh2fe.c \
# Hitachi SH4 # Hitachi SH4
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_SH4=$(if $(filter SH4,$(CPUS)),1,0)
ifneq ($(filter SH4,$(CPUS)),) ifneq ($(filter SH4,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/sh4 OBJDIRS += $(CPUOBJ)/sh4
CPUOBJS += $(CPUOBJ)/sh4/sh4.o $(CPUOBJ)/sh4/sh4comn.o CPUOBJS += $(CPUOBJ)/sh4/sh4.o $(CPUOBJ)/sh4/sh4comn.o
@ -557,8 +501,6 @@ $(CPUOBJ)/sh4/sh4comn.o: $(CPUSRC)/sh4/sh4comn.c \
# Hudsonsoft 6280 # Hudsonsoft 6280
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_H6280=$(if $(filter H6280,$(CPUS)),1,0)
ifneq ($(filter H6280,$(CPUS)),) ifneq ($(filter H6280,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/h6280 OBJDIRS += $(CPUOBJ)/h6280
CPUOBJS += $(CPUOBJ)/h6280/h6280.o CPUOBJS += $(CPUOBJ)/h6280/h6280.o
@ -576,22 +518,7 @@ $(CPUOBJ)/h6280/h6280.o: $(CPUSRC)/h6280/h6280.c \
# Hyperstone E1 series # Hyperstone E1 series
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_E116T=$(if $(filter E116T,$(CPUS)),1,0) ifneq ($(filter E1,$(CPUS)),)
CPUDEFS += -DHAS_E116XT=$(if $(filter E116XT,$(CPUS)),1,0)
CPUDEFS += -DHAS_E116XS=$(if $(filter E116XS,$(CPUS)),1,0)
CPUDEFS += -DHAS_E116XSR=$(if $(filter E116XSR,$(CPUS)),1,0)
CPUDEFS += -DHAS_E132N=$(if $(filter E132N,$(CPUS)),1,0)
CPUDEFS += -DHAS_E132T=$(if $(filter E132T,$(CPUS)),1,0)
CPUDEFS += -DHAS_E132XN=$(if $(filter E132XN,$(CPUS)),1,0)
CPUDEFS += -DHAS_E132XT=$(if $(filter E132XT,$(CPUS)),1,0)
CPUDEFS += -DHAS_E132XS=$(if $(filter E132XS,$(CPUS)),1,0)
CPUDEFS += -DHAS_E132XSR=$(if $(filter E132XSR,$(CPUS)),1,0)
CPUDEFS += -DHAS_GMS30C2116=$(if $(filter GMS30C2116,$(CPUS)),1,0)
CPUDEFS += -DHAS_GMS30C2132=$(if $(filter GMS30C2132,$(CPUS)),1,0)
CPUDEFS += -DHAS_GMS30C2216=$(if $(filter GMS30C2216,$(CPUS)),1,0)
CPUDEFS += -DHAS_GMS30C2232=$(if $(filter GMS30C2232,$(CPUS)),1,0)
ifneq ($(filter E116T E116XT E116XS E116XSR E132N E132T E132XN E132XT E132XS E132XSR GMS30C2116 GMS30C2132 GMS30C2216 GMS30C2232,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/e132xs OBJDIRS += $(CPUOBJ)/e132xs
CPUOBJS += $(CPUOBJ)/e132xs/e132xs.o CPUOBJS += $(CPUOBJ)/e132xs/e132xs.o
DBGOBJS += $(CPUOBJ)/e132xs/32xsdasm.o DBGOBJS += $(CPUOBJ)/e132xs/32xsdasm.o
@ -607,8 +534,6 @@ $(CPUOBJ)/e132xs/e132xs.o: $(CPUSRC)/e132xs/e132xs.c \
# Intel 8080/8085A # Intel 8080/8085A
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_I8085=$(if $(filter I8085,$(CPUS)),1,0)
ifneq ($(filter I8085,$(CPUS)),) ifneq ($(filter I8085,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/i8085 OBJDIRS += $(CPUOBJ)/i8085
CPUOBJS += $(CPUOBJ)/i8085/i8085.o CPUOBJS += $(CPUOBJ)/i8085/i8085.o
@ -626,8 +551,6 @@ $(CPUOBJ)/i8085/i8085.o: $(CPUSRC)/i8085/i8085.c \
# Intel MCS-48 (8039 and derivatives) # Intel MCS-48 (8039 and derivatives)
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_MCS48=$(if $(filter MCS48,$(CPUS)),1,0)
ifneq ($(filter MCS48,$(CPUS)),) ifneq ($(filter MCS48,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/mcs48 OBJDIRS += $(CPUOBJ)/mcs48
CPUOBJS += $(CPUOBJ)/mcs48/mcs48.o CPUOBJS += $(CPUOBJ)/mcs48/mcs48.o
@ -643,22 +566,7 @@ $(CPUOBJ)/mcs48/mcs48.o: $(CPUSRC)/mcs48/mcs48.c \
# Intel 8051 and derivatives # Intel 8051 and derivatives
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_I8031=$(if $(filter I8031,$(CPUS)),1,0) ifneq ($(filter MCS51,$(CPUS)),)
CPUDEFS += -DHAS_I8032=$(if $(filter I8032,$(CPUS)),1,0)
CPUDEFS += -DHAS_I8051=$(if $(filter I8051,$(CPUS)),1,0)
CPUDEFS += -DHAS_I8052=$(if $(filter I8052,$(CPUS)),1,0)
CPUDEFS += -DHAS_I8751=$(if $(filter I8751,$(CPUS)),1,0)
CPUDEFS += -DHAS_I8752=$(if $(filter I8752,$(CPUS)),1,0)
CPUDEFS += -DHAS_I80C31=$(if $(filter I80C31,$(CPUS)),1,0)
CPUDEFS += -DHAS_I80C32=$(if $(filter I80C32,$(CPUS)),1,0)
CPUDEFS += -DHAS_I80C51=$(if $(filter I80C51,$(CPUS)),1,0)
CPUDEFS += -DHAS_I80C52=$(if $(filter I80C52,$(CPUS)),1,0)
CPUDEFS += -DHAS_I87C51=$(if $(filter I87C51,$(CPUS)),1,0)
CPUDEFS += -DHAS_I87C52=$(if $(filter I87C52,$(CPUS)),1,0)
CPUDEFS += -DHAS_AT89C4051=$(if $(filter AT89C4051,$(CPUS)),1,0)
CPUDEFS += -DHAS_DS5002FP=$(if $(filter DS5002FP,$(CPUS)),1,0)
ifneq ($(filter DS5002FP I8031 I8032 I8051 I8052 I8751 I8752 I80C31 I80C32 I80C51 I80C52 I87C51 I87C52 AT89C4051,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/mcs51 OBJDIRS += $(CPUOBJ)/mcs51
CPUOBJS += $(CPUOBJ)/mcs51/mcs51.o CPUOBJS += $(CPUOBJ)/mcs51/mcs51.o
DBGOBJS += $(CPUOBJ)/mcs51/mcs51dasm.o DBGOBJS += $(CPUOBJ)/mcs51/mcs51dasm.o
@ -672,31 +580,14 @@ $(CPUOBJ)/mcs51/mcs51.o: $(CPUSRC)/mcs51/mcs51.c \
# Intel 80x86 series # Intel 80x86 series
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_I8086=$(if $(filter I8086,$(CPUS)),1,0) ifneq ($(filter I86,$(CPUS)),)
CPUDEFS += -DHAS_I8088=$(if $(filter I8088,$(CPUS)),1,0)
CPUDEFS += -DHAS_I80186=$(if $(filter I80186,$(CPUS)),1,0)
CPUDEFS += -DHAS_I80188=$(if $(filter I80188,$(CPUS)),1,0)
CPUDEFS += -DHAS_I80286=$(if $(filter I80286,$(CPUS)),1,0)
CPUDEFS += -DHAS_I386=$(if $(filter I386,$(CPUS)),1,0)
CPUDEFS += -DHAS_I486=$(if $(filter I486,$(CPUS)),1,0)
CPUDEFS += -DHAS_PENTIUM=$(if $(filter PENTIUM,$(CPUS)),1,0)
CPUDEFS += -DHAS_MEDIAGX=$(if $(filter MEDIAGX,$(CPUS)),1,0)
ifneq ($(filter I8086 I8088 I80186 I80188,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/i86 $(CPUOBJ)/i386 OBJDIRS += $(CPUOBJ)/i86 $(CPUOBJ)/i386
CPUOBJS += $(CPUOBJ)/i86/i86.o CPUOBJS += $(CPUOBJ)/i86/i86.o
DBGOBJS += $(CPUOBJ)/i386/i386dasm.o
endif
ifneq ($(filter I80286,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/i86 $(CPUOBJ)/i386
CPUOBJS += $(CPUOBJ)/i86/i286.o CPUOBJS += $(CPUOBJ)/i86/i286.o
DBGOBJS += $(CPUOBJ)/i386/i386dasm.o DBGOBJS += $(CPUOBJ)/i386/i386dasm.o
endif endif
ifneq ($(filter I386,$(CPUS)),)
ifneq ($(filter I386 I486 PENTIUM MEDIAGX,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/i386 OBJDIRS += $(CPUOBJ)/i386
CPUOBJS += $(CPUOBJ)/i386/i386.o CPUOBJS += $(CPUOBJ)/i386/i386.o
DBGOBJS += $(CPUOBJ)/i386/i386dasm.o DBGOBJS += $(CPUOBJ)/i386/i386dasm.o
@ -739,8 +630,6 @@ $(CPUOBJ)/i386/i386.o: $(CPUSRC)/i386/i386.c \
# Intel i860 # Intel i860
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_I860=$(if $(filter I860,$(CPUS)),1,0)
ifneq ($(filter I860,$(CPUS)),) ifneq ($(filter I860,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/i860 OBJDIRS += $(CPUOBJ)/i860
CPUOBJS += $(CPUOBJ)/i860/i860.o CPUOBJS += $(CPUOBJ)/i860/i860.o
@ -755,8 +644,6 @@ $(CPUOBJ)/i860/i860.o: $(CPUSRC)/i860/i860.c \
# Intel i960 # Intel i960
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_I960=$(if $(filter I960,$(CPUS)),1,0)
ifneq ($(filter I960,$(CPUS)),) ifneq ($(filter I960,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/i960 OBJDIRS += $(CPUOBJ)/i960
CPUOBJS += $(CPUOBJ)/i960/i960.o CPUOBJS += $(CPUOBJ)/i960/i960.o
@ -772,8 +659,6 @@ $(CPUOBJ)/i960/i960.o: $(CPUSRC)/i960/i960.c \
# Konami custom CPU (6809-based) # Konami custom CPU (6809-based)
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_KONAMI=$(if $(filter KONAMI,$(CPUS)),1,0)
ifneq ($(filter KONAMI,$(CPUS)),) ifneq ($(filter KONAMI,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/konami OBJDIRS += $(CPUOBJ)/konami
CPUOBJS += $(CPUOBJ)/konami/konami.o CPUOBJS += $(CPUOBJ)/konami/konami.o
@ -791,8 +676,6 @@ $(CPUOBJ)/konami/konami.o: $(CPUSRC)/konami/konami.c \
# LH5801 # LH5801
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_LH5801=$(if $(filter LH5801,$(CPUS)),1,0)
ifneq ($(filter LH5801,$(CPUS)),) ifneq ($(filter LH5801,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/lh5801 OBJDIRS += $(CPUOBJ)/lh5801
CPUOBJS += $(CPUOBJ)/lh5801/lh5801.o CPUOBJS += $(CPUOBJ)/lh5801/lh5801.o
@ -809,12 +692,7 @@ $(CPUOBJ)/lh5801/lh5801.o: $(CPUSRC)/lh5801/lh5801.c \
# Fujitsu MB88xx # Fujitsu MB88xx
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_MB8841=$(if $(filter MB8841,$(CPUS)),1,0) ifneq ($(filter MB88XX,$(CPUS)),)
CPUDEFS += -DHAS_MB8842=$(if $(filter MB8842,$(CPUS)),1,0)
CPUDEFS += -DHAS_MB8843=$(if $(filter MB8843,$(CPUS)),1,0)
CPUDEFS += -DHAS_MB8844=$(if $(filter MB8844,$(CPUS)),1,0)
ifneq ($(filter MB8841 MB8842 MB8843 MB8844,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/mb88xx OBJDIRS += $(CPUOBJ)/mb88xx
CPUOBJS += $(CPUOBJ)/mb88xx/mb88xx.o CPUOBJS += $(CPUOBJ)/mb88xx/mb88xx.o
DBGOBJS += $(CPUOBJ)/mb88xx/mb88dasm.o DBGOBJS += $(CPUOBJ)/mb88xx/mb88dasm.o
@ -829,8 +707,6 @@ $(CPUOBJ)/mb88xx/mb88xx.o: $(CPUSRC)/mb88xx/mb88xx.c \
# Fujitsu MB86233 # Fujitsu MB86233
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_MB86233=$(if $(filter MB86233,$(CPUS)),1,0)
ifneq ($(filter MB86233,$(CPUS)),) ifneq ($(filter MB86233,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/mb86233 OBJDIRS += $(CPUOBJ)/mb86233
CPUOBJS += $(CPUOBJ)/mb86233/mb86233.o CPUOBJS += $(CPUOBJ)/mb86233/mb86233.o
@ -846,13 +722,7 @@ $(CPUOBJ)/mb86233/mb86233.o: $(CPUSRC)/mb86233/mb86233.c \
# Microchip PIC16C5x # Microchip PIC16C5x
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_PIC16C54=$(if $(filter PIC16C54,$(CPUS)),1,0) ifneq ($(filter PIC16C5X,$(CPUS)),)
CPUDEFS += -DHAS_PIC16C55=$(if $(filter PIC16C55,$(CPUS)),1,0)
CPUDEFS += -DHAS_PIC16C56=$(if $(filter PIC16C56,$(CPUS)),1,0)
CPUDEFS += -DHAS_PIC16C57=$(if $(filter PIC16C57,$(CPUS)),1,0)
CPUDEFS += -DHAS_PIC16C58=$(if $(filter PIC16C58,$(CPUS)),1,0)
ifneq ($(filter PIC16C54 PIC16C55 PIC16C56 PIC16C57 PIC16C58,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/pic16c5x OBJDIRS += $(CPUOBJ)/pic16c5x
CPUOBJS += $(CPUOBJ)/pic16c5x/pic16c5x.o CPUOBJS += $(CPUOBJ)/pic16c5x/pic16c5x.o
DBGOBJS += $(CPUOBJ)/pic16c5x/16c5xdsm.o DBGOBJS += $(CPUOBJ)/pic16c5x/16c5xdsm.o
@ -865,40 +735,23 @@ $(CPUOBJ)/pic16c5x/pic16c5x.o: $(CPUSRC)/pic16c5x/pic16c5x.c \
#------------------------------------------------- #-------------------------------------------------
# MIPS R3000 (MIPS I/II) series # MIPS R3000 (MIPS I/II) series
# MIPS R4000 (MIPS III/IV) series
# Sony PlayStation CPU (R3000-based + GTE)
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_R3000=$(if $(filter R3000,$(CPUS)),1,0) ifneq ($(filter MIPS,$(CPUS)),)
CPUDEFS += -DHAS_R3041=$(if $(filter R3041,$(CPUS)),1,0)
ifneq ($(filter R3000 R3041,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/mips OBJDIRS += $(CPUOBJ)/mips
CPUOBJS += $(CPUOBJ)/mips/r3000.o CPUOBJS += $(CPUOBJ)/mips/r3000.o
CPUOBJS += $(CPUOBJ)/mips/mips3com.o $(CPUOBJ)/mips/mips3fe.o $(CPUOBJ)/mips/mips3drc.o $(DRCOBJ)
CPUOBJS += $(CPUOBJ)/mips/psx.o
DBGOBJS += $(CPUOBJ)/mips/r3kdasm.o DBGOBJS += $(CPUOBJ)/mips/r3kdasm.o
DBGOBJS += $(CPUOBJ)/mips/mips3dsm.o
DBGOBJS += $(CPUOBJ)/mips/psxdasm.o
endif endif
$(CPUOBJ)/mips/r3000.o: $(CPUSRC)/mips/r3000.c \ $(CPUOBJ)/mips/r3000.o: $(CPUSRC)/mips/r3000.c \
$(CPUSRC)/mips/r3000.h $(CPUSRC)/mips/r3000.h
#-------------------------------------------------
# MIPS R4000 (MIPS III/IV) series
#-------------------------------------------------
CPUDEFS += -DHAS_VR4300=$(if $(filter VR4300,$(CPUS)),1,0)
CPUDEFS += -DHAS_R4600=$(if $(filter R4600,$(CPUS)),1,0)
CPUDEFS += -DHAS_R4650=$(if $(filter R4650,$(CPUS)),1,0)
CPUDEFS += -DHAS_R4700=$(if $(filter R4700,$(CPUS)),1,0)
CPUDEFS += -DHAS_R5000=$(if $(filter R5000,$(CPUS)),1,0)
CPUDEFS += -DHAS_QED5271=$(if $(filter QED5271,$(CPUS)),1,0)
CPUDEFS += -DHAS_RM7000=$(if $(filter RM7000,$(CPUS)),1,0)
ifneq ($(filter VR4300 R4600 R4650 R4700 R5000 QED5271 RM7000,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/mips
CPUOBJS += $(CPUOBJ)/mips/mips3com.o $(CPUOBJ)/mips/mips3fe.o $(CPUOBJ)/mips/mips3drc.o $(DRCOBJ)
DBGOBJS += $(CPUOBJ)/mips/mips3dsm.o
endif
$(CPUOBJ)/mips/mips3com.o: $(CPUSRC)/mips/mips3.h \ $(CPUOBJ)/mips/mips3com.o: $(CPUSRC)/mips/mips3.h \
$(CPUSRC)/mips/mips3com.h $(CPUSRC)/mips/mips3com.h
@ -912,16 +765,16 @@ $(CPUOBJ)/mips/mips3drc.o: $(CPUSRC)/mips/mips3drc.c \
$(CPUSRC)/mips/mips3fe.h \ $(CPUSRC)/mips/mips3fe.h \
$(DRCDEPS) $(DRCDEPS)
$(CPUOBJ)/mips/psx.o: $(CPUSRC)/mips/psx.c \
$(CPUSRC)/mips/psx.h
#------------------------------------------------- #-------------------------------------------------
# Mitsubishi M37702 and M37710 (based on 65C816) # Mitsubishi M37702 and M37710 (based on 65C816)
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_M37702=$(if $(filter M37702,$(CPUS)),1,0) ifneq ($(filter M37710,$(CPUS)),)
CPUDEFS += -DHAS_M37710=$(if $(filter M37710,$(CPUS)),1,0)
ifneq ($(filter M37702 M37710,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/m37710 OBJDIRS += $(CPUOBJ)/m37710
CPUOBJS += \ CPUOBJS += \
$(CPUOBJ)/m37710/m37710.o \ $(CPUOBJ)/m37710/m37710.o \
@ -961,39 +814,11 @@ $(CPUOBJ)/m37710/m7700ds.o: $(CPUSRC)/m37710/m7700ds.c \
# Mostek 6502 and its many derivatives # Mostek 6502 and its many derivatives
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_M6502=$(if $(filter M6502,$(CPUS)),1,0) ifneq ($(filter M6502,$(CPUS)),)
CPUDEFS += -DHAS_M65C02=$(if $(filter M65C02,$(CPUS)),1,0)
CPUDEFS += -DHAS_M65SC02=$(if $(filter M65SC02,$(CPUS)),1,0)
CPUDEFS += -DHAS_M65CE02=$(if $(filter M65CE02,$(CPUS)),1,0)
CPUDEFS += -DHAS_M6509=$(if $(filter M6509,$(CPUS)),1,0)
CPUDEFS += -DHAS_M6510=$(if $(filter M6510 M6510T M7501 M8502,$(CPUS)),1,0)
CPUDEFS += -DHAS_M6510T=$(if $(filter M6510T,$(CPUS)),1,0)
CPUDEFS += -DHAS_M7501=$(if $(filter M7501,$(CPUS)),1,0)
CPUDEFS += -DHAS_M8502=$(if $(filter M8502,$(CPUS)),1,0)
CPUDEFS += -DHAS_N2A03=$(if $(filter N2A03,$(CPUS)),1,0)
CPUDEFS += -DHAS_DECO16=$(if $(filter DECO16,$(CPUS)),1,0)
CPUDEFS += -DHAS_M4510=$(if $(filter M4510,$(CPUS)),1,0)
ifneq ($(filter M6502 M65C02 M65SC02 M6510 M6510T M7501 M8502 N2A03 DECO16,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/m6502 OBJDIRS += $(CPUOBJ)/m6502
CPUOBJS += $(CPUOBJ)/m6502/m6502.o CPUOBJS += $(CPUOBJ)/m6502/m6502.o
DBGOBJS += $(CPUOBJ)/m6502/6502dasm.o
endif
ifneq ($(filter M65CE02,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/m6502
CPUOBJS += $(CPUOBJ)/m6502/m65ce02.o
DBGOBJS += $(CPUOBJ)/m6502/6502dasm.o
endif
ifneq ($(filter M6509,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/m6502
CPUOBJS += $(CPUOBJ)/m6502/m6509.o CPUOBJS += $(CPUOBJ)/m6502/m6509.o
DBGOBJS += $(CPUOBJ)/m6502/6502dasm.o CPUOBJS += $(CPUOBJ)/m6502/m65ce02.o
endif
ifneq ($(filter M4510,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/m6502
CPUOBJS += $(CPUOBJ)/m6502/m4510.o CPUOBJS += $(CPUOBJ)/m6502/m4510.o
DBGOBJS += $(CPUOBJ)/m6502/6502dasm.o DBGOBJS += $(CPUOBJ)/m6502/6502dasm.o
endif endif
@ -1023,15 +848,7 @@ $(CPUOBJ)/m6502/m6509.o: $(CPUSRC)/m6502/m6509.c \
# Motorola 680x # Motorola 680x
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_M6800=$(if $(filter M6800,$(CPUS)),1,0) ifneq ($(filter M6800,$(CPUS)),)
CPUDEFS += -DHAS_M6801=$(if $(filter M6801,$(CPUS)),1,0)
CPUDEFS += -DHAS_M6802=$(if $(filter M6802,$(CPUS)),1,0)
CPUDEFS += -DHAS_M6803=$(if $(filter M6803,$(CPUS)),1,0)
CPUDEFS += -DHAS_M6808=$(if $(filter M6808,$(CPUS)),1,0)
CPUDEFS += -DHAS_HD63701=$(if $(filter HD63701,$(CPUS)),1,0)
CPUDEFS += -DHAS_NSC8105=$(if $(filter NSC8105,$(CPUS)),1,0)
ifneq ($(filter M6800 M6801 M6802 M6803 M6808 HD63701 NSC8105,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/m6800 OBJDIRS += $(CPUOBJ)/m6800
CPUOBJS += $(CPUOBJ)/m6800/m6800.o CPUOBJS += $(CPUOBJ)/m6800/m6800.o
DBGOBJS += $(CPUOBJ)/m6800/6800dasm.o DBGOBJS += $(CPUOBJ)/m6800/6800dasm.o
@ -1048,11 +865,7 @@ $(CPUOBJ)/m6800/m6800.o: $(CPUSRC)/m6800/m6800.c \
# Motorola 6805 # Motorola 6805
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_M6805=$(if $(filter M6805,$(CPUS)),1,0) ifneq ($(filter M6805,$(CPUS)),)
CPUDEFS += -DHAS_M68705=$(if $(filter M68705,$(CPUS)),1,0)
CPUDEFS += -DHAS_HD63705=$(if $(filter HD63705,$(CPUS)),1,0)
ifneq ($(filter M6805 M68705 HD63705,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/m6805 OBJDIRS += $(CPUOBJ)/m6805
CPUOBJS += $(CPUOBJ)/m6805/m6805.o CPUOBJS += $(CPUOBJ)/m6805/m6805.o
DBGOBJS += $(CPUOBJ)/m6805/6805dasm.o DBGOBJS += $(CPUOBJ)/m6805/6805dasm.o
@ -1068,10 +881,7 @@ $(CPUOBJ)/m6805/m6805.o: $(CPUSRC)/m6805/m6805.c \
# Motorola 6809 # Motorola 6809
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_M6809=$(if $(filter M6809,$(CPUS)),1,0) ifneq ($(filter M6809,$(CPUS)),)
CPUDEFS += -DHAS_M6809E=$(if $(filter M6809E,$(CPUS)),1,0)
ifneq ($(filter M6809 M6809E,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/m6809 OBJDIRS += $(CPUOBJ)/m6809
CPUOBJS += $(CPUOBJ)/m6809/m6809.o CPUOBJS += $(CPUOBJ)/m6809/m6809.o
DBGOBJS += $(CPUOBJ)/m6809/6809dasm.o DBGOBJS += $(CPUOBJ)/m6809/6809dasm.o
@ -1088,8 +898,6 @@ $(CPUOBJ)/m6809/m6809.o: $(CPUSRC)/m6809/m6809.c \
# Motorola 68HC11 # Motorola 68HC11
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_MC68HC11=$(if $(filter MC68HC11,$(CPUS)),1,0)
ifneq ($(filter MC68HC11,$(CPUS)),) ifneq ($(filter MC68HC11,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/mc68hc11 OBJDIRS += $(CPUOBJ)/mc68hc11
CPUOBJS += $(CPUOBJ)/mc68hc11/mc68hc11.o CPUOBJS += $(CPUOBJ)/mc68hc11/mc68hc11.o
@ -1105,8 +913,6 @@ $(CPUOBJ)/mc68hc11/mc68hc11.o: $(CPUSRC)/mc68hc11/mc68hc11.c \
# Motorola 68000 series # Motorola 68000 series
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_M680X0=$(if $(filter M680X0,$(CPUS)),1,0)
ifneq ($(filter M680X0,$(CPUS)),) ifneq ($(filter M680X0,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/m68000 OBJDIRS += $(CPUOBJ)/m68000
CPUOBJS += $(CPUOBJ)/m68000/m68kcpu.o $(CPUOBJ)/m68000/m68kops.o CPUOBJS += $(CPUOBJ)/m68000/m68kcpu.o $(CPUOBJ)/m68000/m68kops.o
@ -1149,8 +955,6 @@ $(CPUOBJ)/m68000/m68kcpu.o: $(CPUOBJ)/m68000/m68kops.c \
# Motorola/Freescale dsp56k # Motorola/Freescale dsp56k
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_DSP56156=$(if $(filter DSP56156,$(CPUS)),1,0)
ifneq ($(filter DSP56156,$(CPUS)),) ifneq ($(filter DSP56156,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/dsp56k OBJDIRS += $(CPUOBJ)/dsp56k
CPUOBJS += $(CPUOBJ)/dsp56k/dsp56k.o CPUOBJS += $(CPUOBJ)/dsp56k/dsp56k.o
@ -1165,27 +969,31 @@ $(CPUOBJ)/dsp56k/dsp56k.o: $(CPUSRC)/dsp56k/dsp56k.c \
#------------------------------------------------- #-------------------------------------------------
# PDP-1 # PDP-1
# TX0
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_PDP1=$(if $(filter PDP1,$(CPUS)),1,0)
ifneq ($(filter PDP1,$(CPUS)),) ifneq ($(filter PDP1,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/pdp1 OBJDIRS += $(CPUOBJ)/pdp1
CPUOBJS += $(CPUOBJ)/pdp1/pdp1.o CPUOBJS += $(CPUOBJ)/pdp1/pdp1.o
CPUOBJS += $(CPUOBJ)/pdp1/tx0.o
DBGOBJS += $(CPUOBJ)/pdp1/pdp1dasm.o DBGOBJS += $(CPUOBJ)/pdp1/pdp1dasm.o
DBGOBJS += $(CPUOBJ)/pdp1/tx0dasm.o
endif endif
$(CPUOBJ)/pdp1/pdp1.o: $(CPUSRC)/pdp1/pdp1.c \ $(CPUOBJ)/pdp1/pdp1.o: $(CPUSRC)/pdp1/pdp1.c \
$(CPUSRC)/pdp1/pdp1.h $(CPUSRC)/pdp1/pdp1.h
$(CPUOBJ)/pdp1/tx0.o: $(CPUSRC)/pdp1/tx0.h \
$(CPUSRC)/pdp1/tx0.c
$(CPUOBJ)/pdp1/tx0dasm.o: $(CPUSRC)/pdp1/tx0.h \
$(CPUSRC)/pdp1/tx0dasm.c
#------------------------------------------------- #-------------------------------------------------
# Motorola PowerPC series # Motorola PowerPC series
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_POWERPC=$(if $(filter POWERPC,$(CPUS)),1,0)
ifneq ($(filter POWERPC,$(CPUS)),) ifneq ($(filter POWERPC,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/powerpc OBJDIRS += $(CPUOBJ)/powerpc
CPUOBJS += $(CPUOBJ)/powerpc/ppccom.o $(CPUOBJ)/powerpc/ppcfe.o $(CPUOBJ)/powerpc/ppcdrc.o $(DRCOBJ) CPUOBJS += $(CPUOBJ)/powerpc/ppccom.o $(CPUOBJ)/powerpc/ppcfe.o $(CPUOBJ)/powerpc/ppcdrc.o $(DRCOBJ)
@ -1211,14 +1019,7 @@ $(CPUOBJ)/powerpc/ppcdrc.o: $(CPUSRC)/powerpc/ppcdrc.c \
# NEC V-series Intel-compatible # NEC V-series Intel-compatible
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_V20=$(if $(filter V20,$(CPUS)),1,0) ifneq ($(filter NEC,$(CPUS)),)
CPUDEFS += -DHAS_V25=$(if $(filter V25,$(CPUS)),1,0)
CPUDEFS += -DHAS_V30=$(if $(filter V30,$(CPUS)),1,0)
CPUDEFS += -DHAS_V30MZ=$(if $(filter V30MZ,$(CPUS)),1,0)
CPUDEFS += -DHAS_V33=$(if $(filter V33,$(CPUS)),1,0)
CPUDEFS += -DHAS_V35=$(if $(filter V35,$(CPUS)),1,0)
ifneq ($(filter V20 V25 V30 V33 V35,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/nec OBJDIRS += $(CPUOBJ)/nec
CPUOBJS += $(CPUOBJ)/nec/nec.o CPUOBJS += $(CPUOBJ)/nec/nec.o
DBGOBJS += $(CPUOBJ)/nec/necdasm.o DBGOBJS += $(CPUOBJ)/nec/necdasm.o
@ -1252,10 +1053,7 @@ $(CPUOBJ)/v30mz/v30mz.o: $(CPUSRC)/v30mz/v30mz.c \
# NEC V60/V70 # NEC V60/V70
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_V60=$(if $(filter V60,$(CPUS)),1,0) ifneq ($(filter V60,$(CPUS)),)
CPUDEFS += -DHAS_V70=$(if $(filter V70,$(CPUS)),1,0)
ifneq ($(filter V60 V70,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/v60 OBJDIRS += $(CPUOBJ)/v60
CPUOBJS += $(CPUOBJ)/v60/v60.o CPUOBJS += $(CPUOBJ)/v60/v60.o
DBGOBJS += $(CPUOBJ)/v60/v60d.o DBGOBJS += $(CPUOBJ)/v60/v60d.o
@ -1283,8 +1081,6 @@ $(CPUOBJ)/v60/v60.o: $(CPUSRC)/v60/am.c \
# NEC V810 (uPD70732) # NEC V810 (uPD70732)
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_V810=$(if $(filter V810,$(CPUS)),1,0)
ifneq ($(filter V810,$(CPUS)),) ifneq ($(filter V810,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/v810 OBJDIRS += $(CPUOBJ)/v810
CPUOBJS += $(CPUOBJ)/v810/v810.o CPUOBJS += $(CPUOBJ)/v810/v810.o
@ -1300,11 +1096,7 @@ $(CPUOBJ)/v810/v810.o: $(CPUSRC)/v810/v810.c \
# NEC uPD7810 series # NEC uPD7810 series
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_UPD7810=$(if $(filter UPD7810,$(CPUS)),1,0) ifneq ($(filter UPD7810,$(CPUS)),)
CPUDEFS += -DHAS_UPD7807=$(if $(filter UPD7807,$(CPUS)),1,0)
CPUDEFS += -DHAS_UPD7801=$(if $(filter UPD7801,$(CPUS)),1,0)
ifneq ($(filter UPD7810 UPD7807 UPD7801,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/upd7810 OBJDIRS += $(CPUOBJ)/upd7810
CPUOBJS += $(CPUOBJ)/upd7810/upd7810.o CPUOBJS += $(CPUOBJ)/upd7810/upd7810.o
DBGOBJS += $(CPUOBJ)/upd7810/7810dasm.o DBGOBJS += $(CPUOBJ)/upd7810/7810dasm.o
@ -1321,8 +1113,6 @@ $(CPUOBJ)/upd7810/upd7810.o: $(CPUSRC)/upd7810/upd7810.c \
# Nintendo Minx # Nintendo Minx
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_MINX=$(if $(filter MINX,$(CPUS)),1,0)
ifneq ($(filter MINX,$(CPUS)),) ifneq ($(filter MINX,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/minx OBJDIRS += $(CPUOBJ)/minx
CPUOBJS += $(CPUOBJ)/minx/minx.o CPUOBJS += $(CPUOBJ)/minx/minx.o
@ -1343,8 +1133,6 @@ $(CPUOBJ)/minx/minx.o: $(CPUSRC)/minx/minx.c \
# Nintendo/SGI RSP (R3000-based + vector processing) # Nintendo/SGI RSP (R3000-based + vector processing)
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_RSP=$(if $(filter RSP,$(CPUS)),1,0)
ifneq ($(filter RSP,$(CPUS)),) ifneq ($(filter RSP,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/rsp OBJDIRS += $(CPUOBJ)/rsp
CPUOBJS += $(CPUOBJ)/rsp/rsp.o CPUOBJS += $(CPUOBJ)/rsp/rsp.o
@ -1360,8 +1148,6 @@ $(CPUOBJ)/rsp/rsp.o: $(CPUSRC)/rsp/rsp.c \
# Saturn # Saturn
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_SATURN=$(if $(filter SATURN,$(CPUS)),1,0)
ifneq ($(filter SATURN,$(CPUS)),) ifneq ($(filter SATURN,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/saturn OBJDIRS += $(CPUOBJ)/saturn
CPUOBJS += $(CPUOBJ)/saturn/saturn.o CPUOBJS += $(CPUOBJ)/saturn/saturn.o
@ -1379,8 +1165,6 @@ $(CPUOBJ)/saturn/saturn.o: $(CPUSRC)/saturn/saturn.c \
# Signetics 2650 # Signetics 2650
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_S2650=$(if $(filter S2650,$(CPUS)),1,0)
ifneq ($(filter S2650,$(CPUS)),) ifneq ($(filter S2650,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/s2650 OBJDIRS += $(CPUOBJ)/s2650
CPUOBJS += $(CPUOBJ)/s2650/s2650.o CPUOBJS += $(CPUOBJ)/s2650/s2650.o
@ -1397,8 +1181,6 @@ $(CPUOBJ)/s2650/s2650.o: $(CPUSRC)/s2650/s2650.c \
# SC61860 # SC61860
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_SC61860=$(if $(filter SC61860,$(CPUS)),1,0)
ifneq ($(filter SC61860,$(CPUS)),) ifneq ($(filter SC61860,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/sc61860 OBJDIRS += $(CPUOBJ)/sc61860
CPUOBJS += $(CPUOBJ)/sc61860/sc61860.o CPUOBJS += $(CPUOBJ)/sc61860/sc61860.o
@ -1416,8 +1198,6 @@ $(CPUOBJ)/sc61860/sc61860.o: $(CPUSRC)/sc61860/sc61860.h \
# SM8500 # SM8500
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_SM8500=$(if $(filter SM8500,$(CPUS)),1,0)
ifneq ($(filter SM8500,$(CPUS)),) ifneq ($(filter SM8500,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/sm8500 OBJDIRS += $(CPUOBJ)/sm8500
CPUOBJS += $(CPUOBJ)/sm8500/sm8500.o CPUOBJS += $(CPUOBJ)/sm8500/sm8500.o
@ -1434,8 +1214,6 @@ $(CPUOBJ)/sm8500/sm8500.o: $(CPUSRC)/sm8500/sm8500.c \
# Sony/Nintendo SPC700 # Sony/Nintendo SPC700
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_SPC700=$(if $(filter SPC700,$(CPUS)),1,0)
ifneq ($(filter SPC700,$(CPUS)),) ifneq ($(filter SPC700,$(CPUS)),)
SPCD = cpu/spc700 SPCD = cpu/spc700
OBJDIRS += $(CPUOBJ)/spc700 OBJDIRS += $(CPUOBJ)/spc700
@ -1448,30 +1226,10 @@ $(CPUOBJ)/spc700/spc700.o: $(CPUSRC)/spc700/spc700.c \
#-------------------------------------------------
# Sony PlayStation CPU (R3000-based + GTE)
#-------------------------------------------------
CPUDEFS += -DHAS_PSXCPU=$(if $(filter PSXCPU,$(CPUS)),1,0)
CPUDEFS += -DHAS_CXD8661R=$(if $(filter CXD8661R,$(CPUS)),1,0)
ifneq ($(filter PSXCPU CXD8661R,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/mips
CPUOBJS += $(CPUOBJ)/mips/psx.o
DBGOBJS += $(CPUOBJ)/mips/psxdasm.o
endif
$(CPUOBJ)/mips/psx.o: $(CPUSRC)/mips/psx.c \
$(CPUSRC)/mips/psx.h
#------------------------------------------------- #-------------------------------------------------
# SSP1601 # SSP1601
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_SSP1601=$(if $(filter SSP1601,$(CPUS)),1,0)
ifneq ($(filter SSP1601,$(CPUS)),) ifneq ($(filter SSP1601,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/ssp1601 OBJDIRS += $(CPUOBJ)/ssp1601
CPUOBJS += $(CPUOBJ)/ssp1601/ssp1601.o CPUOBJS += $(CPUOBJ)/ssp1601/ssp1601.o
@ -1487,10 +1245,7 @@ $(CPUOBJ)/ssp1610/ssp1601.o: $(CPUSRC)/ssp1601/ssp1601.c \
# Texas Instruments TMS7000 series # Texas Instruments TMS7000 series
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_TMS7000=$(if $(filter TMS7000,$(CPUS)),1,0) ifneq ($(filter TMS7000,$(CPUS)),)
CPUDEFS += -DHAS_TMS7000_EXL=$(if $(filter TMS7000_EXL,$(CPUS)),1,0)
ifneq ($(filter TMS7000 TMS7000_EXL,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/tms7000 OBJDIRS += $(CPUOBJ)/tms7000
CPUOBJS += $(CPUOBJ)/tms7000/tms7000.o CPUOBJS += $(CPUOBJ)/tms7000/tms7000.o
DBGOBJS += $(CPUOBJ)/tms7000/7000dasm.o DBGOBJS += $(CPUOBJ)/tms7000/7000dasm.o
@ -1508,37 +1263,11 @@ $(CPUOBJ)/tms7000/7000dasm.o: $(CPUSRC)/tms7000/tms7000.h \
# Texas Instruments TMS99xx series # Texas Instruments TMS99xx series
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_TMS9900=$(if $(filter TMS9900,$(CPUS)),1,0) ifneq ($(filter TMS9900,$(CPUS)),)
CPUDEFS += -DHAS_TMS9940=$(if $(filter TMS9940,$(CPUS)),1,0)
CPUDEFS += -DHAS_TMS9980=$(if $(filter TMS9980,$(CPUS)),1,0)
CPUDEFS += -DHAS_TMS9985=$(if $(filter TMS9985,$(CPUS)),1,0)
CPUDEFS += -DHAS_TMS9989=$(if $(filter TMS9989,$(CPUS)),1,0)
CPUDEFS += -DHAS_TMS9995=$(if $(filter TMS9995,$(CPUS)),1,0)
CPUDEFS += -DHAS_TMS99105A=$(if $(filter TMS99105A,$(CPUS)),1,0)
CPUDEFS += -DHAS_TMS99110A=$(if $(filter TMS99110A,$(CPUS)),1,0)
CPUDEFS += -DHAS_TMS99000=$(if $(filter TMS99000,$(CPUS)),1,0)
CPUDEFS += -DHAS_TI990_10=$(if $(filter TMS99010,$(CPUS)),1,0)
ifneq ($(filter TMS9900 TMS9940 TMS99000,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/tms9900 OBJDIRS += $(CPUOBJ)/tms9900
CPUOBJS += $(CPUOBJ)/tms9900/tms9900.o CPUOBJS += $(CPUOBJ)/tms9900/tms9900.o
DBGOBJS += $(CPUOBJ)/tms9900/9900dasm.o
endif
ifneq ($(filter TMS9980 TMS9985 TMS9989,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/tms9900
CPUOBJS += $(CPUOBJ)/tms9900/tms9980a.o CPUOBJS += $(CPUOBJ)/tms9900/tms9980a.o
DBGOBJS += $(CPUOBJ)/tms9900/9900dasm.o
endif
ifneq ($(filter TMS9995 TMS99105A TMS99110A,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/tms9900
CPUOBJS += $(CPUOBJ)/tms9900/tms9995.o CPUOBJS += $(CPUOBJ)/tms9900/tms9995.o
DBGOBJS += $(CPUOBJ)/tms9900/9900dasm.o
endif
ifneq ($(filter TMS99010,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/tms9900
CPUOBJS += $(CPUOBJ)/tms9900/ti990_10.o CPUOBJS += $(CPUOBJ)/tms9900/ti990_10.o
DBGOBJS += $(CPUOBJ)/tms9900/9900dasm.o DBGOBJS += $(CPUOBJ)/tms9900/9900dasm.o
endif endif
@ -1569,8 +1298,6 @@ $(CPUOBJ)/tms9900/ti990_10.o: $(CPUSRC)/tms9900/ti990_10.c \
# Texas Instruments TMS340x0 graphics controllers # Texas Instruments TMS340x0 graphics controllers
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_TMS340X0=$(if $(filter TMS340X0,$(CPUS)),1,0)
ifneq ($(filter TMS340X0,$(CPUS)),) ifneq ($(filter TMS340X0,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/tms34010 OBJDIRS += $(CPUOBJ)/tms34010
CPUOBJS += $(CPUOBJ)/tms34010/tms34010.o CPUOBJS += $(CPUOBJ)/tms34010/tms34010.o
@ -1590,8 +1317,6 @@ $(CPUOBJ)/tms34010/tms34010.o: $(CPUSRC)/tms34010/tms34010.c \
# Texas Instruments TMS3201x DSP # Texas Instruments TMS3201x DSP
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_TMS32010=$(if $(filter TMS32010,$(CPUS)),1,0)
ifneq ($(filter TMS32010,$(CPUS)),) ifneq ($(filter TMS32010,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/tms32010 OBJDIRS += $(CPUOBJ)/tms32010
CPUOBJS += $(CPUOBJ)/tms32010/tms32010.o CPUOBJS += $(CPUOBJ)/tms32010/tms32010.o
@ -1607,10 +1332,7 @@ $(CPUOBJ)/tms32010/tms32010.o: $(CPUSRC)/tms32010/tms32010.c \
# Texas Instruments TMS3202x DSP # Texas Instruments TMS3202x DSP
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_TMS32025=$(if $(filter TMS32025,$(CPUS)),1,0) ifneq ($(filter TMS32025,$(CPUS)),)
CPUDEFS += -DHAS_TMS32026=$(if $(filter TMS32026,$(CPUS)),1,0)
ifneq ($(filter TMS32025 TMS32026,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/tms32025 OBJDIRS += $(CPUOBJ)/tms32025
CPUOBJS += $(CPUOBJ)/tms32025/tms32025.o CPUOBJS += $(CPUOBJ)/tms32025/tms32025.o
DBGOBJS += $(CPUOBJ)/tms32025/32025dsm.o DBGOBJS += $(CPUOBJ)/tms32025/32025dsm.o
@ -1625,10 +1347,7 @@ $(CPUOBJ)/tms32025/tms32025.o: $(CPUSRC)/tms32025/tms32025.c \
# Texas Instruments TMS3203x DSP # Texas Instruments TMS3203x DSP
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_TMS32031=$(if $(filter TMS32031,$(CPUS)),1,0) ifneq ($(filter TMS32031,$(CPUS)),)
CPUDEFS += -DHAS_TMS32032=$(if $(filter TMS32032,$(CPUS)),1,0)
ifneq ($(filter TMS32031 TMS32032,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/tms32031 OBJDIRS += $(CPUOBJ)/tms32031
CPUOBJS += $(CPUOBJ)/tms32031/tms32031.o CPUOBJS += $(CPUOBJ)/tms32031/tms32031.o
DBGOBJS += $(CPUOBJ)/tms32031/dis32031.o DBGOBJS += $(CPUOBJ)/tms32031/dis32031.o
@ -1644,8 +1363,6 @@ $(CPUOBJ)/tms32031/tms32031.o: $(CPUSRC)/tms32031/tms32031.c \
# Texas Instruments TMS3205x DSP # Texas Instruments TMS3205x DSP
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_TMS32051=$(if $(filter TMS32051,$(CPUS)),1,0)
ifneq ($(filter TMS32051,$(CPUS)),) ifneq ($(filter TMS32051,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/tms32051 OBJDIRS += $(CPUOBJ)/tms32051
CPUOBJS += $(CPUOBJ)/tms32051/tms32051.o CPUOBJS += $(CPUOBJ)/tms32051/tms32051.o
@ -1661,8 +1378,6 @@ $(CPUOBJ)/tms32051/tms32051.o: $(CPUSRC)/tms32051/tms32051.c \
# Texas Instruments TMS57002 DSP # Texas Instruments TMS57002 DSP
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_TMS57002=$(if $(filter TMS57002,$(CPUS)),1,0)
ifneq ($(filter TMS57002,$(CPUS)),) ifneq ($(filter TMS57002,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/tms57002 OBJDIRS += $(CPUOBJ)/tms57002
CPUOBJS += $(CPUOBJ)/tms57002/tms57002.o CPUOBJS += $(CPUOBJ)/tms57002/tms57002.o
@ -1694,8 +1409,6 @@ endif
# Toshiba TLCS-90 Series # Toshiba TLCS-90 Series
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_TLCS90=$(if $(filter TLCS90,$(CPUS)),1,0)
ifneq ($(filter TLCS90,$(CPUS)),) ifneq ($(filter TLCS90,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/tlcs90 OBJDIRS += $(CPUOBJ)/tlcs90
CPUOBJS += $(CPUOBJ)/tlcs90/tlcs90.o CPUOBJS += $(CPUOBJ)/tlcs90/tlcs90.o
@ -1707,33 +1420,10 @@ $(CPUOBJ)/tlcs90/tlcs90.o: $(CPUSRC)/tlcs90/tlcs90.c \
#-------------------------------------------------
# TX0
#-------------------------------------------------
CPUDEFS += -DHAS_TX0_64KW=$(if $(filter TX0,$(CPUS)),1,0)
CPUDEFS += -DHAS_TX0_8KW=$(if $(filter TX0,$(CPUS)),1,0)
ifneq ($(filter TX0,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/pdp1
CPUOBJS += $(CPUOBJ)/pdp1/tx0.o
DBGOBJS += $(CPUOBJ)/pdp1/tx0dasm.o
endif
$(CPUOBJ)/pdp1/tx0.o: $(CPUSRC)/pdp1/tx0.h \
$(CPUSRC)/pdp1/tx0.c
$(CPUOBJ)/pdp1/tx0dasm.o: $(CPUSRC)/pdp1/tx0.h \
$(CPUSRC)/pdp1/tx0dasm.c
#------------------------------------------------- #-------------------------------------------------
# Zilog Z80 # Zilog Z80
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_Z80=$(if $(filter Z80,$(CPUS)),1,0)
ifneq ($(filter Z80,$(CPUS)),) ifneq ($(filter Z80,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/z80 OBJDIRS += $(CPUOBJ)/z80
CPUOBJS += $(CPUOBJ)/z80/z80.o $(CPUOBJ)/z80/z80daisy.o CPUOBJS += $(CPUOBJ)/z80/z80.o $(CPUOBJ)/z80/z80daisy.o
@ -1749,8 +1439,6 @@ $(CPUOBJ)/z80/z80.o: $(CPUSRC)/z80/z80.c \
# Sharp LR35902 (Game Boy CPU) # Sharp LR35902 (Game Boy CPU)
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_LR35902=$(if $(filter LR35902,$(CPUS)),1,0)
ifneq ($(filter LR35902,$(CPUS)),) ifneq ($(filter LR35902,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/lr35902 OBJDIRS += $(CPUOBJ)/lr35902
CPUOBJS += $(CPUOBJ)/lr35902/lr35902.o CPUOBJS += $(CPUOBJ)/lr35902/lr35902.o
@ -1768,8 +1456,6 @@ $(CPUOBJ)/lr35902/lr35902.o: $(CPUSRC)/lr35902/lr35902.c \
# Zilog Z180 # Zilog Z180
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_Z180=$(if $(filter Z180,$(CPUS)),1,0)
ifneq ($(filter Z180,$(CPUS)),) ifneq ($(filter Z180,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/z180 $(CPUOBJ)/z80 OBJDIRS += $(CPUOBJ)/z180 $(CPUOBJ)/z80
CPUOBJS += $(CPUOBJ)/z180/z180.o $(CPUOBJ)/z80/z80daisy.o CPUOBJS += $(CPUOBJ)/z180/z180.o $(CPUOBJ)/z80/z80daisy.o
@ -1794,8 +1480,6 @@ $(CPUOBJ)/z180/z180.o: $(CPUSRC)/z180/z180.c \
# Zilog Z8000 # Zilog Z8000
#------------------------------------------------- #-------------------------------------------------
CPUDEFS += -DHAS_Z8000=$(if $(filter Z8000,$(CPUS)),1,0)
ifneq ($(filter Z8000,$(CPUS)),) ifneq ($(filter Z8000,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/z8000 OBJDIRS += $(CPUOBJ)/z8000
CPUOBJS += $(CPUOBJ)/z8000/z8000.o CPUOBJS += $(CPUOBJ)/z8000/z8000.o

View File

@ -377,57 +377,45 @@ static void check_interrupts(hyperstone_state *cpustate);
#define SAME_SRCF_DST (decode)->same_srcf_dst #define SAME_SRCF_DST (decode)->same_srcf_dst
// 4Kb IRAM (On-Chip Memory) // 4Kb IRAM (On-Chip Memory)
#if (HAS_E116T || HAS_GMS30C2116)
static ADDRESS_MAP_START( e116_4k_iram_map, ADDRESS_SPACE_PROGRAM, 16 ) static ADDRESS_MAP_START( e116_4k_iram_map, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM AM_MIRROR(0x1ffff000) AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM AM_MIRROR(0x1ffff000)
ADDRESS_MAP_END ADDRESS_MAP_END
#endif
#if (HAS_E132N || HAS_E132T || HAS_GMS30C2132)
static ADDRESS_MAP_START( e132_4k_iram_map, ADDRESS_SPACE_PROGRAM, 32 ) static ADDRESS_MAP_START( e132_4k_iram_map, ADDRESS_SPACE_PROGRAM, 32 )
AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM AM_MIRROR(0x1ffff000) AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM AM_MIRROR(0x1ffff000)
ADDRESS_MAP_END ADDRESS_MAP_END
#endif
// 8Kb IRAM (On-Chip Memory) // 8Kb IRAM (On-Chip Memory)
#if (HAS_E116XT || HAS_GMS30C2216)
static ADDRESS_MAP_START( e116_8k_iram_map, ADDRESS_SPACE_PROGRAM, 16 ) static ADDRESS_MAP_START( e116_8k_iram_map, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0xc0000000, 0xc0001fff) AM_RAM AM_MIRROR(0x1fffe000) AM_RANGE(0xc0000000, 0xc0001fff) AM_RAM AM_MIRROR(0x1fffe000)
ADDRESS_MAP_END ADDRESS_MAP_END
#endif
#if (HAS_E132XN || HAS_E132XT || HAS_GMS30C2232)
static ADDRESS_MAP_START( e132_8k_iram_map, ADDRESS_SPACE_PROGRAM, 32 ) static ADDRESS_MAP_START( e132_8k_iram_map, ADDRESS_SPACE_PROGRAM, 32 )
AM_RANGE(0xc0000000, 0xc0001fff) AM_RAM AM_MIRROR(0x1fffe000) AM_RANGE(0xc0000000, 0xc0001fff) AM_RAM AM_MIRROR(0x1fffe000)
ADDRESS_MAP_END ADDRESS_MAP_END
#endif
// 16Kb IRAM (On-Chip Memory) // 16Kb IRAM (On-Chip Memory)
#if (HAS_E116XS || HAS_E116XSR)
static ADDRESS_MAP_START( e116_16k_iram_map, ADDRESS_SPACE_PROGRAM, 16 ) static ADDRESS_MAP_START( e116_16k_iram_map, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0xc0000000, 0xc0003fff) AM_RAM AM_MIRROR(0x1fffc000) AM_RANGE(0xc0000000, 0xc0003fff) AM_RAM AM_MIRROR(0x1fffc000)
ADDRESS_MAP_END ADDRESS_MAP_END
#endif
#if (HAS_E132XS || HAS_E132XSR)
static ADDRESS_MAP_START( e132_16k_iram_map, ADDRESS_SPACE_PROGRAM, 32 ) static ADDRESS_MAP_START( e132_16k_iram_map, ADDRESS_SPACE_PROGRAM, 32 )
AM_RANGE(0xc0000000, 0xc0003fff) AM_RAM AM_MIRROR(0x1fffc000) AM_RANGE(0xc0000000, 0xc0003fff) AM_RAM AM_MIRROR(0x1fffc000)
ADDRESS_MAP_END ADDRESS_MAP_END
#endif
INLINE hyperstone_state *get_safe_token(const device_config *device) INLINE hyperstone_state *get_safe_token(const device_config *device)
{ {
@ -1565,121 +1553,89 @@ static void hyperstone_init(const device_config *device, cpu_irq_callback irqcal
cpustate->clock_scale_mask = scale_mask; cpustate->clock_scale_mask = scale_mask;
} }
#if (HAS_E116T || HAS_E116XT || HAS_E116XS || HAS_E116XSR || HAS_GMS30C2116 || HAS_GMS30C2216)
static void e116_init(const device_config *device, cpu_irq_callback irqcallback, int scale_mask) static void e116_init(const device_config *device, cpu_irq_callback irqcallback, int scale_mask)
{ {
hyperstone_state *cpustate = get_safe_token(device); hyperstone_state *cpustate = get_safe_token(device);
hyperstone_init(device, irqcallback, scale_mask); hyperstone_init(device, irqcallback, scale_mask);
cpustate->opcodexor = 0; cpustate->opcodexor = 0;
} }
#endif
#if (HAS_E116T)
static CPU_INIT( e116t ) static CPU_INIT( e116t )
{ {
e116_init(device, irqcallback, 0); e116_init(device, irqcallback, 0);
} }
#endif
#if (HAS_E116XT)
static CPU_INIT( e116xt ) static CPU_INIT( e116xt )
{ {
e116_init(device, irqcallback, 3); e116_init(device, irqcallback, 3);
} }
#endif
#if (HAS_E116XS)
static CPU_INIT( e116xs ) static CPU_INIT( e116xs )
{ {
e116_init(device, irqcallback, 7); e116_init(device, irqcallback, 7);
} }
#endif
#if (HAS_E116XSR)
static CPU_INIT( e116xsr ) static CPU_INIT( e116xsr )
{ {
e116_init(device, irqcallback, 7); e116_init(device, irqcallback, 7);
} }
#endif
#if (HAS_GMS30C2116)
static CPU_INIT( gms30c2116 ) static CPU_INIT( gms30c2116 )
{ {
e116_init(device, irqcallback, 0); e116_init(device, irqcallback, 0);
} }
#endif
#if (HAS_GMS30C2216)
static CPU_INIT( gms30c2216 ) static CPU_INIT( gms30c2216 )
{ {
e116_init(device, irqcallback, 0); e116_init(device, irqcallback, 0);
} }
#endif
#if (HAS_E132N || HAS_E132T || HAS_E132XN || HAS_E132XT || HAS_E132XS || HAS_E132XSR || HAS_GMS30C2132 || HAS_GMS30C2232)
static void e132_init(const device_config *device, cpu_irq_callback irqcallback, int scale_mask) static void e132_init(const device_config *device, cpu_irq_callback irqcallback, int scale_mask)
{ {
hyperstone_state *cpustate = get_safe_token(device); hyperstone_state *cpustate = get_safe_token(device);
hyperstone_init(device, irqcallback, scale_mask); hyperstone_init(device, irqcallback, scale_mask);
cpustate->opcodexor = WORD_XOR_BE(0); cpustate->opcodexor = WORD_XOR_BE(0);
} }
#endif
#if (HAS_E132N)
static CPU_INIT( e132n ) static CPU_INIT( e132n )
{ {
e132_init(device, irqcallback, 0); e132_init(device, irqcallback, 0);
} }
#endif
#if (HAS_E132T)
static CPU_INIT( e132t ) static CPU_INIT( e132t )
{ {
e132_init(device, irqcallback, 0); e132_init(device, irqcallback, 0);
} }
#endif
#if (HAS_E132XN)
static CPU_INIT( e132xn ) static CPU_INIT( e132xn )
{ {
e132_init(device, irqcallback, 3); e132_init(device, irqcallback, 3);
} }
#endif
#if (HAS_E132XT)
static CPU_INIT( e132xt ) static CPU_INIT( e132xt )
{ {
e132_init(device, irqcallback, 3); e132_init(device, irqcallback, 3);
} }
#endif
#if (HAS_E132XS)
static CPU_INIT( e132xs ) static CPU_INIT( e132xs )
{ {
e132_init(device, irqcallback, 7); e132_init(device, irqcallback, 7);
} }
#endif
#if (HAS_E132XSR)
static CPU_INIT( e132xsr ) static CPU_INIT( e132xsr )
{ {
e132_init(device, irqcallback, 7); e132_init(device, irqcallback, 7);
} }
#endif
#if (HAS_GMS30C2132)
static CPU_INIT( gms30c2132 ) static CPU_INIT( gms30c2132 )
{ {
e132_init(device, irqcallback, 0); e132_init(device, irqcallback, 0);
} }
#endif
#if (HAS_GMS30C2232)
static CPU_INIT( gms30c2232 ) static CPU_INIT( gms30c2232 )
{ {
e132_init(device, irqcallback, 0); e132_init(device, irqcallback, 0);
} }
#endif
static CPU_RESET( hyperstone ) static CPU_RESET( hyperstone )
{ {
@ -5190,7 +5146,6 @@ static CPU_GET_INFO( hyperstone )
} }
#if (HAS_E116T)
CPU_GET_INFO( e116t ) CPU_GET_INFO( e116t )
{ {
switch (state) switch (state)
@ -5211,9 +5166,7 @@ CPU_GET_INFO( e116t )
CPU_GET_INFO_CALL(hyperstone); CPU_GET_INFO_CALL(hyperstone);
} }
} }
#endif
#if (HAS_E116XT)
CPU_GET_INFO( e116xt ) CPU_GET_INFO( e116xt )
{ {
switch (state) switch (state)
@ -5234,9 +5187,7 @@ CPU_GET_INFO( e116xt )
CPU_GET_INFO_CALL(hyperstone); CPU_GET_INFO_CALL(hyperstone);
} }
} }
#endif
#if (HAS_E116XS)
CPU_GET_INFO( e116xs ) CPU_GET_INFO( e116xs )
{ {
switch (state) switch (state)
@ -5257,9 +5208,7 @@ CPU_GET_INFO( e116xs )
CPU_GET_INFO_CALL(hyperstone); CPU_GET_INFO_CALL(hyperstone);
} }
} }
#endif
#if (HAS_E116XSR)
CPU_GET_INFO( e116xsr ) CPU_GET_INFO( e116xsr )
{ {
switch (state) switch (state)
@ -5280,9 +5229,7 @@ CPU_GET_INFO( e116xsr )
CPU_GET_INFO_CALL(hyperstone); CPU_GET_INFO_CALL(hyperstone);
} }
} }
#endif
#if (HAS_E132N)
CPU_GET_INFO( e132n ) CPU_GET_INFO( e132n )
{ {
switch (state) switch (state)
@ -5303,9 +5250,7 @@ CPU_GET_INFO( e132n )
CPU_GET_INFO_CALL(hyperstone); CPU_GET_INFO_CALL(hyperstone);
} }
} }
#endif
#if (HAS_E132T)
CPU_GET_INFO( e132t ) CPU_GET_INFO( e132t )
{ {
switch (state) switch (state)
@ -5326,9 +5271,7 @@ CPU_GET_INFO( e132t )
CPU_GET_INFO_CALL(hyperstone); CPU_GET_INFO_CALL(hyperstone);
} }
} }
#endif
#if (HAS_E132XN)
CPU_GET_INFO( e132xn ) CPU_GET_INFO( e132xn )
{ {
switch (state) switch (state)
@ -5349,9 +5292,7 @@ CPU_GET_INFO( e132xn )
CPU_GET_INFO_CALL(hyperstone); CPU_GET_INFO_CALL(hyperstone);
} }
} }
#endif
#if (HAS_E132XT)
CPU_GET_INFO( e132xt ) CPU_GET_INFO( e132xt )
{ {
switch (state) switch (state)
@ -5372,9 +5313,7 @@ CPU_GET_INFO( e132xt )
CPU_GET_INFO_CALL(hyperstone); CPU_GET_INFO_CALL(hyperstone);
} }
} }
#endif
#if (HAS_E132XS)
CPU_GET_INFO( e132xs ) CPU_GET_INFO( e132xs )
{ {
switch (state) switch (state)
@ -5395,9 +5334,7 @@ CPU_GET_INFO( e132xs )
CPU_GET_INFO_CALL(hyperstone); CPU_GET_INFO_CALL(hyperstone);
} }
} }
#endif
#if (HAS_E132XSR)
CPU_GET_INFO( e132xsr ) CPU_GET_INFO( e132xsr )
{ {
switch (state) switch (state)
@ -5418,9 +5355,7 @@ CPU_GET_INFO( e132xsr )
CPU_GET_INFO_CALL(hyperstone); CPU_GET_INFO_CALL(hyperstone);
} }
} }
#endif
#if (HAS_GMS30C2116)
CPU_GET_INFO( gms30c2116 ) CPU_GET_INFO( gms30c2116 )
{ {
switch (state) switch (state)
@ -5441,9 +5376,7 @@ CPU_GET_INFO( gms30c2116 )
CPU_GET_INFO_CALL(hyperstone); CPU_GET_INFO_CALL(hyperstone);
} }
} }
#endif
#if (HAS_GMS30C2132)
CPU_GET_INFO( gms30c2132 ) CPU_GET_INFO( gms30c2132 )
{ {
switch (state) switch (state)
@ -5464,9 +5397,7 @@ CPU_GET_INFO( gms30c2132 )
CPU_GET_INFO_CALL(hyperstone); CPU_GET_INFO_CALL(hyperstone);
} }
} }
#endif
#if (HAS_GMS30C2216)
CPU_GET_INFO( gms30c2216 ) CPU_GET_INFO( gms30c2216 )
{ {
switch (state) switch (state)
@ -5487,9 +5418,7 @@ CPU_GET_INFO( gms30c2216 )
CPU_GET_INFO_CALL(hyperstone); CPU_GET_INFO_CALL(hyperstone);
} }
} }
#endif
#if (HAS_GMS30C2232)
CPU_GET_INFO( gms30c2232 ) CPU_GET_INFO( gms30c2232 )
{ {
switch (state) switch (state)
@ -5510,4 +5439,3 @@ CPU_GET_INFO( gms30c2232 )
CPU_GET_INFO_CALL(hyperstone); CPU_GET_INFO_CALL(hyperstone);
} }
} }
#endif

View File

@ -23,75 +23,47 @@
/* Functions */ /* Functions */
#if (HAS_E116T)
CPU_GET_INFO( e116t ); CPU_GET_INFO( e116t );
#define CPU_E116T CPU_GET_INFO_NAME( e116t ) #define CPU_E116T CPU_GET_INFO_NAME( e116t )
#endif
#if (HAS_E116XT)
CPU_GET_INFO( e116xt ); CPU_GET_INFO( e116xt );
#define CPU_E116XT CPU_GET_INFO_NAME( e116xt ) #define CPU_E116XT CPU_GET_INFO_NAME( e116xt )
#endif
#if (HAS_E116XS)
CPU_GET_INFO( e116xs ); CPU_GET_INFO( e116xs );
#define CPU_E116XS CPU_GET_INFO_NAME( e116xs ) #define CPU_E116XS CPU_GET_INFO_NAME( e116xs )
#endif
#if (HAS_E116XSR)
CPU_GET_INFO( e116xsr ); CPU_GET_INFO( e116xsr );
#define CPU_E116XSR CPU_GET_INFO_NAME( e116xsr ) #define CPU_E116XSR CPU_GET_INFO_NAME( e116xsr )
#endif
#if (HAS_E132N)
CPU_GET_INFO( e132n ); CPU_GET_INFO( e132n );
#define CPU_E132N CPU_GET_INFO_NAME( e132n ) #define CPU_E132N CPU_GET_INFO_NAME( e132n )
#endif
#if (HAS_E132T)
CPU_GET_INFO( e132t ); CPU_GET_INFO( e132t );
#define CPU_E132T CPU_GET_INFO_NAME( e132t ) #define CPU_E132T CPU_GET_INFO_NAME( e132t )
#endif
#if (HAS_E132XN)
CPU_GET_INFO( e132xn ); CPU_GET_INFO( e132xn );
#define CPU_E132XN CPU_GET_INFO_NAME( e132xn ) #define CPU_E132XN CPU_GET_INFO_NAME( e132xn )
#endif
#if (HAS_E132XT)
CPU_GET_INFO( e132xt ); CPU_GET_INFO( e132xt );
#define CPU_E132XT CPU_GET_INFO_NAME( e132xt ) #define CPU_E132XT CPU_GET_INFO_NAME( e132xt )
#endif
#if (HAS_E132XS)
CPU_GET_INFO( e132xs ); CPU_GET_INFO( e132xs );
#define CPU_E132XS CPU_GET_INFO_NAME( e132xs ) #define CPU_E132XS CPU_GET_INFO_NAME( e132xs )
#endif
#if (HAS_E132XSR)
CPU_GET_INFO( e132xsr ); CPU_GET_INFO( e132xsr );
#define CPU_E132XSR CPU_GET_INFO_NAME( e132xsr ) #define CPU_E132XSR CPU_GET_INFO_NAME( e132xsr )
#endif
#if (HAS_GMS30C2116)
CPU_GET_INFO( gms30c2116 ); CPU_GET_INFO( gms30c2116 );
#define CPU_GMS30C2116 CPU_GET_INFO_NAME( gms30c2116 ) #define CPU_GMS30C2116 CPU_GET_INFO_NAME( gms30c2116 )
#endif
#if (HAS_GMS30C2132)
CPU_GET_INFO( gms30c2132 ); CPU_GET_INFO( gms30c2132 );
#define CPU_GMS30C2132 CPU_GET_INFO_NAME( gms30c2132 ) #define CPU_GMS30C2132 CPU_GET_INFO_NAME( gms30c2132 )
#endif
#if (HAS_GMS30C2216)
CPU_GET_INFO( gms30c2216 ); CPU_GET_INFO( gms30c2216 );
#define CPU_GMS30C2216 CPU_GET_INFO_NAME( gms30c2216 ) #define CPU_GMS30C2216 CPU_GET_INFO_NAME( gms30c2216 )
#endif
#if (HAS_GMS30C2232)
CPU_GET_INFO( gms30c2232 ); CPU_GET_INFO( gms30c2232 );
#define CPU_GMS30C2232 CPU_GET_INFO_NAME( gms30c2232 ) #define CPU_GMS30C2232 CPU_GET_INFO_NAME( gms30c2232 )
#endif
extern unsigned dasm_hyperstone(char *buffer, unsigned pc, const UINT8 *oprom, unsigned h_flag, int private_fp); extern unsigned dasm_hyperstone(char *buffer, unsigned pc, const UINT8 *oprom, unsigned h_flag, int private_fp);

View File

@ -1062,7 +1062,6 @@ CPU_GET_INFO( i386 )
/*****************************************************************************/ /*****************************************************************************/
/* Intel 486 */ /* Intel 486 */
#if (HAS_I486)
static CPU_INIT( i486 ) static CPU_INIT( i486 )
{ {
@ -1170,12 +1169,10 @@ CPU_GET_INFO( i486 )
default: CPU_GET_INFO_CALL(i386); break; default: CPU_GET_INFO_CALL(i386); break;
} }
} }
#endif
/*****************************************************************************/ /*****************************************************************************/
/* Pentium */ /* Pentium */
#if (HAS_PENTIUM)
static CPU_INIT( pentium ) static CPU_INIT( pentium )
{ {
@ -1303,12 +1300,10 @@ CPU_GET_INFO( pentium )
default: CPU_GET_INFO_CALL(i386); break; default: CPU_GET_INFO_CALL(i386); break;
} }
} }
#endif
/*****************************************************************************/ /*****************************************************************************/
/* Cyrix MediaGX */ /* Cyrix MediaGX */
#if (HAS_MEDIAGX)
static CPU_INIT( mediagx ) static CPU_INIT( mediagx )
{ {
@ -1436,4 +1431,3 @@ CPU_GET_INFO( mediagx )
default: CPU_GET_INFO_CALL(i386); break; default: CPU_GET_INFO_CALL(i386); break;
} }
} }
#endif

View File

@ -226,14 +226,12 @@ static CPU_INIT( i8086 )
configure_memory_16bit(cpustate); configure_memory_16bit(cpustate);
} }
#if (HAS_I8088||HAS_I80188)
static CPU_INIT( i8088 ) static CPU_INIT( i8088 )
{ {
i8086_state *cpustate = get_safe_token(device); i8086_state *cpustate = get_safe_token(device);
CPU_INIT_CALL(i8086); CPU_INIT_CALL(i8086);
configure_memory_8bit(cpustate); configure_memory_8bit(cpustate);
} }
#endif
static CPU_RESET( i8086 ) static CPU_RESET( i8086 )
{ {
@ -334,7 +332,6 @@ static CPU_DISASSEMBLE( i8086 )
} }
#if (HAS_I80186 || HAS_I80188)
#include "i86.h" #include "i86.h"
@ -382,7 +379,6 @@ static CPU_EXECUTE( i80186 )
return cycles - cpustate->icount; return cycles - cpustate->icount;
} }
#endif
@ -593,7 +589,6 @@ CPU_GET_INFO( i8086 )
} }
#if (HAS_I8088)
/************************************************************************** /**************************************************************************
* CPU-specific get_info/set_info * CPU-specific get_info/set_info
**************************************************************************/ **************************************************************************/
@ -615,10 +610,8 @@ CPU_GET_INFO( i8088 )
default: CPU_GET_INFO_CALL(i8086); break; default: CPU_GET_INFO_CALL(i8086); break;
} }
} }
#endif
#if (HAS_I80186)
/************************************************************************** /**************************************************************************
* CPU-specific get_info/set_info * CPU-specific get_info/set_info
**************************************************************************/ **************************************************************************/
@ -640,10 +633,8 @@ CPU_GET_INFO( i80186 )
default: CPU_GET_INFO_CALL(i8086); break; default: CPU_GET_INFO_CALL(i8086); break;
} }
} }
#endif
#if (HAS_I80188)
/************************************************************************** /**************************************************************************
* CPU-specific get_info/set_info * CPU-specific get_info/set_info
**************************************************************************/ **************************************************************************/
@ -666,4 +657,3 @@ CPU_GET_INFO( i80188 )
default: CPU_GET_INFO_CALL(i8086); break; default: CPU_GET_INFO_CALL(i8086); break;
} }
} }
#endif

View File

@ -3,7 +3,6 @@
*****************************************************************************/ *****************************************************************************/
#ifdef I8086 #ifdef I8086
#if (HAS_I8088||HAS_I80188)
static void configure_memory_8bit(i8086_state *cpustate) static void configure_memory_8bit(i8086_state *cpustate)
{ {
cpustate->mem.fetch_xor = 0; cpustate->mem.fetch_xor = 0;
@ -14,7 +13,6 @@ static void configure_memory_8bit(i8086_state *cpustate)
cpustate->mem.wword = memory_write_word_8le; cpustate->mem.wword = memory_write_word_8le;
} }
#endif #endif
#endif
/***************************************************************************** /*****************************************************************************

View File

@ -29,15 +29,9 @@
#include "debugger.h" #include "debugger.h"
#include "m6502.h" #include "m6502.h"
#if (HAS_M65CE02)
#include "m65ce02.h" #include "m65ce02.h"
#endif
#if (HAS_M6509)
#include "m6509.h" #include "m6509.h"
#endif
#if (HAS_M4510)
#include "m4510.h" #include "m4510.h"
#endif
enum addr_mode { enum addr_mode {
non, /* no additional arguments */ non, /* no additional arguments */
@ -341,7 +335,6 @@ static const struct op6502_info op65sc02[256] = {
{ill,non},{sbc,abx},{inc,abx},{bbs,zpb} {ill,non},{sbc,abx},{inc,abx},{bbs,zpb}
}; };
#if (HAS_M65CE02)
static const struct op6502_info op65ce02[256] = { static const struct op6502_info op65ce02[256] = {
{m6502_brk,imm},{ora,idx},{cle,imp},{see,imp},/* 00 */ {m6502_brk,imm},{ora,idx},{cle,imp},{see,imp},/* 00 */
{tsb,zpg},{ora,zpg},{asl,zpg},{rmb,zpg}, {tsb,zpg},{ora,zpg},{asl,zpg},{rmb,zpg},
@ -408,9 +401,7 @@ static const struct op6502_info op65ce02[256] = {
{sed,imp},{sbc,aby},{plx,imp},{plz,imp}, {sed,imp},{sbc,aby},{plx,imp},{plz,imp},
{phw,aba},{sbc,abx},{inc,abx},{bbs,zpb} {phw,aba},{sbc,abx},{inc,abx},{bbs,zpb}
}; };
#endif
#if (HAS_M4510)
// only map instead of aug and 20 bit memory management // only map instead of aug and 20 bit memory management
static const struct op6502_info op4510[256] = { static const struct op6502_info op4510[256] = {
{m6502_brk,imm},{ora,idx},{cle,imp},{see,imp},/* 00 */ {m6502_brk,imm},{ora,idx},{cle,imp},{see,imp},/* 00 */
@ -478,9 +469,7 @@ static const struct op6502_info op4510[256] = {
{sed,imp},{sbc,aby},{plx,imp},{plz,imp}, {sed,imp},{sbc,aby},{plx,imp},{plz,imp},
{phw,aba},{sbc,abx},{inc,abx},{bbs,zpb} {phw,aba},{sbc,abx},{inc,abx},{bbs,zpb}
}; };
#endif
#if (HAS_DECO16)
static const struct op6502_info opdeco16[256] = static const struct op6502_info opdeco16[256] =
{ {
{m6502_brk,imp},{ora,idx},{ill,non},{ill,non},/* 00 */ {m6502_brk,imp},{ora,idx},{ill,non},{ill,non},/* 00 */
@ -548,7 +537,6 @@ static const struct op6502_info opdeco16[256] =
{sed,imp},{sbc,aby},{ill,non},{ill,non}, {sed,imp},{sbc,aby},{ill,non},{ill,non},
{ill,non},{sbc,abx},{inc,abx},{ill,non} {ill,non},{sbc,abx},{inc,abx},{ill,non}
}; };
#endif
/***************************************************************************** /*****************************************************************************
* Disassemble a single opcode starting at pc * Disassemble a single opcode starting at pc
@ -747,44 +735,32 @@ CPU_DISASSEMBLE( m6502 )
return internal_m6502_dasm(op6502, buffer, pc, oprom, opram); return internal_m6502_dasm(op6502, buffer, pc, oprom, opram);
} }
#if (HAS_M65SC02)
CPU_DISASSEMBLE( m65sc02 ) CPU_DISASSEMBLE( m65sc02 )
{ {
return internal_m6502_dasm(op65sc02, buffer, pc, oprom, opram); return internal_m6502_dasm(op65sc02, buffer, pc, oprom, opram);
} }
#endif
#if (HAS_M65C02||HAS_M65SC02||HAS_DECO16)
CPU_DISASSEMBLE( m65c02 ) CPU_DISASSEMBLE( m65c02 )
{ {
return internal_m6502_dasm(op65c02, buffer, pc, oprom, opram); return internal_m6502_dasm(op65c02, buffer, pc, oprom, opram);
} }
#endif
#if (HAS_M65CE02)
CPU_DISASSEMBLE( m65ce02 ) CPU_DISASSEMBLE( m65ce02 )
{ {
return internal_m6502_dasm(op65ce02, buffer, pc, oprom, opram); return internal_m6502_dasm(op65ce02, buffer, pc, oprom, opram);
} }
#endif
#if (HAS_M6510)
CPU_DISASSEMBLE( m6510 ) CPU_DISASSEMBLE( m6510 )
{ {
return internal_m6502_dasm(op6502, buffer, pc, oprom, opram); return internal_m6502_dasm(op6502, buffer, pc, oprom, opram);
} }
#endif
#if (HAS_DECO16)
CPU_DISASSEMBLE( deco16 ) CPU_DISASSEMBLE( deco16 )
{ {
return internal_m6502_dasm(opdeco16, buffer, pc, oprom, opram); return internal_m6502_dasm(opdeco16, buffer, pc, oprom, opram);
} }
#endif
#if (HAS_M4510)
CPU_DISASSEMBLE( m4510 ) CPU_DISASSEMBLE( m4510 )
{ {
return internal_m6502_dasm(op4510, buffer, pc, oprom, opram); return internal_m6502_dasm(op4510, buffer, pc, oprom, opram);
} }
#endif

View File

@ -24,11 +24,6 @@
/* 10.March 2000 PeT added 6502 set overflow input line */ /* 10.March 2000 PeT added 6502 set overflow input line */
/* 13.September 2000 PeT N2A03 jmp indirect */ /* 13.September 2000 PeT N2A03 jmp indirect */
#if ((HAS_M65SC02 || HAS_DECO16) && !HAS_M65C02)
#undef HAS_M65C02
#define HAS_M65C02 1
#endif
#include "debugger.h" #include "debugger.h"
#include "m6502.h" #include "m6502.h"
#include "ops02.h" #include "ops02.h"
@ -82,13 +77,10 @@ struct _m6502_Regs
m6502_read_indexed_func rdmem_id; /* readmem callback for indexed instructions */ m6502_read_indexed_func rdmem_id; /* readmem callback for indexed instructions */
m6502_write_indexed_func wrmem_id; /* writemem callback for indexed instructions */ m6502_write_indexed_func wrmem_id; /* writemem callback for indexed instructions */
#if (HAS_M6510) || (HAS_M6510T) || (HAS_M8502) || (HAS_M7501)
UINT8 ddr; UINT8 ddr;
UINT8 port; UINT8 port;
m6510_port_read_func port_read; m6510_port_read_func port_read;
m6510_port_write_func port_write; m6510_port_write_func port_write;
#endif
}; };
INLINE m6502_Regs *get_safe_token(const device_config *device) INLINE m6502_Regs *get_safe_token(const device_config *device)
@ -116,29 +108,19 @@ static void default_wdmem_id(const address_space *space, offs_t offset, UINT8 da
***************************************************************/ ***************************************************************/
#include "t6502.c" #include "t6502.c"
#if (HAS_M6510)
#include "t6510.c" #include "t6510.c"
#endif
#include "opsn2a03.h" #include "opsn2a03.h"
#if (HAS_N2A03)
#include "tn2a03.c" #include "tn2a03.c"
#endif
#include "opsc02.h" #include "opsc02.h"
#if (HAS_M65C02)
#include "t65c02.c" #include "t65c02.c"
#endif
#if (HAS_M65SC02)
#include "t65sc02.c" #include "t65sc02.c"
#endif
#if (HAS_DECO16)
#include "tdeco16.c" #include "tdeco16.c"
#endif
/***************************************************************************** /*****************************************************************************
* *
@ -170,13 +152,11 @@ static void m6502_common_init(const device_config *device, cpu_irq_callback irqc
state_save_register_device_item(device, 0, cpustate->irq_state); state_save_register_device_item(device, 0, cpustate->irq_state);
state_save_register_device_item(device, 0, cpustate->so_state); state_save_register_device_item(device, 0, cpustate->so_state);
#if (HAS_M6510) || (HAS_M6510T) || (HAS_M8502) || (HAS_M7501)
if (subtype == SUBTYPE_6510) if (subtype == SUBTYPE_6510)
{ {
state_save_register_device_item(device, 0, cpustate->port); state_save_register_device_item(device, 0, cpustate->port);
state_save_register_device_item(device, 0, cpustate->ddr); state_save_register_device_item(device, 0, cpustate->ddr);
} }
#endif
} }
static CPU_INIT( m6502 ) static CPU_INIT( m6502 )
@ -325,7 +305,6 @@ static void m6502_set_irq_line(m6502_Regs *cpustate, int irqline, int state)
/**************************************************************************** /****************************************************************************
* 2A03 section * 2A03 section
****************************************************************************/ ****************************************************************************/
#if (HAS_N2A03)
static CPU_INIT( n2a03 ) static CPU_INIT( n2a03 )
{ {
@ -342,13 +321,11 @@ void n2a03_irq(const device_config *device)
m6502_take_irq(cpustate); m6502_take_irq(cpustate);
} }
#endif
/**************************************************************************** /****************************************************************************
* 6510 section * 6510 section
****************************************************************************/ ****************************************************************************/
#if (HAS_M6510)
static CPU_INIT( m6510 ) static CPU_INIT( m6510 )
{ {
@ -410,13 +387,11 @@ static ADDRESS_MAP_START(m6510_mem, ADDRESS_SPACE_PROGRAM, 8)
AM_RANGE(0x0000, 0x0001) AM_READWRITE(m6510_read_0000, m6510_write_0000) AM_RANGE(0x0000, 0x0001) AM_READWRITE(m6510_read_0000, m6510_write_0000)
ADDRESS_MAP_END ADDRESS_MAP_END
#endif
/**************************************************************************** /****************************************************************************
* 65C02 section * 65C02 section
****************************************************************************/ ****************************************************************************/
#if (HAS_M65C02)
static CPU_INIT( m65c02 ) static CPU_INIT( m65c02 )
{ {
@ -518,22 +493,18 @@ static void m65c02_set_irq_line(m6502_Regs *cpustate, int irqline, int state)
else else
m6502_set_irq_line(cpustate, irqline,state); m6502_set_irq_line(cpustate, irqline,state);
} }
#endif
/**************************************************************************** /****************************************************************************
* 65SC02 section * 65SC02 section
****************************************************************************/ ****************************************************************************/
#if (HAS_M65SC02)
static CPU_INIT( m65sc02 ) static CPU_INIT( m65sc02 )
{ {
m6502_common_init(device, irqcallback, SUBTYPE_65SC02, insn65sc02, "m65sc02"); m6502_common_init(device, irqcallback, SUBTYPE_65SC02, insn65sc02, "m65sc02");
} }
#endif
/**************************************************************************** /****************************************************************************
* DECO16 section * DECO16 section
****************************************************************************/ ****************************************************************************/
#if (HAS_DECO16)
static CPU_INIT( deco16 ) static CPU_INIT( deco16 )
{ {
@ -665,7 +636,6 @@ static CPU_EXECUTE( deco16 )
return cycles - cpustate->icount; return cycles - cpustate->icount;
} }
#endif
@ -796,7 +766,6 @@ CPU_GET_INFO( m6502 )
} }
#if (HAS_N2A03)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -814,10 +783,8 @@ CPU_GET_INFO( n2a03 )
default: CPU_GET_INFO_CALL(m6502); break; default: CPU_GET_INFO_CALL(m6502); break;
} }
} }
#endif
#if (HAS_M6510) || (HAS_M6510T) || (HAS_M8502) || (HAS_M7501)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -860,10 +827,8 @@ CPU_GET_INFO( m6510 )
default: CPU_GET_INFO_CALL(m6502); break; default: CPU_GET_INFO_CALL(m6502); break;
} }
} }
#endif
#if (HAS_M6510T)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -878,10 +843,8 @@ CPU_GET_INFO( m6510t )
default: CPU_GET_INFO_CALL(m6510); break; default: CPU_GET_INFO_CALL(m6510); break;
} }
} }
#endif
#if (HAS_M7501)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -896,10 +859,8 @@ CPU_GET_INFO( m7501 )
default: CPU_GET_INFO_CALL(m6510); break; default: CPU_GET_INFO_CALL(m6510); break;
} }
} }
#endif
#if (HAS_M8502)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -914,10 +875,8 @@ CPU_GET_INFO( m8502 )
default: CPU_GET_INFO_CALL(m6510); break; default: CPU_GET_INFO_CALL(m6510); break;
} }
} }
#endif
#if (HAS_M65C02)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -952,10 +911,8 @@ CPU_GET_INFO( m65c02 )
default: CPU_GET_INFO_CALL(m6502); break; default: CPU_GET_INFO_CALL(m6502); break;
} }
} }
#endif
#if (HAS_M65SC02)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -978,10 +935,8 @@ CPU_GET_INFO( m65sc02 )
default: CPU_GET_INFO_CALL(m65c02); break; default: CPU_GET_INFO_CALL(m65c02); break;
} }
} }
#endif
#if (HAS_DECO16)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -1026,4 +981,3 @@ CPU_GET_INFO( deco16 )
default: CPU_GET_INFO_CALL(m6502); break; default: CPU_GET_INFO_CALL(m6502); break;
} }
} }
#endif

View File

@ -33,21 +33,11 @@
#define FAST_MEMORY 0 #define FAST_MEMORY 0
#define SUBTYPE_6502 0 #define SUBTYPE_6502 0
#if (HAS_M65C02)
#define SUBTYPE_65C02 1 #define SUBTYPE_65C02 1
#endif
#if (HAS_M6510)
#define SUBTYPE_6510 2 #define SUBTYPE_6510 2
#endif
#if (HAS_N2A03)
#define SUBTYPE_2A03 3 #define SUBTYPE_2A03 3
#endif
#if (HAS_M65SC02)
#define SUBTYPE_65SC02 4 #define SUBTYPE_65SC02 4
#endif
#if (HAS_DECO16)
#define SUBTYPE_DECO16 5 #define SUBTYPE_DECO16 5
#endif
enum enum
{ {
@ -86,7 +76,6 @@ extern CPU_DISASSEMBLE( m6502 );
/**************************************************************************** /****************************************************************************
* The 6510 * The 6510
****************************************************************************/ ****************************************************************************/
#if (HAS_M6510)
#define M6510_A M6502_A #define M6510_A M6502_A
#define M6510_X M6502_X #define M6510_X M6502_X
#define M6510_Y M6502_Y #define M6510_Y M6502_Y
@ -105,9 +94,7 @@ extern CPU_GET_INFO( m6510 );
extern CPU_DISASSEMBLE( m6510 ); extern CPU_DISASSEMBLE( m6510 );
#endif
#if (HAS_M6510T)
#define M6510T_A M6502_A #define M6510T_A M6502_A
#define M6510T_X M6502_X #define M6510T_X M6502_X
#define M6510T_Y M6502_Y #define M6510T_Y M6502_Y
@ -124,9 +111,7 @@ extern CPU_DISASSEMBLE( m6510 );
extern CPU_GET_INFO( m6510t ); extern CPU_GET_INFO( m6510t );
#define CPU_M6510T CPU_GET_INFO_NAME( m6510t ) #define CPU_M6510T CPU_GET_INFO_NAME( m6510t )
#endif
#if (HAS_M7501)
#define M7501_A M6502_A #define M7501_A M6502_A
#define M7501_X M6502_X #define M7501_X M6502_X
#define M7501_Y M6502_Y #define M7501_Y M6502_Y
@ -142,9 +127,7 @@ extern CPU_GET_INFO( m6510t );
extern CPU_GET_INFO( m7501 ); extern CPU_GET_INFO( m7501 );
#define CPU_M7501 CPU_GET_INFO_NAME( m7501 ) #define CPU_M7501 CPU_GET_INFO_NAME( m7501 )
#endif
#if (HAS_M8502)
#define M8502_A M6502_A #define M8502_A M6502_A
#define M8502_X M6502_X #define M8502_X M6502_X
#define M8502_Y M6502_Y #define M8502_Y M6502_Y
@ -160,13 +143,11 @@ extern CPU_GET_INFO( m7501 );
extern CPU_GET_INFO( m8502 ); extern CPU_GET_INFO( m8502 );
#define CPU_M8502 CPU_GET_INFO_NAME( m8502 ) #define CPU_M8502 CPU_GET_INFO_NAME( m8502 )
#endif
/**************************************************************************** /****************************************************************************
* The 2A03 (NES 6502 without decimal mode ADC/SBC) * The 2A03 (NES 6502 without decimal mode ADC/SBC)
****************************************************************************/ ****************************************************************************/
#if (HAS_N2A03)
#define N2A03_A M6502_A #define N2A03_A M6502_A
#define N2A03_X M6502_X #define N2A03_X M6502_X
#define N2A03_Y M6502_Y #define N2A03_Y M6502_Y
@ -190,13 +171,11 @@ extern CPU_GET_INFO( n2a03 );
causes an IRQ to be generated. This function allows the IRQ to be called causes an IRQ to be generated. This function allows the IRQ to be called
from the PSG core when such an occasion arises. */ from the PSG core when such an occasion arises. */
extern void n2a03_irq(const device_config *device); extern void n2a03_irq(const device_config *device);
#endif
/**************************************************************************** /****************************************************************************
* The 65C02 * The 65C02
****************************************************************************/ ****************************************************************************/
#if (HAS_M65C02)
#define M65C02_A M6502_A #define M65C02_A M6502_A
#define M65C02_X M6502_X #define M65C02_X M6502_X
#define M65C02_Y M6502_Y #define M65C02_Y M6502_Y
@ -215,12 +194,10 @@ extern CPU_GET_INFO( m65c02 );
extern CPU_DISASSEMBLE( m65c02 ); extern CPU_DISASSEMBLE( m65c02 );
#endif
/**************************************************************************** /****************************************************************************
* The 65SC02 * The 65SC02
****************************************************************************/ ****************************************************************************/
#if (HAS_M65SC02)
#define M65SC02_A M6502_A #define M65SC02_A M6502_A
#define M65SC02_X M6502_X #define M65SC02_X M6502_X
#define M65SC02_Y M6502_Y #define M65SC02_Y M6502_Y
@ -238,12 +215,10 @@ extern CPU_GET_INFO( m65sc02 );
#define CPU_M65SC02 CPU_GET_INFO_NAME( m65sc02 ) #define CPU_M65SC02 CPU_GET_INFO_NAME( m65sc02 )
extern CPU_DISASSEMBLE( m65sc02 ); extern CPU_DISASSEMBLE( m65sc02 );
#endif
/**************************************************************************** /****************************************************************************
* The DECO CPU16 * The DECO CPU16
****************************************************************************/ ****************************************************************************/
#if (HAS_DECO16)
#define DECO16_A M6502_A #define DECO16_A M6502_A
#define DECO16_X M6502_X #define DECO16_X M6502_X
#define DECO16_Y M6502_Y #define DECO16_Y M6502_Y
@ -259,7 +234,6 @@ extern CPU_DISASSEMBLE( m65sc02 );
extern CPU_GET_INFO( deco16 ); extern CPU_GET_INFO( deco16 );
#define CPU_DECO16 CPU_GET_INFO_NAME( deco16 ) #define CPU_DECO16 CPU_GET_INFO_NAME( deco16 )
#endif
extern CPU_DISASSEMBLE( deco16 ); extern CPU_DISASSEMBLE( deco16 );

View File

@ -22,14 +22,12 @@ OP_HANDLER( illegal )
} }
/* HD63701 only */ /* HD63701 only */
#if (HAS_HD63701)
//OP_HANDLER( trap ) //OP_HANDLER( trap )
OP_HANDLER( trap ) OP_HANDLER( trap )
{ {
logerror("m6800: illegal opcode: address %04X, op %02X\n",PC,(int) M_RDOP_ARG(PC)&0xFF); logerror("m6800: illegal opcode: address %04X, op %02X\n",PC,(int) M_RDOP_ARG(PC)&0xFF);
TAKE_TRAP; TAKE_TRAP;
} }
#endif
/* $00 ILLEGAL */ /* $00 ILLEGAL */
@ -201,7 +199,6 @@ OP_HANDLER( daa )
/* $1a ILLEGAL */ /* $1a ILLEGAL */
#if (HAS_HD63701)
/* $1a SLP */ /* HD63701YO only */ /* $1a SLP */ /* HD63701YO only */
OP_HANDLER( slp ) OP_HANDLER( slp )
{ {
@ -209,7 +206,6 @@ OP_HANDLER( slp )
cpustate->wai_state |= M6800_SLP; cpustate->wai_state |= M6800_SLP;
EAT_CYCLES; EAT_CYCLES;
} }
#endif
/* $1b ABA inherent ***** */ /* $1b ABA inherent ***** */
OP_HANDLER( aba ) OP_HANDLER( aba )

View File

@ -188,9 +188,7 @@ INLINE void sbcb_ix(m6800_state *cpustate);
INLINE void sec(m6800_state *cpustate); INLINE void sec(m6800_state *cpustate);
INLINE void sei(m6800_state *cpustate); INLINE void sei(m6800_state *cpustate);
INLINE void sev(m6800_state *cpustate); INLINE void sev(m6800_state *cpustate);
#if (HAS_HD63701)
INLINE void slp(m6800_state *cpustate); INLINE void slp(m6800_state *cpustate);
#endif
INLINE void sta_di(m6800_state *cpustate); INLINE void sta_di(m6800_state *cpustate);
INLINE void sta_ex(m6800_state *cpustate); INLINE void sta_ex(m6800_state *cpustate);
INLINE void sta_im(m6800_state *cpustate); INLINE void sta_im(m6800_state *cpustate);
@ -245,9 +243,7 @@ INLINE void cpx_di(m6800_state *cpustate);
INLINE void cpx_ex(m6800_state *cpustate); INLINE void cpx_ex(m6800_state *cpustate);
INLINE void cpx_im(m6800_state *cpustate); INLINE void cpx_im(m6800_state *cpustate);
INLINE void cpx_ix(m6800_state *cpustate); INLINE void cpx_ix(m6800_state *cpustate);
#if (HAS_HD63701)
INLINE void trap(m6800_state *cpustate); INLINE void trap(m6800_state *cpustate);
#endif
static void (*const m6800_insn[0x100])(m6800_state *cpustate) = { static void (*const m6800_insn[0x100])(m6800_state *cpustate) = {
illegal,nop, illegal,illegal,illegal,illegal,tap, tpa, illegal,nop, illegal,illegal,illegal,illegal,tap, tpa,
@ -284,7 +280,6 @@ subb_ex,cmpb_ex,sbcb_ex,illegal,andb_ex,bitb_ex,ldb_ex, stb_ex,
eorb_ex,adcb_ex,orb_ex, addb_ex,illegal,illegal,ldx_ex, stx_ex eorb_ex,adcb_ex,orb_ex, addb_ex,illegal,illegal,ldx_ex, stx_ex
}; };
#if (HAS_M6801||HAS_M6803)
static void (*const m6803_insn[0x100])(m6800_state *cpustate) = { static void (*const m6803_insn[0x100])(m6800_state *cpustate) = {
illegal,nop, illegal,illegal,lsrd, asld, tap, tpa, illegal,nop, illegal,illegal,lsrd, asld, tap, tpa,
inx, dex, clv, sev, clc, sec, cli, sei, inx, dex, clv, sev, clc, sec, cli, sei,
@ -319,9 +314,7 @@ eorb_ix,adcb_ix,orb_ix, addb_ix,ldd_ix, std_ix, ldx_ix, stx_ix,
subb_ex,cmpb_ex,sbcb_ex,addd_ex,andb_ex,bitb_ex,ldb_ex, stb_ex, subb_ex,cmpb_ex,sbcb_ex,addd_ex,andb_ex,bitb_ex,ldb_ex, stb_ex,
eorb_ex,adcb_ex,orb_ex, addb_ex,ldd_ex, std_ex, ldx_ex, stx_ex eorb_ex,adcb_ex,orb_ex, addb_ex,ldd_ex, std_ex, ldx_ex, stx_ex
}; };
#endif
#if (HAS_HD63701)
static void (*const hd63701_insn[0x100])(m6800_state *cpustate) = { static void (*const hd63701_insn[0x100])(m6800_state *cpustate) = {
trap ,nop, trap ,trap ,lsrd, asld, tap, tpa, trap ,nop, trap ,trap ,lsrd, asld, tap, tpa,
inx, dex, clv, sev, clc, sec, cli, sei, inx, dex, clv, sev, clc, sec, cli, sei,
@ -356,9 +349,7 @@ eorb_ix,adcb_ix,orb_ix, addb_ix,ldd_ix, std_ix, ldx_ix, stx_ix,
subb_ex,cmpb_ex,sbcb_ex,addd_ex,andb_ex,bitb_ex,ldb_ex, stb_ex, subb_ex,cmpb_ex,sbcb_ex,addd_ex,andb_ex,bitb_ex,ldb_ex, stb_ex,
eorb_ex,adcb_ex,orb_ex, addb_ex,ldd_ex, std_ex, ldx_ex, stx_ex eorb_ex,adcb_ex,orb_ex, addb_ex,ldd_ex, std_ex, ldx_ex, stx_ex
}; };
#endif
#if (HAS_NSC8105)
static void (*const nsc8105_insn[0x100])(m6800_state *cpustate) = { static void (*const nsc8105_insn[0x100])(m6800_state *cpustate) = {
illegal,illegal,nop, illegal,illegal,tap, illegal,tpa, illegal,illegal,nop, illegal,illegal,tap, illegal,tpa,
inx, clv, dex, sev, clc, cli, sec, sei, inx, clv, dex, sev, clc, cli, sec, sei,
@ -393,4 +384,3 @@ eorb_ix,orb_ix, adcb_ix,addb_ix,adcx_im,ldx_ix, illegal,stx_ix,
subb_ex,sbcb_ex,cmpb_ex,illegal,andb_ex,ldb_ex, bitb_ex,stb_ex, subb_ex,sbcb_ex,cmpb_ex,illegal,andb_ex,ldb_ex, bitb_ex,stb_ex,
eorb_ex,orb_ex, adcb_ex,addb_ex,addx_ex,ldx_ex, illegal,stx_ex eorb_ex,orb_ex, adcb_ex,addb_ex,addx_ex,ldx_ex, illegal,stx_ex
}; };
#endif

View File

@ -657,7 +657,6 @@ INLINE void increment_counter(m6800_state *cpustate, int amount)
/* include the opcode functions */ /* include the opcode functions */
#include "6800ops.c" #include "6800ops.c"
#if (HAS_M6801||HAS_M6803||HAS_HD63701)
static void m6800_tx(m6800_state *cpustate, int value) static void m6800_tx(m6800_state *cpustate, int value)
{ {
cpustate->port2_data = (cpustate->port2_data & 0xef) | (value << 4); cpustate->port2_data = (cpustate->port2_data & 0xef) | (value << 4);
@ -844,7 +843,6 @@ static TIMER_CALLBACK(m6800_rx_tick)
} }
} }
} }
#endif
/**************************************************************************** /****************************************************************************
* Reset registers to their initial values * Reset registers to their initial values
@ -1286,7 +1284,6 @@ static CPU_EXECUTE( m6800 )
/**************************************************************************** /****************************************************************************
* M6801 almost (fully?) equal to the M6803 * M6801 almost (fully?) equal to the M6803
****************************************************************************/ ****************************************************************************/
#if (HAS_M6801)
static CPU_INIT( m6801 ) static CPU_INIT( m6801 )
{ {
m6800_state *cpustate = get_safe_token(device); m6800_state *cpustate = get_safe_token(device);
@ -1306,12 +1303,10 @@ static CPU_INIT( m6801 )
state_register(cpustate, "m6801"); state_register(cpustate, "m6801");
} }
#endif
/**************************************************************************** /****************************************************************************
* M6802 almost (fully?) equal to the M6800 * M6802 almost (fully?) equal to the M6800
****************************************************************************/ ****************************************************************************/
#if (HAS_M6802)
static CPU_INIT( m6802 ) static CPU_INIT( m6802 )
{ {
m6800_state *cpustate = get_safe_token(device); m6800_state *cpustate = get_safe_token(device);
@ -1327,12 +1322,10 @@ static CPU_INIT( m6802 )
state_register(cpustate, "m6802"); state_register(cpustate, "m6802");
} }
#endif
/**************************************************************************** /****************************************************************************
* M6803 almost (fully?) equal to the M6801 * M6803 almost (fully?) equal to the M6801
****************************************************************************/ ****************************************************************************/
#if (HAS_M6803)
static CPU_INIT( m6803 ) static CPU_INIT( m6803 )
{ {
m6800_state *cpustate = get_safe_token(device); m6800_state *cpustate = get_safe_token(device);
@ -1352,7 +1345,6 @@ static CPU_INIT( m6803 )
state_register(cpustate, "m6803"); state_register(cpustate, "m6803");
} }
#endif
/**************************************************************************** /****************************************************************************
* Execute one instruction * Execute one instruction
@ -1624,7 +1616,6 @@ INLINE void m6803_execute_one(m6800_state *cpustate, UINT8 ireg)
/**************************************************************************** /****************************************************************************
* Execute cycles CPU cycles. Return number of cycles really executed * Execute cycles CPU cycles. Return number of cycles really executed
****************************************************************************/ ****************************************************************************/
#if (HAS_M6803||HAS_M6801)
static CPU_EXECUTE( m6803 ) static CPU_EXECUTE( m6803 )
{ {
m6800_state *cpustate = get_safe_token(device); m6800_state *cpustate = get_safe_token(device);
@ -1654,9 +1645,7 @@ static CPU_EXECUTE( m6803 )
return cycles - cpustate->icount; return cycles - cpustate->icount;
} }
#endif
#if (HAS_M6803)
static READ8_HANDLER( m6803_internal_registers_r ); static READ8_HANDLER( m6803_internal_registers_r );
static WRITE8_HANDLER( m6803_internal_registers_w ); static WRITE8_HANDLER( m6803_internal_registers_w );
@ -1667,12 +1656,10 @@ static ADDRESS_MAP_START(m6803_mem, ADDRESS_SPACE_PROGRAM, 8)
AM_RANGE(0x0080, 0x00ff) AM_RAM /* 6803 internal RAM */ AM_RANGE(0x0080, 0x00ff) AM_RAM /* 6803 internal RAM */
ADDRESS_MAP_END ADDRESS_MAP_END
#endif
/**************************************************************************** /****************************************************************************
* M6808 almost (fully?) equal to the M6800 * M6808 almost (fully?) equal to the M6800
****************************************************************************/ ****************************************************************************/
#if (HAS_M6808)
static CPU_INIT( m6808 ) static CPU_INIT( m6808 )
{ {
m6800_state *cpustate = get_safe_token(device); m6800_state *cpustate = get_safe_token(device);
@ -1688,12 +1675,10 @@ static CPU_INIT( m6808 )
state_register(cpustate, "m6808"); state_register(cpustate, "m6808");
} }
#endif
/**************************************************************************** /****************************************************************************
* HD63701 similiar to the M6800 * HD63701 similiar to the M6800
****************************************************************************/ ****************************************************************************/
#if (HAS_HD63701)
static CPU_INIT( hd63701 ) static CPU_INIT( hd63701 )
{ {
@ -2041,13 +2026,11 @@ WRITE8_HANDLER( hd63701_internal_registers_w )
{ {
m6803_internal_registers_w(space, offset,data); m6803_internal_registers_w(space, offset,data);
} }
#endif
/**************************************************************************** /****************************************************************************
* NSC-8105 similiar to the M6800, but the opcodes are scrambled and there * NSC-8105 similiar to the M6800, but the opcodes are scrambled and there
* is at least one new opcode ($fc) * is at least one new opcode ($fc)
****************************************************************************/ ****************************************************************************/
#if (HAS_NSC8105)
static CPU_INIT( nsc8105 ) static CPU_INIT( nsc8105 )
{ {
m6800_state *cpustate = get_safe_token(device); m6800_state *cpustate = get_safe_token(device);
@ -2362,10 +2345,8 @@ static CPU_EXECUTE( nsc8105 )
return cycles - cpustate->icount; return cycles - cpustate->icount;
} }
#endif
#if (HAS_M6803||HAS_HD63701)
static READ8_HANDLER( m6803_internal_registers_r ) static READ8_HANDLER( m6803_internal_registers_r )
{ {
@ -2654,7 +2635,6 @@ static WRITE8_HANDLER( m6803_internal_registers_w )
break; break;
} }
} }
#endif
/************************************************************************** /**************************************************************************
@ -2772,7 +2752,6 @@ CPU_GET_INFO( m6800 )
} }
#if (HAS_M6801)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -2797,10 +2776,8 @@ CPU_GET_INFO( m6801 )
default: CPU_GET_INFO_CALL(m6800); break; default: CPU_GET_INFO_CALL(m6800); break;
} }
} }
#endif
#if (HAS_M6802)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -2822,10 +2799,8 @@ CPU_GET_INFO( m6802 )
default: CPU_GET_INFO_CALL(m6800); break; default: CPU_GET_INFO_CALL(m6800); break;
} }
} }
#endif
#if (HAS_M6803)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -2852,10 +2827,8 @@ CPU_GET_INFO( m6803 )
default: CPU_GET_INFO_CALL(m6800); break; default: CPU_GET_INFO_CALL(m6800); break;
} }
} }
#endif
#if (HAS_M6808)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -2877,10 +2850,8 @@ CPU_GET_INFO( m6808 )
default: CPU_GET_INFO_CALL(m6800); break; default: CPU_GET_INFO_CALL(m6800); break;
} }
} }
#endif
#if (HAS_HD63701)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -2905,10 +2876,8 @@ CPU_GET_INFO( hd63701 )
default: CPU_GET_INFO_CALL(m6800); break; default: CPU_GET_INFO_CALL(m6800); break;
} }
} }
#endif
#if (HAS_NSC8105)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -2931,4 +2900,3 @@ CPU_GET_INFO( nsc8105 )
default: CPU_GET_INFO_CALL(m6800); break; default: CPU_GET_INFO_CALL(m6800); break;
} }
} }
#endif

View File

@ -23,7 +23,6 @@ enum
/* it is usuali to use PULSE_LINE state */ /* it is usuali to use PULSE_LINE state */
}; };
#if (HAS_M6801||HAS_M6803||HAS_HD63701)
/* By default, on a port write port bits which are not set as output in the DDR */ /* By default, on a port write port bits which are not set as output in the DDR */
/* are set to the value returned by a read from the same port. If you need to */ /* are set to the value returned by a read from the same port. If you need to */
/* know the DDR for e.g. port 1, do m6803_internal_registers_r(M6801_DDR1) */ /* know the DDR for e.g. port 1, do m6803_internal_registers_r(M6801_DDR1) */
@ -43,32 +42,22 @@ enum
M6803_PORT3, M6803_PORT3,
M6803_PORT4 M6803_PORT4
}; };
#endif
CPU_GET_INFO( m6800 ); CPU_GET_INFO( m6800 );
#define CPU_M6800 CPU_GET_INFO_NAME( m6800 ) #define CPU_M6800 CPU_GET_INFO_NAME( m6800 )
#if (HAS_M6801)
CPU_GET_INFO( m6801 ); CPU_GET_INFO( m6801 );
#define CPU_M6801 CPU_GET_INFO_NAME( m6801 ) #define CPU_M6801 CPU_GET_INFO_NAME( m6801 )
#endif
#if (HAS_M6802)
CPU_GET_INFO( m6802 ); CPU_GET_INFO( m6802 );
#define CPU_M6802 CPU_GET_INFO_NAME( m6802 ) #define CPU_M6802 CPU_GET_INFO_NAME( m6802 )
#endif
#if (HAS_M6803)
CPU_GET_INFO( m6803 ); CPU_GET_INFO( m6803 );
#define CPU_M6803 CPU_GET_INFO_NAME( m6803 ) #define CPU_M6803 CPU_GET_INFO_NAME( m6803 )
#endif
#if (HAS_M6808)
CPU_GET_INFO( m6808 ); CPU_GET_INFO( m6808 );
#define CPU_M6808 CPU_GET_INFO_NAME( m6808 ) #define CPU_M6808 CPU_GET_INFO_NAME( m6808 )
#endif
#if (HAS_HD63701)
CPU_GET_INFO( hd63701 ); CPU_GET_INFO( hd63701 );
#define CPU_HD63701 CPU_GET_INFO_NAME( hd63701 ) #define CPU_HD63701 CPU_GET_INFO_NAME( hd63701 )
@ -86,12 +75,9 @@ CPU_GET_INFO( hd63701 );
READ8_HANDLER( hd63701_internal_registers_r ); READ8_HANDLER( hd63701_internal_registers_r );
WRITE8_HANDLER( hd63701_internal_registers_w ); WRITE8_HANDLER( hd63701_internal_registers_w );
#endif
#if (HAS_NSC8105)
CPU_GET_INFO( nsc8105 ); CPU_GET_INFO( nsc8105 );
#define CPU_NSC8105 CPU_GET_INFO_NAME( nsc8105 ) #define CPU_NSC8105 CPU_GET_INFO_NAME( nsc8105 )
#endif
CPU_DISASSEMBLE( m6800 ); CPU_DISASSEMBLE( m6800 );
@ -108,7 +94,6 @@ CPU_DISASSEMBLE( nsc8105 );
/**************************************************************************** /****************************************************************************
* For now make the 6801 using the m6800 variables and functions * For now make the 6801 using the m6800 variables and functions
****************************************************************************/ ****************************************************************************/
#if (HAS_M6801)
#define M6801_A M6800_A #define M6801_A M6800_A
#define M6801_B M6800_B #define M6801_B M6800_B
#define M6801_PC M6800_PC #define M6801_PC M6800_PC
@ -123,12 +108,10 @@ CPU_DISASSEMBLE( nsc8105 );
#define M6801_IRQ_LINE M6800_IRQ_LINE #define M6801_IRQ_LINE M6800_IRQ_LINE
extern CPU_GET_INFO( m6801 ); extern CPU_GET_INFO( m6801 );
#endif
/**************************************************************************** /****************************************************************************
* For now make the 6802 using the m6800 variables and functions * For now make the 6802 using the m6800 variables and functions
****************************************************************************/ ****************************************************************************/
#if (HAS_M6802)
#define M6802_A M6800_A #define M6802_A M6800_A
#define M6802_B M6800_B #define M6802_B M6800_B
#define M6802_PC M6800_PC #define M6802_PC M6800_PC
@ -143,12 +126,10 @@ extern CPU_GET_INFO( m6801 );
#define M6802_IRQ_LINE M6800_IRQ_LINE #define M6802_IRQ_LINE M6800_IRQ_LINE
extern CPU_GET_INFO( m6802 ); extern CPU_GET_INFO( m6802 );
#endif
/**************************************************************************** /****************************************************************************
* For now make the 6803 using the m6800 variables and functions * For now make the 6803 using the m6800 variables and functions
****************************************************************************/ ****************************************************************************/
#if (HAS_M6803)
#define M6803_A M6800_A #define M6803_A M6800_A
#define M6803_B M6800_B #define M6803_B M6800_B
#define M6803_PC M6800_PC #define M6803_PC M6800_PC
@ -164,9 +145,7 @@ extern CPU_GET_INFO( m6802 );
#define M6803_TIN_LINE M6800_TIN_LINE #define M6803_TIN_LINE M6800_TIN_LINE
extern CPU_GET_INFO( m6803 ); extern CPU_GET_INFO( m6803 );
#endif
#if (HAS_M6801||HAS_M6803||HAS_HD63701)
/* By default, on a port write port bits which are not set as output in the DDR */ /* By default, on a port write port bits which are not set as output in the DDR */
/* are set to the value returned by a read from the same port. If you need to */ /* are set to the value returned by a read from the same port. If you need to */
/* know the DDR for e.g. port 1, do m6803_internal_registers_r(M6801_DDR1) */ /* know the DDR for e.g. port 1, do m6803_internal_registers_r(M6801_DDR1) */
@ -180,12 +159,10 @@ extern CPU_GET_INFO( m6803 );
#define M6803_PORT2 0x101 #define M6803_PORT2 0x101
#define M6803_PORT3 0x102 #define M6803_PORT3 0x102
#define M6803_PORT4 0x103 #define M6803_PORT4 0x103
#endif
/**************************************************************************** /****************************************************************************
* For now make the 6808 using the m6800 variables and functions * For now make the 6808 using the m6800 variables and functions
****************************************************************************/ ****************************************************************************/
#if (HAS_M6808)
#define M6808_A M6800_A #define M6808_A M6800_A
#define M6808_B M6800_B #define M6808_B M6800_B
#define M6808_PC M6800_PC #define M6808_PC M6800_PC
@ -200,12 +177,10 @@ extern CPU_GET_INFO( m6803 );
#define M6808_IRQ_LINE M6800_IRQ_LINE #define M6808_IRQ_LINE M6800_IRQ_LINE
extern CPU_GET_INFO( m6808 ); extern CPU_GET_INFO( m6808 );
#endif
/**************************************************************************** /****************************************************************************
* For now make the HD63701 using the m6800 variables and functions * For now make the HD63701 using the m6800 variables and functions
****************************************************************************/ ****************************************************************************/
#if (HAS_HD63701)
#define HD63701_A M6800_A #define HD63701_A M6800_A
#define HD63701_B M6800_B #define HD63701_B M6800_B
#define HD63701_PC M6800_PC #define HD63701_PC M6800_PC
@ -236,12 +211,10 @@ extern CPU_GET_INFO( hd63701 );
READ8_HANDLER( hd63701_internal_registers_r ); READ8_HANDLER( hd63701_internal_registers_r );
WRITE8_HANDLER( hd63701_internal_registers_w ); WRITE8_HANDLER( hd63701_internal_registers_w );
#endif
/**************************************************************************** /****************************************************************************
* For now make the NSC8105 using the m6800 variables and functions * For now make the NSC8105 using the m6800 variables and functions
****************************************************************************/ ****************************************************************************/
#if (HAS_NSC8105)
#define NSC8105_A M6800_A #define NSC8105_A M6800_A
#define NSC8105_B M6800_B #define NSC8105_B M6800_B
#define NSC8105_PC M6800_PC #define NSC8105_PC M6800_PC
@ -257,7 +230,6 @@ WRITE8_HANDLER( hd63701_internal_registers_w );
#define NSC8105_TIN_LINE M6800_TIN_LINE #define NSC8105_TIN_LINE M6800_TIN_LINE
extern CPU_GET_INFO( nsc8105 ); extern CPU_GET_INFO( nsc8105 );
#endif
#endif #endif
#endif /* __M6800_H__ */ #endif /* __M6800_H__ */

View File

@ -310,7 +310,6 @@ INLINE void WM16( m6805_Regs *cpustate, UINT32 Addr, PAIR *p )
} }
#endif #endif
#if (HAS_M68705)
/* Generate interrupt - m68705 version */ /* Generate interrupt - m68705 version */
static void m68705_Interrupt( m6805_Regs *cpustate ) static void m68705_Interrupt( m6805_Regs *cpustate )
@ -341,7 +340,6 @@ static void m68705_Interrupt( m6805_Regs *cpustate )
cpustate->iCount -= 11; cpustate->iCount -= 11;
} }
} }
#endif
/* Generate interrupts */ /* Generate interrupts */
static void Interrupt( m6805_Regs *cpustate ) static void Interrupt( m6805_Regs *cpustate )
@ -350,7 +348,6 @@ static void Interrupt( m6805_Regs *cpustate )
/* pending_interrupts until the interrupt is taken, no matter what the */ /* pending_interrupts until the interrupt is taken, no matter what the */
/* external IRQ pin does. */ /* external IRQ pin does. */
#if (HAS_HD63705)
if( (cpustate->pending_interrupts & (1<<HD63705_INT_NMI)) != 0) if( (cpustate->pending_interrupts & (1<<HD63705_INT_NMI)) != 0)
{ {
PUSHWORD(cpustate->pc); PUSHWORD(cpustate->pc);
@ -370,10 +367,6 @@ static void Interrupt( m6805_Regs *cpustate )
} }
else if( (cpustate->pending_interrupts & ((1<<M6805_IRQ_LINE)|HD63705_INT_MASK)) != 0 ) { else if( (cpustate->pending_interrupts & ((1<<M6805_IRQ_LINE)|HD63705_INT_MASK)) != 0 ) {
if ( (CC & IFLAG) == 0 ) { if ( (CC & IFLAG) == 0 ) {
#else
if( (cpustate->pending_interrupts & (1<<M6805_IRQ_LINE)) != 0 ) {
if ( (CC & IFLAG) == 0 ) {
#endif
{ {
/* standard IRQ */ /* standard IRQ */
//#if (HAS_HD63705) //#if (HAS_HD63705)
@ -390,7 +383,6 @@ static void Interrupt( m6805_Regs *cpustate )
(*cpustate->irq_callback)(cpustate->device, 0); (*cpustate->irq_callback)(cpustate->device, 0);
#if (HAS_HD63705)
if(SUBTYPE==SUBTYPE_HD63705) if(SUBTYPE==SUBTYPE_HD63705)
{ {
/* Need to add emulation of other interrupt sources here KW-2/4/99 */ /* Need to add emulation of other interrupt sources here KW-2/4/99 */
@ -438,7 +430,6 @@ static void Interrupt( m6805_Regs *cpustate )
} }
} }
else else
#endif
{ {
RM16( cpustate, 0xffff - 5, &pPC ); RM16( cpustate, 0xffff - 5, &pPC );
} }
@ -529,13 +520,11 @@ static CPU_EXECUTE( m6805 )
{ {
if (cpustate->pending_interrupts != 0) if (cpustate->pending_interrupts != 0)
{ {
#if (HAS_M68705)
if (SUBTYPE==SUBTYPE_M68705) if (SUBTYPE==SUBTYPE_M68705)
{ {
m68705_Interrupt(cpustate); m68705_Interrupt(cpustate);
} }
else else
#endif
{ {
Interrupt(cpustate); Interrupt(cpustate);
} }
@ -817,7 +806,6 @@ static CPU_EXECUTE( m6805 )
/**************************************************************************** /****************************************************************************
* M68705 section * M68705 section
****************************************************************************/ ****************************************************************************/
#if (HAS_M68705)
static CPU_INIT( m68705 ) static CPU_INIT( m68705 )
{ {
m6805_Regs *cpustate = get_safe_token(device); m6805_Regs *cpustate = get_safe_token(device);
@ -843,12 +831,10 @@ static void m68705_set_irq_line(m6805_Regs *cpustate, int irqline, int state)
if (state != CLEAR_LINE) cpustate->pending_interrupts |= 1<<irqline; if (state != CLEAR_LINE) cpustate->pending_interrupts |= 1<<irqline;
} }
#endif
/**************************************************************************** /****************************************************************************
* HD63705 section * HD63705 section
****************************************************************************/ ****************************************************************************/
#if (HAS_HD63705)
static CPU_INIT( hd63705 ) static CPU_INIT( hd63705 )
{ {
m6805_Regs *cpustate = get_safe_token(device); m6805_Regs *cpustate = get_safe_token(device);
@ -887,7 +873,6 @@ static void hd63705_set_irq_line(m6805_Regs *cpustate, int irqline, int state)
if (state != CLEAR_LINE) cpustate->pending_interrupts |= 1<<irqline; if (state != CLEAR_LINE) cpustate->pending_interrupts |= 1<<irqline;
} }
} }
#endif
@ -998,7 +983,6 @@ CPU_GET_INFO( m6805 )
} }
#if (HAS_M68705)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -1035,10 +1019,8 @@ CPU_GET_INFO( m68705 )
default: CPU_GET_INFO_CALL(m6805); break; default: CPU_GET_INFO_CALL(m6805); break;
} }
} }
#endif
#if (HAS_HD63705)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -1096,4 +1078,3 @@ CPU_GET_INFO( hd63705 )
default: CPU_GET_INFO_CALL(m6805); break; default: CPU_GET_INFO_CALL(m6805); break;
} }
} }
#endif

View File

@ -17,7 +17,6 @@ extern CPU_GET_INFO( m6805 );
/**************************************************************************** /****************************************************************************
* 68705 section * 68705 section
****************************************************************************/ ****************************************************************************/
#if (HAS_M68705)
#define M68705_A M6805_A #define M68705_A M6805_A
#define M68705_PC M6805_PC #define M68705_PC M6805_PC
#define M68705_S M6805_S #define M68705_S M6805_S
@ -31,12 +30,10 @@ extern CPU_GET_INFO( m6805 );
extern CPU_GET_INFO( m68705 ); extern CPU_GET_INFO( m68705 );
#define CPU_M68705 CPU_GET_INFO_NAME( m68705 ) #define CPU_M68705 CPU_GET_INFO_NAME( m68705 )
#endif
/**************************************************************************** /****************************************************************************
* HD63705 section * HD63705 section
****************************************************************************/ ****************************************************************************/
#if (HAS_HD63705)
#define HD63705_A M6805_A #define HD63705_A M6805_A
#define HD63705_PC M6805_PC #define HD63705_PC M6805_PC
#define HD63705_S M6805_S #define HD63705_S M6805_S
@ -61,7 +58,6 @@ extern CPU_GET_INFO( m68705 );
extern CPU_GET_INFO( hd63705 ); extern CPU_GET_INFO( hd63705 );
#define CPU_HD63705 CPU_GET_INFO_NAME( hd63705 ) #define CPU_HD63705 CPU_GET_INFO_NAME( hd63705 )
#endif
CPU_DISASSEMBLE( m6805 ); CPU_DISASSEMBLE( m6805 );

View File

@ -2134,7 +2134,6 @@ static CPU_GET_INFO( mips3 )
R4600 VARIANTS R4600 VARIANTS
***************************************************************************/ ***************************************************************************/
#if (HAS_R4600)
static CPU_INIT( r4600be ) static CPU_INIT( r4600be )
{ {
size_t memsize = mips3com_init(&mips3.core, MIPS3_TYPE_R4600, TRUE, device, index, clock, irqcallback, NULL); size_t memsize = mips3com_init(&mips3.core, MIPS3_TYPE_R4600, TRUE, device, index, clock, irqcallback, NULL);
@ -2184,7 +2183,6 @@ CPU_GET_INFO( r4600le )
default: CPU_GET_INFO_CALL(mips3); break; default: CPU_GET_INFO_CALL(mips3); break;
} }
} }
#endif
@ -2192,7 +2190,6 @@ CPU_GET_INFO( r4600le )
R4650 VARIANTS R4650 VARIANTS
***************************************************************************/ ***************************************************************************/
#if (HAS_R4650)
static CPU_INIT( r4650be ) static CPU_INIT( r4650be )
{ {
size_t memsize = mips3com_init(&mips3.core, MIPS3_TYPE_R4650, TRUE, device, index, clock, irqcallback, NULL); size_t memsize = mips3com_init(&mips3.core, MIPS3_TYPE_R4650, TRUE, device, index, clock, irqcallback, NULL);
@ -2242,7 +2239,6 @@ CPU_GET_INFO( r4650le )
default: CPU_GET_INFO_CALL(mips3); break; default: CPU_GET_INFO_CALL(mips3); break;
} }
} }
#endif
@ -2250,7 +2246,6 @@ CPU_GET_INFO( r4650le )
R4700 VARIANTS R4700 VARIANTS
***************************************************************************/ ***************************************************************************/
#if (HAS_R4700)
static CPU_INIT( r4700be ) static CPU_INIT( r4700be )
{ {
size_t memsize = mips3com_init(&mips3.core, MIPS3_TYPE_R4700, TRUE, device, index, clock, irqcallback, NULL); size_t memsize = mips3com_init(&mips3.core, MIPS3_TYPE_R4700, TRUE, device, index, clock, irqcallback, NULL);
@ -2301,7 +2296,6 @@ CPU_GET_INFO( r4700le )
default: CPU_GET_INFO_CALL(mips3); break; default: CPU_GET_INFO_CALL(mips3); break;
} }
} }
#endif
@ -2309,7 +2303,6 @@ CPU_GET_INFO( r4700le )
R5000 VARIANTS R5000 VARIANTS
***************************************************************************/ ***************************************************************************/
#if (HAS_R5000)
static CPU_INIT( r5000be ) static CPU_INIT( r5000be )
{ {
size_t memsize = mips3com_init(&mips3.core, MIPS3_TYPE_R5000, TRUE, device, index, clock, irqcallback, NULL); size_t memsize = mips3com_init(&mips3.core, MIPS3_TYPE_R5000, TRUE, device, index, clock, irqcallback, NULL);
@ -2359,7 +2352,6 @@ CPU_GET_INFO( r5000le )
default: CPU_GET_INFO_CALL(mips3); break; default: CPU_GET_INFO_CALL(mips3); break;
} }
} }
#endif
@ -2367,7 +2359,6 @@ CPU_GET_INFO( r5000le )
QED5271 VARIANTS QED5271 VARIANTS
***************************************************************************/ ***************************************************************************/
#if (HAS_QED5271)
static CPU_INIT( qed5271be ) static CPU_INIT( qed5271be )
{ {
size_t memsize = mips3com_init(&mips3.core, MIPS3_TYPE_QED5271, TRUE, device, index, clock, irqcallback, NULL); size_t memsize = mips3com_init(&mips3.core, MIPS3_TYPE_QED5271, TRUE, device, index, clock, irqcallback, NULL);
@ -2417,7 +2408,6 @@ CPU_GET_INFO( qed5271le )
default: CPU_GET_INFO_CALL(mips3); break; default: CPU_GET_INFO_CALL(mips3); break;
} }
} }
#endif
@ -2425,7 +2415,6 @@ CPU_GET_INFO( qed5271le )
RM7000 VARIANTS RM7000 VARIANTS
***************************************************************************/ ***************************************************************************/
#if (HAS_RM7000)
static CPU_INIT( rm7000be ) static CPU_INIT( rm7000be )
{ {
size_t memsize = mips3com_init(&mips3.core, MIPS3_TYPE_RM7000, TRUE, device, index, clock, irqcallback, NULL); size_t memsize = mips3com_init(&mips3.core, MIPS3_TYPE_RM7000, TRUE, device, index, clock, irqcallback, NULL);
@ -2475,4 +2464,3 @@ CPU_GET_INFO( rm7000le )
default: CPU_GET_INFO_CALL(mips3); break; default: CPU_GET_INFO_CALL(mips3); break;
} }
} }
#endif

View File

@ -229,7 +229,6 @@ void mips3drc_set_options(const device_config *device, UINT32 options);
void mips3drc_add_fastram(const device_config *device, offs_t start, offs_t end, UINT8 readonly, void *base); void mips3drc_add_fastram(const device_config *device, offs_t start, offs_t end, UINT8 readonly, void *base);
void mips3drc_add_hotspot(const device_config *device, offs_t pc, UINT32 opcode, UINT32 cycles); void mips3drc_add_hotspot(const device_config *device, offs_t pc, UINT32 opcode, UINT32 cycles);
#if (HAS_VR4300)
CPU_GET_INFO( vr4300be ); CPU_GET_INFO( vr4300be );
CPU_GET_INFO( vr4300le ); CPU_GET_INFO( vr4300le );
#define CPU_VR4300BE CPU_GET_INFO_NAME( vr4300be ) #define CPU_VR4300BE CPU_GET_INFO_NAME( vr4300be )
@ -238,49 +237,36 @@ CPU_GET_INFO( vr4310be );
CPU_GET_INFO( vr4310le ); CPU_GET_INFO( vr4310le );
#define CPU_VR4310BE CPU_GET_INFO_NAME( vr4310be ) #define CPU_VR4310BE CPU_GET_INFO_NAME( vr4310be )
#define CPU_VR4310LE CPU_GET_INFO_NAME( vr4310le ) #define CPU_VR4310LE CPU_GET_INFO_NAME( vr4310le )
#endif
#if (HAS_R4600)
CPU_GET_INFO( r4600be ); CPU_GET_INFO( r4600be );
#define CPU_R4600BE CPU_GET_INFO_NAME( r4600be ) #define CPU_R4600BE CPU_GET_INFO_NAME( r4600be )
CPU_GET_INFO( r4600le ); CPU_GET_INFO( r4600le );
#define CPU_R4600LE CPU_GET_INFO_NAME( r4600le ) #define CPU_R4600LE CPU_GET_INFO_NAME( r4600le )
#endif
#if (HAS_R4650)
CPU_GET_INFO( r4650be); CPU_GET_INFO( r4650be);
#define CPU_R4650BE CPU_GET_INFO_NAME( r4650be ) #define CPU_R4650BE CPU_GET_INFO_NAME( r4650be )
CPU_GET_INFO( r4650le); CPU_GET_INFO( r4650le);
#define CPU_R4650LE CPU_GET_INFO_NAME( r4650le ) #define CPU_R4650LE CPU_GET_INFO_NAME( r4650le )
#endif
#if (HAS_R4700)
CPU_GET_INFO( r4700be ); CPU_GET_INFO( r4700be );
#define CPU_R4700BE CPU_GET_INFO_NAME( r4700be ) #define CPU_R4700BE CPU_GET_INFO_NAME( r4700be )
CPU_GET_INFO( r4700le ); CPU_GET_INFO( r4700le );
#define CPU_R4700LE CPU_GET_INFO_NAME( r4700le ) #define CPU_R4700LE CPU_GET_INFO_NAME( r4700le )
#endif
#if (HAS_R5000)
CPU_GET_INFO( r5000be ); CPU_GET_INFO( r5000be );
#define CPU_R5000BE CPU_GET_INFO_NAME( r5000be ) #define CPU_R5000BE CPU_GET_INFO_NAME( r5000be )
CPU_GET_INFO( r5000le ); CPU_GET_INFO( r5000le );
#define CPU_R5000LE CPU_GET_INFO_NAME( r5000le ) #define CPU_R5000LE CPU_GET_INFO_NAME( r5000le )
#endif
#if (HAS_QED5271)
CPU_GET_INFO( qed5271be ); CPU_GET_INFO( qed5271be );
#define CPU_QED5271BE CPU_GET_INFO_NAME( qed5271be ) #define CPU_QED5271BE CPU_GET_INFO_NAME( qed5271be )
CPU_GET_INFO( qed5271le ); CPU_GET_INFO( qed5271le );
#define CPU_QED5271LE CPU_GET_INFO_NAME( qed5271le ) #define CPU_QED5271LE CPU_GET_INFO_NAME( qed5271le )
#endif
#if (HAS_RM7000)
CPU_GET_INFO( rm7000be ); CPU_GET_INFO( rm7000be );
#define CPU_RM7000BE CPU_GET_INFO_NAME( rm7000be ) #define CPU_RM7000BE CPU_GET_INFO_NAME( rm7000be )
CPU_GET_INFO( rm7000le ); CPU_GET_INFO( rm7000le );
#define CPU_RM7000LE CPU_GET_INFO_NAME( rm7000le ) #define CPU_RM7000LE CPU_GET_INFO_NAME( rm7000le )
#endif

View File

@ -3676,7 +3676,6 @@ static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, i
***************************************************************************/ ***************************************************************************/
// NEC VR4300 series is MIPS III with 32-bit address bus and slightly custom COP0/TLB // NEC VR4300 series is MIPS III with 32-bit address bus and slightly custom COP0/TLB
#if (HAS_VR4300)
static CPU_INIT( vr4300be ) static CPU_INIT( vr4300be )
{ {
mips3_init(MIPS3_TYPE_VR4300, TRUE, device, irqcallback); mips3_init(MIPS3_TYPE_VR4300, TRUE, device, irqcallback);
@ -3759,14 +3758,12 @@ CPU_GET_INFO( vr4310le )
default: CPU_GET_INFO_CALL(mips3); break; default: CPU_GET_INFO_CALL(mips3); break;
} }
} }
#endif
/*************************************************************************** /***************************************************************************
R4600 VARIANTS R4600 VARIANTS
***************************************************************************/ ***************************************************************************/
#if (HAS_R4600)
static CPU_INIT( r4600be ) static CPU_INIT( r4600be )
{ {
mips3_init(MIPS3_TYPE_R4600, TRUE, device, irqcallback); mips3_init(MIPS3_TYPE_R4600, TRUE, device, irqcallback);
@ -3812,7 +3809,6 @@ CPU_GET_INFO( r4600le )
default: CPU_GET_INFO_CALL(mips3); break; default: CPU_GET_INFO_CALL(mips3); break;
} }
} }
#endif
@ -3820,7 +3816,6 @@ CPU_GET_INFO( r4600le )
R4650 VARIANTS R4650 VARIANTS
***************************************************************************/ ***************************************************************************/
#if (HAS_R4650)
static CPU_INIT( r4650be ) static CPU_INIT( r4650be )
{ {
mips3_init(MIPS3_TYPE_R4650, TRUE, device, irqcallback); mips3_init(MIPS3_TYPE_R4650, TRUE, device, irqcallback);
@ -3866,7 +3861,6 @@ CPU_GET_INFO( r4650le )
default: CPU_GET_INFO_CALL(mips3); break; default: CPU_GET_INFO_CALL(mips3); break;
} }
} }
#endif
@ -3874,7 +3868,6 @@ CPU_GET_INFO( r4650le )
R4700 VARIANTS R4700 VARIANTS
***************************************************************************/ ***************************************************************************/
#if (HAS_R4700)
static CPU_INIT( r4700be ) static CPU_INIT( r4700be )
{ {
mips3_init(MIPS3_TYPE_R4700, TRUE, device, irqcallback); mips3_init(MIPS3_TYPE_R4700, TRUE, device, irqcallback);
@ -3920,7 +3913,6 @@ CPU_GET_INFO( r4700le )
default: CPU_GET_INFO_CALL(mips3); break; default: CPU_GET_INFO_CALL(mips3); break;
} }
} }
#endif
@ -3928,7 +3920,6 @@ CPU_GET_INFO( r4700le )
R5000 VARIANTS R5000 VARIANTS
***************************************************************************/ ***************************************************************************/
#if (HAS_R5000)
static CPU_INIT( r5000be ) static CPU_INIT( r5000be )
{ {
mips3_init(MIPS3_TYPE_R5000, TRUE, device, irqcallback); mips3_init(MIPS3_TYPE_R5000, TRUE, device, irqcallback);
@ -3974,7 +3965,6 @@ CPU_GET_INFO( r5000le )
default: CPU_GET_INFO_CALL(mips3); break; default: CPU_GET_INFO_CALL(mips3); break;
} }
} }
#endif
@ -3982,7 +3972,6 @@ CPU_GET_INFO( r5000le )
QED5271 VARIANTS QED5271 VARIANTS
***************************************************************************/ ***************************************************************************/
#if (HAS_QED5271)
static CPU_INIT( qed5271be ) static CPU_INIT( qed5271be )
{ {
mips3_init(MIPS3_TYPE_QED5271, TRUE, device, irqcallback); mips3_init(MIPS3_TYPE_QED5271, TRUE, device, irqcallback);
@ -4028,7 +4017,6 @@ CPU_GET_INFO( qed5271le )
default: CPU_GET_INFO_CALL(mips3); break; default: CPU_GET_INFO_CALL(mips3); break;
} }
} }
#endif
@ -4036,7 +4024,6 @@ CPU_GET_INFO( qed5271le )
RM7000 VARIANTS RM7000 VARIANTS
***************************************************************************/ ***************************************************************************/
#if (HAS_RM7000)
static CPU_INIT( rm7000be ) static CPU_INIT( rm7000be )
{ {
mips3_init(MIPS3_TYPE_RM7000, TRUE, device, irqcallback); mips3_init(MIPS3_TYPE_RM7000, TRUE, device, irqcallback);
@ -4082,4 +4069,3 @@ CPU_GET_INFO( rm7000le )
default: CPU_GET_INFO_CALL(mips3); break; default: CPU_GET_INFO_CALL(mips3); break;
} }
} }
#endif

View File

@ -6415,7 +6415,6 @@ CPU_GET_INFO( psxcpu )
} }
#if (HAS_CXD8661R)
CPU_GET_INFO( cxd8661r ) CPU_GET_INFO( cxd8661r )
{ {
@ -6432,4 +6431,3 @@ CPU_GET_INFO( cxd8661r )
} }
} }
#endif

View File

@ -1139,7 +1139,6 @@ static void nec_init(const device_config *device, cpu_irq_callback irqcallback,
8-bit memory accessors 8-bit memory accessors
*****************************************************************************/ *****************************************************************************/
#if (HAS_V20||HAS_V25)
static void configure_memory_8bit(nec_state_t *nec_state) static void configure_memory_8bit(nec_state_t *nec_state)
{ {
nec_state->mem.fetch_xor = 0; nec_state->mem.fetch_xor = 0;
@ -1149,14 +1148,12 @@ static void configure_memory_8bit(nec_state_t *nec_state)
nec_state->mem.wbyte = memory_write_byte_8le; nec_state->mem.wbyte = memory_write_byte_8le;
nec_state->mem.wword = memory_write_word_8le; nec_state->mem.wword = memory_write_word_8le;
} }
#endif
/***************************************************************************** /*****************************************************************************
16-bit memory accessors 16-bit memory accessors
*****************************************************************************/ *****************************************************************************/
#if (HAS_V30||HAS_V33||HAS_V35)
static UINT16 read_word_16le(const address_space *space, offs_t addr) static UINT16 read_word_16le(const address_space *space, offs_t addr)
{ {
if (!(addr & 1)) if (!(addr & 1))
@ -1188,7 +1185,6 @@ static void configure_memory_16bit(nec_state_t *nec_state)
nec_state->mem.wbyte = memory_write_byte_16le; nec_state->mem.wbyte = memory_write_byte_16le;
nec_state->mem.wword = write_word_16le; nec_state->mem.wword = write_word_16le;
} }
#endif
static CPU_EXECUTE( necv ) static CPU_EXECUTE( necv )
{ {
@ -1220,7 +1216,6 @@ static CPU_EXECUTE( necv )
} }
/* Wrappers for the different CPU types */ /* Wrappers for the different CPU types */
#if (HAS_V20||HAS_V25)
static CPU_INIT( v20 ) static CPU_INIT( v20 )
{ {
nec_state_t *nec_state = get_safe_token(device); nec_state_t *nec_state = get_safe_token(device);
@ -1231,9 +1226,7 @@ static CPU_INIT( v20 )
nec_state->prefetch_size = 4; /* 3 words */ nec_state->prefetch_size = 4; /* 3 words */
nec_state->prefetch_cycles = 4; /* four cycles per byte */ nec_state->prefetch_cycles = 4; /* four cycles per byte */
} }
#endif
#if (HAS_V30||HAS_V35)
static CPU_INIT( v30 ) static CPU_INIT( v30 )
{ {
nec_state_t *nec_state = get_safe_token(device); nec_state_t *nec_state = get_safe_token(device);
@ -1245,9 +1238,7 @@ static CPU_INIT( v30 )
nec_state->prefetch_cycles = 2; /* two cycles per byte / four per word */ nec_state->prefetch_cycles = 2; /* two cycles per byte / four per word */
} }
#endif
#if (HAS_V33)
static CPU_INIT( v33 ) static CPU_INIT( v33 )
{ {
nec_state_t *nec_state = get_safe_token(device); nec_state_t *nec_state = get_safe_token(device);
@ -1262,7 +1253,6 @@ static CPU_INIT( v33 )
configure_memory_16bit(nec_state); configure_memory_16bit(nec_state);
} }
#endif
@ -1441,7 +1431,6 @@ static CPU_GET_INFO( nec )
} }
#if (HAS_V20)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -1463,10 +1452,8 @@ CPU_GET_INFO( v20 )
default: CPU_GET_INFO_CALL(nec); break; default: CPU_GET_INFO_CALL(nec); break;
} }
} }
#endif
#if (HAS_V25)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -1488,10 +1475,8 @@ CPU_GET_INFO( v25 )
default: CPU_GET_INFO_CALL(nec); break; default: CPU_GET_INFO_CALL(nec); break;
} }
} }
#endif
#if (HAS_V30)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -1509,10 +1494,8 @@ CPU_GET_INFO( v30 )
default: CPU_GET_INFO_CALL(nec); break; default: CPU_GET_INFO_CALL(nec); break;
} }
} }
#endif
#if (HAS_V33)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -1530,10 +1513,8 @@ CPU_GET_INFO( v33 )
default: CPU_GET_INFO_CALL(nec); break; default: CPU_GET_INFO_CALL(nec); break;
} }
} }
#endif
#if (HAS_V35)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -1551,4 +1532,3 @@ CPU_GET_INFO( v35 )
default: CPU_GET_INFO_CALL(nec); break; default: CPU_GET_INFO_CALL(nec); break;
} }
} }
#endif

View File

@ -1110,7 +1110,6 @@ static CPU_GET_INFO( pic16c5x )
#if (HAS_PIC16C54)
/**************************************************************************** /****************************************************************************
* Internal Memory Map * Internal Memory Map
****************************************************************************/ ****************************************************************************/
@ -1161,10 +1160,8 @@ CPU_GET_INFO( pic16c54 )
default: CPU_GET_INFO_CALL(pic16c5x); break; default: CPU_GET_INFO_CALL(pic16c5x); break;
} }
} }
#endif
#if (HAS_PIC16C55)
/**************************************************************************** /****************************************************************************
* Internal Memory Map * Internal Memory Map
****************************************************************************/ ****************************************************************************/
@ -1215,10 +1212,8 @@ CPU_GET_INFO( pic16c55 )
default: CPU_GET_INFO_CALL(pic16c5x); break; default: CPU_GET_INFO_CALL(pic16c5x); break;
} }
} }
#endif
#if (HAS_PIC16C56)
/**************************************************************************** /****************************************************************************
* Internal Memory Map * Internal Memory Map
****************************************************************************/ ****************************************************************************/
@ -1271,10 +1266,8 @@ CPU_GET_INFO( pic16c56 )
default: CPU_GET_INFO_CALL(pic16c5x); break; default: CPU_GET_INFO_CALL(pic16c5x); break;
} }
} }
#endif
#if (HAS_PIC16C57)
/**************************************************************************** /****************************************************************************
* Internal Memory Map * Internal Memory Map
****************************************************************************/ ****************************************************************************/
@ -1331,10 +1324,8 @@ CPU_GET_INFO( pic16c57 )
default: CPU_GET_INFO_CALL(pic16c5x); break; default: CPU_GET_INFO_CALL(pic16c5x); break;
} }
} }
#endif
#if (HAS_PIC16C58)
/**************************************************************************** /****************************************************************************
* Internal Memory Map * Internal Memory Map
****************************************************************************/ ****************************************************************************/
@ -1391,4 +1382,3 @@ CPU_GET_INFO( pic16c58 )
default: CPU_GET_INFO_CALL(pic16c5x); break; default: CPU_GET_INFO_CALL(pic16c5x); break;
} }
} }
#endif

View File

@ -48,39 +48,27 @@ void pic16c5x_set_config(const device_config *cpu, int data);
#if (HAS_PIC16C54)
CPU_GET_INFO( pic16c54 ); CPU_GET_INFO( pic16c54 );
#define CPU_PIC16C54 CPU_GET_INFO_NAME( pic16c54 ) #define CPU_PIC16C54 CPU_GET_INFO_NAME( pic16c54 )
#endif
#if (HAS_PIC16C55)
CPU_GET_INFO( pic16c55 ); CPU_GET_INFO( pic16c55 );
#define CPU_PIC16C55 CPU_GET_INFO_NAME( pic16c55 ) #define CPU_PIC16C55 CPU_GET_INFO_NAME( pic16c55 )
#endif
#if (HAS_PIC16C56)
CPU_GET_INFO( pic16c56 ); CPU_GET_INFO( pic16c56 );
#define CPU_PIC16C56 CPU_GET_INFO_NAME( pic16c56 ) #define CPU_PIC16C56 CPU_GET_INFO_NAME( pic16c56 )
#endif
#if (HAS_PIC16C57)
CPU_GET_INFO( pic16c57 ); CPU_GET_INFO( pic16c57 );
#define CPU_PIC16C57 CPU_GET_INFO_NAME( pic16c57 ) #define CPU_PIC16C57 CPU_GET_INFO_NAME( pic16c57 )
#endif
#if (HAS_PIC16C58)
CPU_GET_INFO( pic16c58 ); CPU_GET_INFO( pic16c58 );
#define CPU_PIC16C58 CPU_GET_INFO_NAME( pic16c58 ) #define CPU_PIC16C58 CPU_GET_INFO_NAME( pic16c58 )
#endif
#if (HAS_PIC16C54) || (HAS_PIC16C55) || (HAS_PIC16C56) || (HAS_PIC16C57) || (HAS_PIC16C58)
CPU_DISASSEMBLE( pic16c5x ); CPU_DISASSEMBLE( pic16c5x );
#endif
#endif /* __PIC16C5X_H__ */ #endif /* __PIC16C5X_H__ */

View File

@ -958,7 +958,6 @@ static CPU_SET_INFO( sharc )
} }
} }
#if (HAS_ADSP21062)
static CPU_SET_INFO( adsp21062 ) static CPU_SET_INFO( adsp21062 )
{ {
if (state >= CPUINFO_INT_INPUT_STATE && state <= CPUINFO_INT_INPUT_STATE + 2) if (state >= CPUINFO_INT_INPUT_STATE && state <= CPUINFO_INT_INPUT_STATE + 2)
@ -976,7 +975,6 @@ static CPU_SET_INFO( adsp21062 )
default: CPU_SET_INFO_CALL(sharc); break; default: CPU_SET_INFO_CALL(sharc); break;
} }
} }
#endif
static CPU_READ( sharc ) static CPU_READ( sharc )
@ -1327,7 +1325,6 @@ static CPU_GET_INFO( sharc )
} }
} }
#if (HAS_ADSP21062)
CPU_GET_INFO( adsp21062 ) CPU_GET_INFO( adsp21062 )
{ {
switch(state) switch(state)
@ -1341,4 +1338,3 @@ CPU_GET_INFO( adsp21062 )
default: CPU_GET_INFO_CALL(sharc); break; default: CPU_GET_INFO_CALL(sharc); break;
} }
} }
#endif

View File

@ -27,10 +27,8 @@ extern void sharc_set_flag_input(const device_config *device, int flag_num, int
extern void sharc_external_iop_write(const device_config *device, UINT32 address, UINT32 data); extern void sharc_external_iop_write(const device_config *device, UINT32 address, UINT32 data);
extern void sharc_external_dma_write(const device_config *device, UINT32 address, UINT64 data); extern void sharc_external_dma_write(const device_config *device, UINT32 address, UINT64 data);
#if (HAS_ADSP21062)
CPU_GET_INFO( adsp21062 ); CPU_GET_INFO( adsp21062 );
#define CPU_ADSP21062 CPU_GET_INFO_NAME( adsp21062 ) #define CPU_ADSP21062 CPU_GET_INFO_NAME( adsp21062 )
#endif
extern UINT32 sharc_dasm_one(char *buffer, offs_t pc, UINT64 opcode); extern UINT32 sharc_dasm_one(char *buffer, offs_t pc, UINT64 opcode);

View File

@ -771,7 +771,6 @@ static CPU_DISASSEMBLE( ssp1601 )
return dasm_ssp1601(buffer, pc, oprom); return dasm_ssp1601(buffer, pc, oprom);
} }
#if (HAS_SSP1601)
static CPU_SET_INFO( ssp1601 ) static CPU_SET_INFO( ssp1601 )
{ {
@ -919,7 +918,6 @@ CPU_GET_INFO( ssp1601 )
case CPUINFO_STR_REGISTER + SSP_PR7: sprintf(info->s, "R7 :%02X", ssp1601_state->r[7]); break; case CPUINFO_STR_REGISTER + SSP_PR7: sprintf(info->s, "R7 :%02X", ssp1601_state->r[7]); break;
} }
} }
#endif
// vim:ts=4 // vim:ts=4

View File

@ -16,10 +16,8 @@ enum
SSP_PR0, SSP_PR1, SSP_PR2, SSP_PR3, SSP_PR4, SSP_PR5, SSP_PR6, SSP_PR7 SSP_PR0, SSP_PR1, SSP_PR2, SSP_PR3, SSP_PR4, SSP_PR5, SSP_PR6, SSP_PR7
}; };
#if (HAS_SSP1601)
CPU_GET_INFO( ssp1601 ); CPU_GET_INFO( ssp1601 );
#define CPU_SSP1601 CPU_GET_INFO_NAME( ssp1601 ) #define CPU_SSP1601 CPU_GET_INFO_NAME( ssp1601 )
#endif
extern unsigned dasm_ssp1601(char *buffer, unsigned pc, const UINT8 *oprom); extern unsigned dasm_ssp1601(char *buffer, unsigned pc, const UINT8 *oprom);

View File

@ -1796,7 +1796,6 @@ static CPU_RESET( tms32025 )
cpustate->datamap[7] = &cpustate->intRAM[0x380]; /* B1 */ cpustate->datamap[7] = &cpustate->intRAM[0x380]; /* B1 */
} }
#if (HAS_TMS32026)
static CPU_RESET( tms32026 ) static CPU_RESET( tms32026 )
{ {
tms32025_state *cpustate = get_safe_token(device); tms32025_state *cpustate = get_safe_token(device);
@ -1821,7 +1820,6 @@ static CPU_RESET( tms32026 )
cpustate->datamap[14] = &cpustate->intRAM[0x700]; /* B3 */ cpustate->datamap[14] = &cpustate->intRAM[0x700]; /* B3 */
cpustate->datamap[15] = &cpustate->intRAM[0x780]; /* B3 */ cpustate->datamap[15] = &cpustate->intRAM[0x780]; /* B3 */
} }
#endif
/**************************************************************************** /****************************************************************************
@ -2436,7 +2434,6 @@ CPU_GET_INFO( tms32025 )
} }
#if (HAS_TMS32026)
/************************************************************************** /**************************************************************************
* CPU-specific set_info * CPU-specific set_info
**************************************************************************/ **************************************************************************/
@ -2454,4 +2451,3 @@ CPU_GET_INFO( tms32026 )
default: CPU_GET_INFO_CALL(tms32025); break; default: CPU_GET_INFO_CALL(tms32025); break;
} }
} }
#endif

View File

@ -679,7 +679,6 @@ static CPU_GET_INFO( tms )
} }
} }
#if (HAS_TMS32051)
static CPU_SET_INFO( tms32051 ) static CPU_SET_INFO( tms32051 )
{ {
tms32051_state *cpustate = get_safe_token(device); tms32051_state *cpustate = get_safe_token(device);
@ -732,4 +731,3 @@ CPU_GET_INFO( tms32051 )
default: CPU_GET_INFO_CALL(tms); break; default: CPU_GET_INFO_CALL(tms); break;
} }
} }
#endif

View File

@ -3,10 +3,8 @@
#ifndef __TMS32051_H__ #ifndef __TMS32051_H__
#define __TMS32051_H__ #define __TMS32051_H__
#if (HAS_TMS32051)
CPU_GET_INFO( tms32051 ); CPU_GET_INFO( tms32051 );
#define CPU_TMS32051 CPU_GET_INFO_NAME( tms32051 ) #define CPU_TMS32051 CPU_GET_INFO_NAME( tms32051 )
#endif
CPU_DISASSEMBLE( tms32051 ); CPU_DISASSEMBLE( tms32051 );

View File

@ -52,7 +52,6 @@ typedef void (*ti99xx_lrex_func)(const device_config *device);
typedef void (*ti99xx_ckon_ckof_func)(const device_config *device, int state); typedef void (*ti99xx_ckon_ckof_func)(const device_config *device, int state);
typedef void (*ti99xx_error_interrupt_func)(const device_config *device, int state); typedef void (*ti99xx_error_interrupt_func)(const device_config *device, int state);
#if (HAS_TI990_10)
extern CPU_GET_INFO( ti990_10 ); extern CPU_GET_INFO( ti990_10 );
#define CPU_TI990_10 CPU_GET_INFO_NAME( ti990_10 ) #define CPU_TI990_10 CPU_GET_INFO_NAME( ti990_10 )
@ -80,9 +79,7 @@ extern WRITE8_HANDLER(ti990_10_mapper_cru_w);
extern READ8_HANDLER(ti990_10_eir_cru_r); extern READ8_HANDLER(ti990_10_eir_cru_r);
extern WRITE8_HANDLER(ti990_10_eir_cru_w); extern WRITE8_HANDLER(ti990_10_eir_cru_w);
#endif
#if (HAS_TMS9900)
extern CPU_GET_INFO( tms9900 ); extern CPU_GET_INFO( tms9900 );
#define CPU_TMS9900 CPU_GET_INFO_NAME( tms9900 ) #define CPU_TMS9900 CPU_GET_INFO_NAME( tms9900 )
@ -95,9 +92,7 @@ typedef struct tms9900reset_param
ti99xx_idle_func idle_callback; ti99xx_idle_func idle_callback;
} tms9900reset_param; } tms9900reset_param;
#endif
#if (HAS_TMS9940)
extern CPU_GET_INFO( tms9940 ); extern CPU_GET_INFO( tms9940 );
#define CPU_TMS9940 CPU_GET_INFO_NAME( tms9940 ) #define CPU_TMS9940 CPU_GET_INFO_NAME( tms9940 )
@ -110,9 +105,7 @@ typedef struct tms9940reset_param
ti99xx_idle_func idle_callback; ti99xx_idle_func idle_callback;
} tms9940reset_param; } tms9940reset_param;
#endif
#if (HAS_TMS9980)
extern CPU_GET_INFO( tms9980a ); extern CPU_GET_INFO( tms9980a );
#define CPU_TMS9980 CPU_GET_INFO_NAME( tms9980a ) #define CPU_TMS9980 CPU_GET_INFO_NAME( tms9980a )
@ -125,9 +118,7 @@ typedef struct tms9980areset_param
ti99xx_idle_func idle_callback; ti99xx_idle_func idle_callback;
} tms9980areset_param; } tms9980areset_param;
#endif
#if (HAS_TMS9985)
extern CPU_GET_INFO( tms9985 ); extern CPU_GET_INFO( tms9985 );
#define CPU_TMS9986 CPU_GET_INFO_NAME( tms9985 ) #define CPU_TMS9986 CPU_GET_INFO_NAME( tms9985 )
@ -140,9 +131,7 @@ typedef struct tms9985reset_param
ti99xx_idle_func idle_callback; ti99xx_idle_func idle_callback;
} tms9985reset_param; } tms9985reset_param;
#endif
#if (HAS_TMS9989)
extern CPU_GET_INFO( tms9989 ); extern CPU_GET_INFO( tms9989 );
#define CPU_TMS9989 CPU_GET_INFO_NAME( tms9989 ) #define CPU_TMS9989 CPU_GET_INFO_NAME( tms9989 )
@ -155,9 +144,7 @@ typedef struct tms9989reset_param
ti99xx_idle_func idle_callback; ti99xx_idle_func idle_callback;
} tms9989reset_param; } tms9989reset_param;
#endif
#if (HAS_TMS9995)
extern CPU_GET_INFO( tms9995 ); extern CPU_GET_INFO( tms9995 );
#define CPU_TMS9995 CPU_GET_INFO_NAME( tms9995 ) #define CPU_TMS9995 CPU_GET_INFO_NAME( tms9995 )
@ -186,9 +173,7 @@ extern WRITE8_HANDLER(tms9995_internal1_w);
extern READ8_HANDLER(tms9995_internal2_r); extern READ8_HANDLER(tms9995_internal2_r);
extern WRITE8_HANDLER(tms9995_internal2_w); extern WRITE8_HANDLER(tms9995_internal2_w);
#endif
#if (HAS_TMS99000)
extern CPU_GET_INFO( tms99000 ); extern CPU_GET_INFO( tms99000 );
#define CPU_TMS99000 CPU_GET_INFO_NAME( tms99000 ) #define CPU_TMS99000 CPU_GET_INFO_NAME( tms99000 )
@ -201,9 +186,7 @@ typedef struct tms99000reset_param
ti99xx_idle_func idle_callback; ti99xx_idle_func idle_callback;
} tms99000reset_param; } tms99000reset_param;
#endif
#if (HAS_TMS99105A)
extern CPU_GET_INFO( tms99105a ); extern CPU_GET_INFO( tms99105a );
#define CPU_TMS99105A CPU_GET_INFO_NAME( tms99105a ) #define CPU_TMS99105A CPU_GET_INFO_NAME( tms99105a )
@ -216,9 +199,7 @@ typedef struct tms99105areset_param
ti99xx_idle_func idle_callback; ti99xx_idle_func idle_callback;
} tms99105areset_param; } tms99105areset_param;
#endif
#if (HAS_TMS99110A)
extern CPU_GET_INFO( tms99110a ); extern CPU_GET_INFO( tms99110a );
#define CPU_TMS99110A CPU_GET_INFO_NAME( tms99110a ) #define CPU_TMS99110A CPU_GET_INFO_NAME( tms99110a )
@ -231,7 +212,6 @@ typedef struct tms99110areset_param
ti99xx_idle_func idle_callback; ti99xx_idle_func idle_callback;
} tms99110areset_param; } tms99110areset_param;
#endif
unsigned Dasm9900 (char *buffer, unsigned pc, int model_id, const UINT8 *oprom, const UINT8 *opram); unsigned Dasm9900 (char *buffer, unsigned pc, int model_id, const UINT8 *oprom, const UINT8 *opram);

View File

@ -81,14 +81,10 @@ enum
extern const char *const v60_reg_names[]; extern const char *const v60_reg_names[];
void v60_stall(const device_config *device); void v60_stall(const device_config *device);
#if HAS_V60
CPU_GET_INFO( v60 ); CPU_GET_INFO( v60 );
#define CPU_V60 CPU_GET_INFO_NAME( v60 ) #define CPU_V60 CPU_GET_INFO_NAME( v60 )
#endif /* HAS_V60 */
#if HAS_V70
CPU_GET_INFO( v70 ); CPU_GET_INFO( v70 );
#define CPU_V70 CPU_GET_INFO_NAME( v70 ) #define CPU_V70 CPU_GET_INFO_NAME( v70 )
#endif /* HAS_V70 */
#endif /* __V60_H__ */ #endif /* __V60_H__ */

View File

@ -37,139 +37,52 @@ CPUS += Z80
CPUS += Z180 CPUS += Z180
CPUS += I8085 CPUS += I8085
CPUS += M6502 CPUS += M6502
CPUS += M65C02
CPUS += M65SC02
CPUS += M65CE02
CPUS += M6509
CPUS += M6510
CPUS += M6510T
CPUS += M7501
CPUS += M8502
CPUS += N2A03
CPUS += DECO16
CPUS += M4510
CPUS += H6280 CPUS += H6280
CPUS += I8086 CPUS += I86
CPUS += I8088
CPUS += I80186
CPUS += I80188
CPUS += I80286
CPUS += I386 CPUS += I386
CPUS += I486 CPUS += NEC
CPUS += PENTIUM
CPUS += MEDIAGX
CPUS += V20
CPUS += V25
CPUS += V30
CPUS += V30MZ CPUS += V30MZ
CPUS += V33
CPUS += V35
CPUS += V60 CPUS += V60
CPUS += V70
CPUS += MCS48 CPUS += MCS48
CPUS += I8031 CPUS += MCS51
CPUS += I8032
CPUS += I8051
CPUS += I8052
CPUS += I8751
CPUS += I8752
CPUS += I80C31
CPUS += I80C32
CPUS += I80C51
CPUS += I80C52
CPUS += I87C51
CPUS += I87C52
CPUS += AT89C4051
CPUS += DS5002FP
CPUS += M6800 CPUS += M6800
CPUS += M6801
CPUS += M6802
CPUS += M6803
CPUS += M6808
CPUS += HD63701
CPUS += NSC8105
CPUS += M6805 CPUS += M6805
CPUS += M68705
CPUS += HD63705
CPUS += HD6309 CPUS += HD6309
CPUS += M6809 CPUS += M6809
CPUS += M6809E
CPUS += KONAMI CPUS += KONAMI
CPUS += M680X0 CPUS += M680X0
CPUS += T11 CPUS += T11
CPUS += S2650 CPUS += S2650
CPUS += TMS340X0 CPUS += TMS340X0
CPUS += TMS9900 CPUS += TMS9900
CPUS += TMS9940
CPUS += TMS9980
CPUS += TMS9985
CPUS += TMS9989
CPUS += TMS9995
CPUS += TMS99105A
CPUS += TMS99110A
CPUS += TMS99000
CPUS += TMS99010
CPUS += Z8000 CPUS += Z8000
CPUS += TMS32010 CPUS += TMS32010
CPUS += TMS32025 CPUS += TMS32025
CPUS += TMS32026
CPUS += TMS32031 CPUS += TMS32031
CPUS += TMS32032
CPUS += TMS32051 CPUS += TMS32051
CPUS += TMS57002 CPUS += TMS57002
CPUS += CCPU CPUS += CCPU
CPUS += ADSP21XX CPUS += ADSP21XX
CPUS += PSXCPU
CPUS += CXD8661R
CPUS += ASAP CPUS += ASAP
CPUS += UPD7810 CPUS += UPD7810
CPUS += UPD7807
CPUS += UPD7801
CPUS += ARM CPUS += ARM
CPUS += ARM7 CPUS += ARM7
CPUS += JAGUAR CPUS += JAGUAR
CPUS += CUBEQCPU CPUS += CUBEQCPU
CPUS += ESRIP CPUS += ESRIP
CPUS += R3000 CPUS += MIPS
CPUS += R3041
CPUS += VR4300
CPUS += R4600
CPUS += R4650
CPUS += R4700
CPUS += R5000
CPUS += QED5271
CPUS += RM7000
CPUS += SH1
CPUS += SH2 CPUS += SH2
CPUS += SH4 CPUS += SH4
CPUS += DSP32C CPUS += DSP32C
CPUS += PIC16C54 CPUS += PIC16C5X
CPUS += PIC16C55
CPUS += PIC16C56
CPUS += PIC16C57
CPUS += PIC16C58
CPUS += G65816 CPUS += G65816
CPUS += SPC700 CPUS += SPC700
CPUS += E116T CPUS += E1
CPUS += E116XT
CPUS += E116XS
CPUS += E116XSR
CPUS += E132N
CPUS += E132T
CPUS += E132XN
CPUS += E132XT
CPUS += E132XS
CPUS += E132XSR
CPUS += GMS30C2116
CPUS += GMS30C2132
CPUS += GMS30C2216
CPUS += GMS30C2232
CPUS += I860 CPUS += I860
CPUS += I960 CPUS += I960
CPUS += H83002 CPUS += H83002
CPUS += H83334 CPUS += H83334
CPUS += V810 CPUS += V810
CPUS += M37702
CPUS += M37710 CPUS += M37710
CPUS += POWERPC CPUS += POWERPC
CPUS += SE3208 CPUS += SE3208
@ -178,14 +91,10 @@ CPUS += ADSP21062
CPUS += DSP56156 CPUS += DSP56156
CPUS += RSP CPUS += RSP
CPUS += ALPHA8201 CPUS += ALPHA8201
CPUS += ALPHA8301
CPUS += CDP1802 CPUS += CDP1802
CPUS += COP400 CPUS += COP400
CPUS += TLCS90 CPUS += TLCS90
CPUS += MB8841 CPUS += MB88XX
CPUS += MB8842
CPUS += MB8843
CPUS += MB8844
CPUS += MB86233 CPUS += MB86233
CPUS += SSP1601 CPUS += SSP1601
CPUS += APEXC CPUS += APEXC
@ -195,10 +104,8 @@ CPUS += LH5801
CPUS += PDP1 CPUS += PDP1
CPUS += SATURN CPUS += SATURN
CPUS += SC61860 CPUS += SC61860
CPUS += TX0
CPUS += LR35902 CPUS += LR35902
CPUS += TMS7000 CPUS += TMS7000
CPUS += TMS7000_EXL
CPUS += SM8500 CPUS += SM8500
CPUS += MINX CPUS += MINX

View File

@ -35,10 +35,10 @@ OBJDIRS += \
CPUS += Z80 CPUS += Z80
CPUS += M6502 CPUS += M6502
CPUS += M6808 CPUS += M6800
CPUS += M6809 CPUS += M6809
CPUS += M68000 CPUS += M68000
CPUS += DS5002FP CPUS += MCS51
@ -93,4 +93,4 @@ DRVLIBS = \
$(DRIVERS)/astrocde.o: $(LAYOUT)/gorf.lh \ $(DRIVERS)/astrocde.o: $(LAYOUT)/gorf.lh \
$(LAYOUT)/tenpindx.lh $(LAYOUT)/tenpindx.lh
$(DRIVERS)/circus.o: $(LAYOUT)/circus.lh \ $(DRIVERS)/circus.o: $(LAYOUT)/circus.lh \
$(LAYOUT)/crash.lh $(LAYOUT)/crash.lh