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https://github.com/holub/mame
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rx01_cpu: Add the rest of the branch conditions (nw)
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0709c3fe27
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a977684012
@ -55,6 +55,7 @@ rx01_cpu_device::rx01_cpu_device(const machine_config &mconfig, const char *tag,
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, m_flags(0)
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, m_flags(0)
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, m_unit(false)
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, m_unit(false)
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, m_load_head(false)
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, m_load_head(false)
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, m_syn_index(false)
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, m_icount(0)
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, m_icount(0)
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{
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{
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std::fill(std::begin(m_sp), std::end(m_sp), 0);
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std::fill(std::begin(m_sp), std::end(m_sp), 0);
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@ -95,6 +96,7 @@ void rx01_cpu_device::device_start()
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state_add(RX01_CRC, "CRC", m_crc).formatstr("%06O");
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state_add(RX01_CRC, "CRC", m_crc).formatstr("%06O");
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state_add(RX01_UNIT, "UNIT", m_unit);
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state_add(RX01_UNIT, "UNIT", m_unit);
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state_add(RX01_LDHD, "LDHD", m_load_head);
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state_add(RX01_LDHD, "LDHD", m_load_head);
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state_add(RX01_INDEX, "INDEX", m_syn_index);
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// Save state registration
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// Save state registration
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save_item(NAME(m_pc));
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save_item(NAME(m_pc));
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@ -111,6 +113,7 @@ void rx01_cpu_device::device_start()
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save_item(NAME(m_flags));
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save_item(NAME(m_flags));
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save_item(NAME(m_unit));
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save_item(NAME(m_unit));
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save_item(NAME(m_load_head));
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save_item(NAME(m_load_head));
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save_item(NAME(m_syn_index));
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}
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}
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void rx01_cpu_device::device_reset()
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void rx01_cpu_device::device_reset()
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@ -149,6 +152,12 @@ bool rx01_cpu_device::sep_data()
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return false;
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return false;
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}
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}
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bool rx01_cpu_device::sep_clk()
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{
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// TODO
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return false;
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}
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bool rx01_cpu_device::missing_clk()
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bool rx01_cpu_device::missing_clk()
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{
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{
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// TODO
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// TODO
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@ -185,6 +194,10 @@ bool rx01_cpu_device::test_condition()
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// Serial data from interface
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// Serial data from interface
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return data_in();
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return data_in();
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case 014:
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// Drive index latch
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return m_syn_index;
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case 020:
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case 020:
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// MSB of shift register
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// MSB of shift register
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return BIT(m_sr, 7);
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return BIT(m_sr, 7);
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@ -201,6 +214,18 @@ bool rx01_cpu_device::test_condition()
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// Track zero of selected drive on head
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// Track zero of selected drive on head
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return (m_flags & FF_IOB0) && (m_flags & FF_IOB3) && drv_sel_trk0();
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return (m_flags & FF_IOB0) && (m_flags & FF_IOB3) && drv_sel_trk0();
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case 040:
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// Drive write protect (TODO)
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return false;
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case 044:
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// Separated clock
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return sep_clk();
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case 050:
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// 12-bit interface mode selected (TODO)
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return false;
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case 054:
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case 054:
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// Separated data equals shift register MSB
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// Separated data equals shift register MSB
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return BIT(m_sr, 7) == sep_data();
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return BIT(m_sr, 7) == sep_data();
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@ -225,7 +250,8 @@ bool rx01_cpu_device::test_condition()
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return (m_flags & FF_FLAG) != 0;
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return (m_flags & FF_FLAG) != 0;
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default:
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default:
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LOG("%04o: Unhandled branch condition %d\n", m_ppc, (m_mb & 074) >> 2);
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// Shouldn't happen
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logerror("%04o: Unhandled branch condition %d\n", m_ppc, (m_mb & 074) >> 2);
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return true;
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return true;
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}
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}
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}
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}
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@ -357,6 +383,7 @@ void rx01_cpu_device::execute_run()
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case 040:
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case 040:
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m_load_head = BIT(m_mb, 1);
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m_load_head = BIT(m_mb, 1);
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m_syn_index = false;
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break;
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break;
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case 044:
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case 044:
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@ -16,7 +16,7 @@ public:
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RX01_R8, RX01_R9, RX01_R10, RX01_R11, RX01_R12, RX01_R13, RX01_R14, RX01_R15,
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RX01_R8, RX01_R9, RX01_R10, RX01_R11, RX01_R12, RX01_R13, RX01_R14, RX01_R15,
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RX01_BAR,
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RX01_BAR,
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RX01_CRC,
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RX01_CRC,
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RX01_UNIT, RX01_LDHD
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RX01_UNIT, RX01_LDHD, RX01_INDEX
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};
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};
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enum : u16 {
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enum : u16 {
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@ -58,6 +58,7 @@ private:
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u8 mux_out();
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u8 mux_out();
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bool data_in();
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bool data_in();
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bool sep_data();
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bool sep_data();
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bool sep_clk();
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bool missing_clk();
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bool missing_clk();
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bool drv_sel_trk0();
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bool drv_sel_trk0();
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bool sec_buf_in();
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bool sec_buf_in();
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@ -88,6 +89,7 @@ private:
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u16 m_flags;
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u16 m_flags;
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bool m_unit;
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bool m_unit;
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bool m_load_head;
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bool m_load_head;
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bool m_syn_index;
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s32 m_icount;
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s32 m_icount;
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};
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};
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