- Added a default NVRAM to fastdrwp.
- Derivated inputs for fasdrwp.
- Added buttons-lamps layout for fastdrwp.
- Promoted fastdrwp set to working.
Systems promoted to working
---------------------------
Fast Draw (poker conversion kit) [Roberto Fresca, Grull Osgo]
Sega Rally has an instruction that calculates d += p and loads a value into d at the same time; it is the loaded value that should be used, not the result of the ALU operation
Also only test the d register when performing an ALU operation
cpu/drcbex64.cpp: Avoid a lot of unnecessary flag manipulation on
shift/rotate operations. Don't calculate flags when not requested.
Don't preserve carry in for operations that don't use it as an input.
cpu/drcbex64.cpp: Avoid loading CL when ECX can be used. Loading CL
doesn't clear the upper bits, so it depends on the previous value of
RCX, causing pipeline dependencies. Loading ECX can grab a fresh rename
register.
cpu/drcbearm64.cpp: Attempt more optimisation on one more load immediate
operation.
cpu/e132xs: Get rid of a redundant TEST - ROLAND can set the Z flag.
* cpu/uml.cpp: Handle some more cases where ROLAND can be turned into
AND in the simplifier.
* cpu/drcbearm.cpp, cpu/drcbex64.cpp: Fixed a number of cases where
4-byte operations wouldn't clear the upper half of the destination
(there are plenty more of these caused by the simplifier that will be
harder to fix).
* cpu/drcbearm64.cpp: Fixed some cases where a conditional MOV could
unexpectedly clear the upper bits of the destination.
* cpu/drcbex64.cpp: Improved code generation for various arithmetic and
logical operations. More AND/OR/XOR/ADD/ADDC operand combinations are
optimised. Special cases of ROLAND/ROLINS are optimised.
* cpu/drcbex64.cpp: Don't treat operands to FADD/FMUL as commutative.
This isn't true when one is a NaN.
-cpu/e132xs: Use osd_printf_error for diagnositc output, and make more
local variables const.
* bus/nes/disksys.cpp: Updates
- Fix dead link
- Implement readable nametable mirroring status
- Fix save state support, Fix initializing function
* sound/rp2c33_snd.cpp: Fix dead link
* Mix and pan sliders work.
* Master volume knob works.
* Tuning knobs and trimmer work. Adjusted knob sensitivity on the layout.
* Corrected relative levels of voices.
* Added output LPF and DC-blocking HPFs.
* Mild refactoring: moved voice setup in strobe_* functions.
- Implemented a custom timer and counter to get correct reads in unknown hardware.
- Added buttons-lamps layout to smshilo.
- Promoted dphl, dphljp, and smshilo to working.
- Added technical notes.
Systems promoted to working
---------------------------
Draw Poker HI-LO (M.Kramer) [Roberto Fresca, Grull Osgo]
HI-LO Double Up Joker Poker [Roberto Fresca, Grull Osgo]
Draw Poker HI-LO (Japanese) [Roberto Fresca, Grull Osgo]
- igs/spoker.cpp: fixed bitplane order in jinhulu2's decode. Fixes colors [David Haywood]
New working clones
------------------
Xingyun Man Guan (China, V651C, set 2) [little0]
New systems marked not working
------------------------------
Chaoji Daheng 6th (v100FI) [little0]
Chao Ji Laizi Dou Dizhu (V109CN) [little0]
New clones marked not working
-----------------------------
Jin Hu Lu 2 (v101IS) [little0]
-cpu/drcbearm64.cpp: Don't emit code for UML NOP - the simplifier
litters the code with these for elided operations.
-frontend/mame/clifront.cpp: Added newline at end of -version output.
- Consolidate driver in one file.
- New palette for drhl and drhla.
- Added new test functions for drhl, drhla, dphl, and dphla.
- Cleaned all the conditional unused things.
- Rewrote inputs for different sets.
- DIP switches improvements for norautp, norautrh,
- New inputs for norautua, dphla, drhl, ssjkrpkr.
- New portmap for dphl, dphla.
- Added Interrupts through vertical sync for all sets based on i8080.
- Fixed norautua and norautub table for bin to bcd conversion.
- New button-lamps layout with 10 buttons for dphl, dphla, dphljp,
drhl, drhla, and ssjkrpkr.
- Clickable buttons for all former buttons-lamps layouts.
- Promoted drhl, drhla, norautua, norautub, and ssjkrpkr to working.
Systems promoted to working
---------------------------
Drews Revenge (v.2.89, set 1) [Roberto Fresca, Grull Osgo]
Noraut Joker Poker (console, set 1) [Roberto Fresca, Grull Osgo]
Southern Systems Joker Poker [Roberto Fresca, Grull Osgo]
Clones promoted to working
--------------------------
Drews Revenge (v.2.89, set 2) [Roberto Fresca, Grull Osgo]
Noraut Joker Poker (console, set 2) [Roberto Fresca, Grull Osgo]
* scripts/minimaws: Set option strict for JavaScript code.
* util/mfpresolve.h: Be explicit about turning nullptr into a pointer to
data.
* cpu/drcbearm64.cpp: Reduced number of temporary registers used for AND
with some operand combinations.
Track the state of the native carry flag to avoid unnecessarily
manipulating the native NZCV register. If the native carry flag does
not correspond to the UML carry flag, test the bit in the flags register
for the C and NC conditions.
Use condition select instructions to implement conditional forms of MOV
and FMOV when advantageous.
Fixed EXIT with C/NC/A/BE condition not working properly if it doesn't
immediately follow a CMP or SUB. Extended reach of conditional EXIT to
+/-128MiB (was +/-1MiB for conditions other than U/NU).
Moved code to set up skipping conditional instructions to a common
function.
Use TBZ/TBNZ for short backward jumps with U/NU/C/NC conditions to save
one instruction and a temporary register.
Simplified/optimised ADD[C]/SUB[B] code generation - avoids an
unnecessary register copy when one operand is in memory and the other is
a small immediate value. Also fixed another unnecessary register copy
for SUB[B] when an operand is kept in a host register.
Slightly optimised generated code for AND immediate.
Clear V/Z/S bits in flags register after SETFLGS or RESTORE. These
flags are kept in the native NZCV register, and SAVE assumes the
corresponding bits in the flags register are clear.
Don't use an extra temporary register for SETFMOD with operand loaded
from memory. It doesn't allow additional parallelism anyway.
Slightly optimised generated code for GETFLGS.
Avoid a redundant TST when flags are requested for the non-optimised
ROLAND case. Also avoid unnecessarily updating flags when not
requested.
Don't update flags for ADD/ADDC/SUB/SUBB/AND if not requested. Slightly
reduces pressure on the NZCV register.
Added TODO notes for opportunities to use CSEL/FCSEL rather than
conditional branches.
* Fixed potential crash on generating code for UML ADDC or SUBB with immediate operands (GitHub #13475).
* Optimised generated code for various degenerate cases and cases where register loads can be avoided.
