* spg110: jak_capb misc guesses (nw)
* misc priority stuff (nw)
* tweaks (nw)
* more tweaks (nw)
* small spg2xx refactor (nw)
* some spg2xx refactoring (nw)
* (nw)
* tidy (nw)
* these have all been moved out into modules (nw)
* sprite work in progress (nw)
* (nw)
* spg110: shift some stuff around and split into files here too
* (nw)
* (nw)
* (nw)
* sprite improvements
(Epoxy brick CPU) to Joker Card / Multi Card (Epoxy brick CPU).
Added documentation and hardware notes about the behaviour and
how the scheme works. Added a default NVRAM. [Roberto Fresca, Grull Osgo]
Added PLDs to pool10e set. [unknown...]
* Hook up the two 6821 PIAs
* Clean up inputs, add dipswitch locations, label some switches
* Add output ports and hook up coin counter and lamps
* Add simple layout showing the five buttons (clickable artwork)
(nw) After this change, the keyboard sends scan codes to the host successfully, but fails to receive/process commands from the host. Failure is probably due to differences between the 6805U3 that's really in the keyboard, and the 68705U3 that's the best match in mame at the moment, so requires expanded 6805 emulation.
This effectively reverts b380514764 and
c24473ddff, restoring the state at
598cd52272.
Before pushing, please check that what you're about to push is sane.
Check your local commit log and ensure there isn't anything out-of-place
before pushing to mainline. When things like this happen, it wastes
everyone's time. I really don't need this in a week when real work™ is
busting my balls and I'm behind where I want to be with preparing for
MAME release.
- added MOSFET model. Currently capacitances are not modelled.
This is a 3-pin model (Bulk connected to Source) with provisions to
extend it to 4-pin at a later stage.
- Add a capacitor generic model which is charge conserving.
Switch netlist to use this model instead of constant capacity model.
- Start putting constants into a central place.
Please expect minor timing differences due to a different numerical
path.
The cmos inverter example illustrates the analog implementation of a
cmos inverter gate. These were used a lot back in the 70s/80s to
generate sinus waves. The model should also be able to better emulate
4066 analog switches.
The addition of a relatively simple capacitor model is planned at a
later stage.
Expect everything from the MOSFET model at the current stage. Wrong
results as well as convergence issues and crashes.
