Added ability to test the instruction/data cache ram. The scratchpad and BIU register are now handled internally to the CPU.
All writes are performed with masks. SWL/SWR used to be implemented with two writes ( one byte and one word ) when writing three bytes, now it only ever performs one. Byte and Word writes use masks as they leave the rest of the register on the bus, which can be picked up by larger registers.
The read/write functions to use are cached when the SR bits are updated, as are the bad address masks.
Added coprocessor 1 & 3 support, though they don't do anything useful.
All loads now go through the delay pipeline, a lwl/lwr will grab the value out of the pipeline if it's updating the same register.
Added undocumented behaviour of BLEZ/BGTZ. The comparison for zero can be changed by specifying an alternate register in the RT field ( the documentation says you should always use register 0 ).
Restricted to 16 COP0 registers & generate an exception if any of the 5 for the MMU are used.
Added BCF/BCT instructions, although I have found no conditions that affect them yet.
Generates an exception if any MMU instructions are executed.
Sets the CE instruction for all exceptions, not just those involving a coprocessor. The bits of the opcode that specify the coprocessor are grabbed no matter what the instruction.
Added TAR register and BT bit in SR. When an exception occurs during a branch, BT determines whether it was taken or not. The TAR register gets set to the destination of the branch.
Fixed the BD bit when you are in a branch delay slot and you didn't take the branch, this shows up in the pipeline as !pc.
Fixed branches within a branch delay slot.
Multiply & divide instructions can be aborted if you write to HI/LO before reading the result.
Added data breakpoints, you don't appear to be able to set breakpoints on any of the addresses internal to the CPU.
Multiply/divide/GTE instructions can execute when an exception is taken, although the EPC indicates that it hasn't. The BIOS avoids rerunning GTE instructions as they are destructive, so you have to make sure they run.
Added bus error handling, PSXCPU is limited to 8mb of ram & any access outside this range will trigger an exception. I believe this is to be an internal limit.
Added CXD8611R as a specific CPU type, System 12 appears to allow more than 8mb of ram & it's possible that this is different.
Mapped out all instructions to either generate an exception or ignore bits.
Updated the disassembler to match the decoding.
Fixed disassembling of branch instructions in a branch delay slot.
Lui checks for a ori/addiu following and will show you the result.
Added step over/out support.
Fixed standalone disassembler.
Subject: patch for SVP (Sega Virtua Processor) emulation
hello,
this patch adds support for Sega Virtua Processor, to run
Genesis/MegaDrive version of Virtua Racing, intended to be used by
MESS. It consists of a CPU core SSP1601, and updates in megadriv.c:
* SSP1601 replaces SSP1610, as it has been confirmed by Stiletto and
other sources that SVP actually contains SSP1601. The current SSP1610
is placeholder only (nearly completely unimplemented) anyway.
* Changes in megadriv.c add a new driver for Genesis/MegaDrive+SVP
combination, also add SVP memory controller logic and memory map.
The diff has already been reviewed by Reip and SSP1610 removal was one
of his suggestions (SSP1610 is not used by any drivers).
Converted address maps to tokens. Changed the address_map structure
to house global map-wide information and hung a list of entries off
of it corresponding to each address range. Introduced new functions
address_map_alloc() and address_map_free() to build/destroy these
structures. Updated all code as necessary.
Fixed several instances of porttagtohandler*() in the address maps.
Drivers should use AM_READ_PORT() macros instead.
ADDRESS_MAP_EXTERN() now is required to specify the number of
databits, just like ADDRESS_MAP_START.
Removed ADDRESS_MAP_FLAGS() grossness. There are now three new macros
which replace its former usage. ADDRESS_MAP_GLOBAL_MASK(mask)
specifies a global address-space-wide mask on all addresses. Useful
for cases where one or more address lines simply are not used at
all. And ADDRESS_MAP_UNMAP_LOW/HIGH specifies the behavior of
unmapped reads (do they come back as 0 or ~0).
Changed internal memory mapping behavior to keep only a single
address map and store the byte-adjusted values next in the address
map entries rather than maintaining two separate maps. Many other
small internal changes/cleanups.
- Define a new MDRV_CPU_VBLANK_INT_HACK() (ZV: defined in deprecat.h) which is a copy of the current MDRV_CPU_VBLANK_INT()
- Find all the places where VBLANK_INT is used with something other than 1 interrupt per frame and change it to the new macro
- Remove the "# per frame" parameter from the MDRV_SCREEN_VBLANK_INT() and add a screen tag in its place; updated all callers appropriately.
- ZV: Added some validation of the interrupt setup to validate.c
The idea behind this is that using a VBLANK interrupt with more than one interrupt per frame in conceptually wrong.
The screen tag will allow us to move the interrupt timing code from cpuexec.c to video.c, where it really belongs.
Subject: uPD7801, uPD78C05, and uPD78C06 cpu cores added to the uPD7810
cpu core
This patch adds basic support for the NEC uPD7801, uPD78C05, and
uPD78C06 cpus to the uPD7810 cpu core.
Hi mamedev,
Here's my periodic batch of code cleanups. The usual batch of adding static/const plus some include fixes. In addition, I reverted some of the changes to build.mak from u1 which made some MSVC builds fail, and adjusted/optimized an m10.c gfx_layout. I also added some missing cores to cpuintrf.c, sndintrf.c and added some missing #if's to 5220intf.c.
~aa
- Added some instructions to the H8/30xx CPU:
or.l ERs, ERd
rotl/shal.l ERd
not.l/neg.l ERd
exts.w Rd
sub/or/xor.l #Imm:32, ERd
bset/bnot/bclr.b Rn, @ERd
bst/bist.b #Imm:3, @ERd
bnot.b #Imm:3, @ERd
- Added H8/3007 & H8/3044 variants with their memory maps.
Preliminary implementation of the H8/3007 timers.
(a make clean is required)
P.S.
I've moved the docs we have in docs/cpu/H8-30xx and added a couple more.
Roms are in roms/current/p/puzzlet.zip
Added #include "deprecat.h" where necessary to make this happen.
Cleaned up cpuexec.c/.h to latest core style.
Cleaned up implementation of extended INP header in inptport.c.
Removed external access to cycles_currently_ran().
Replaced use of cycles_currently_ran() in v9938 code with mame_rand(), since that is effectively the same thing. :)
The idea is to create extra work if a driver wants to use these and hopefully
gives an incentive to look for an alternate solution
- Added #include of deprecat.h that rely on these contructs
- Removed a bunch of unneccassary #include's from these files
Cleaned up jaguar driver:
* proper video timing, configured by the chipset
* 32-bit rendering, removing 16bpp hacks
* support for borders
* proper object processor timing, including multiple passes per line
* added R3041 as a clone of the R3000
* fixed XTALs based on documentation
* fixed movd instructions
* add MB8884 and M58715 cpu types
* moved timer hack to M58715
* added ram_mask for internal ram access
* added R.A11 as 'M' to dasm flags
* added EA "IO" port
* mario now uses M58715 as sound cpu
Here's a patch that fixes compile errors when compiling a C++ source file including "render.h"
and "palette.h". C++ (at least g++) does not like typedef's for an enum coming before the actual enum.
- removed years from copyright notices
- removed redundant (c) from copyright notices
- updated "the MAME Team" to be "Nicola Salmoria and the MAME Team"
