Current document says it's unknown where are the background images
stored. But it should be in the TRJ-100 custom package, that needs a
custom adapter to dump it.
Also add a side note that the TRJ-100 chip generates 5MHz clock for
some unknown reasons, and used by some ICs as a clock. This may help
to solve the speed problems in the future.
* spectrum list work (nw)
* list cleanups (nw)
* spectrum list cleanups (nw)
* spectrum list cleanups (nw)
* spectrum list work (nw)
* spectrum list work (nw)
* spectrum list work (nw)
* list work (nw)
* spectrum list work (nw)
* list work (nw)
* spectrum list work (nw)
* spectrum list work (nw)
* list work (nw)
Add support for the SS-30 bus. The DC5 FDC, MPS2, PIA-IDE and MPT have been
added to the SS-30 bus and are split out.
A separate floppy format has been added for UniFLEX, and the FLEX format has
been improved. These formats should be usable now, and have been lightly
tested.
The banked memory was not implemented correctly and has been updated.
The DMAF2 and DMAF3 FDCs are still implemented in the swtpc09 device, but have
been updated. These belong on the SS-50 bus, but there is no SS-50 bus yet -
still on the TODO list.
The PIA IDE has been implemented on the SS-30 bus, and updated to get it
working, and the swtpc09i machine is promoted to working. Have been able to
boot this from a FLEX hard disk image, and it also boots FLEX using the DC5
FDC.
Tested swtpc09 running FLEX with DMAF2 support. Tested swtpc09d3 running
UniFLEX and it seems to run well. The hard disk support is still TODO, but
added a reference to the WD1000 documentation. Did not have a UniFLEX image on
hand to test the swtpc09u, but have tested the DMAF2 under FLEX and UniFLEX
using DMAF3 so it's probably ok or close. Had no documentation for the DMAF3.
Bit 7 of the control register inhibits all drive select lines when high and
this is now implemented. This was a long standing feature in this line of
floppy disk controller boards. The drives are also inhibited when the motor
timer has timed out. It is not just their motors that are off.
Add a conf option to interpret bit 7 of the control register as an 'erroneous'
side select, and log such usage. Some drivers use bit 7 for side selection and
this option help work around them and adapt them.
Add support to set the clock rate using the DC5 extended control register, and
update the associated code. The clock rate config option is now only an
'expected' rate and may be null.
Clarify that the motor timer is only triggered by access to the FDC registers
and not by access to the control registers. There appears to be a common error
in drivers, they access the control register and then wait a period, and it
appears they wait for the motor to spin up, but that can not happen. The
problem appears to be documented, flaky disk booting, having to reset and try
again and again. It seems best to deal with that in boot and driver software
rather than an emulator hack.
The motors are on, or off, irrespective of drive selection.
Rewrite the updating of the floppy and FDC state based on the control register
and the motor timer out, so that the latched control register state is
respected when the motor timer output changes - it had been just turning the
motors on or off but the drive selection also needs to be updated.
Reset the DDEN input, setting it for single density, upon device reset.
Default DC5 to 16 byte address mode to suit the SWTPC 6809 - the SWTPC 6800
overrides this default for it's 4 byte address mode.
Indentation fixes.
* ss-30 mps: default to 9600 baud
* SWTPC - add floppy disk support
Include the DC5 floppy disk controller on the expected SS-30 I/O positions of
ports 5 and 6.
Add a config option to select the CPU clock rate. Higher FDC clock rates need
higher CPU rates to download the data fast enough without DMA.
A couple of SWTBUG ROM patch config options are added to make disk
booting more practical.
Narrow the address range block used for the motherboard I/O to 0x8000 to
0x8fff, and also narrow the mirroring to potentially support two mother boards
with twice as many I/O cards. Add documentation to explain these changes.
Make 32K the default lower RAM size.
Implement RAM from 0xa000 to 0xdfff, as FLEX needs much of that.
Document the path to supporting Low and High PROMS.
Emit a 9600 baud rate clock on the 150/9600 line. This was a practical rate at
the time and screen based software is not practical at the prior rate of 1200
baud. This was a document option.
The emulator now runs FLEX 2 on a range of disk formats. Disk driver software
support is still an issue, another monitor PROM might be needed, there might
be an issue with the FDC 'ready' input, but this is a big step forward.
Bit 7 of the control register inhibits all drive select lines when high and
this is now implemented. This was a long standing feature in this line of
floppy disk controller boards. The drives are also inhibited when the motor
timer has timed out. It is not just their motors that are off.
Add a conf option to interpret bit 7 of the control register as an 'erroneous'
side select, and log such usage. Some drivers use bit 7 for side selection and
this option help work around them and adapt them.
Add support to set the clock rate using the DC5 extended control register, and
update the associated code. The clock rate config option is now only an
'expected' rate and may be null.
Clarify that the motor timer is only triggered by access to the FDC registers
and not by access to the control registers. There appears to be a common error
in drivers, they access the control register and then wait a period, and it
appears they wait for the motor to spin up, but that can not happen. The
problem appears to be documented, flaky disk booting, having to reset and try
again and again. It seems best to deal with that in boot and driver software
rather than an emulator hack.
The motors are on, or off, irrespective of drive selection.
Rewrite the updating of the floppy and FDC state based on the control register
and the motor timer out, so that the latched control register state is
respected when the motor timer output changes - it had been just turning the
motors on or off but the drive selection also needs to be updated.
Reset the DDEN input, setting it for single density, upon device reset.
Default DC5 to 16 byte address mode to suit the SWTPC 6809 - the SWTPC 6800
overrides this default for it's 4 byte address mode.
Indentation fixes.
