MAME_INCLUDES_<FILENAME>_H is now the standardized way for a MAME include header, starting with a double underscore is reserved by the C++ standard go figure (nw)
- Make read_byte/word and write_byte/word overridable virtual functions (80186 MMU probably will need to override this in the future)
- Make fetch_op an alias for fetch (implementations were identical already)
- Remove sreg argument from read_byte/word and write_byte/word (it was almost always m_easeg as set by calc_addr, sometimes with dubious evaluation order)
- Restrict logic for separating address spaces for CS/ES/SS accesses to 8086/8088 (later x86 models do not broadcast the descriptors)
- Encapsulate m_e16 within the only function that used it
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Soreyuke Anpanman Crayon Kids [ShouTime, Bill D, Surgeville, Sean Sutton, George Walsh, Evan Korzon, Dulleron, SpinalFeyd, Gyrovision, Bryce Van Horn, Paul Vining, Charles MacDonald, Smitdogg, The Dumping Union]
- Make the global flipping functions of driver_device protected so as not to be accessible from within subdevices
- Eliminate the flip_screen_set_no_update kludge
* new NOT WORKING
Zone 40 [BeckyRGB]
Wireless Air 60 [BeckyRGB]
it isn't 100% clear these belong here, but it's also possible they do, so until more is known, put them here.
* various leapster.xml software list additions [Team Europe]
(also added some missing 'supported="no"'' lines)
* add some extra Leapster bios sets [Sean Riddle]
* create derived 6502 type for XaviX because it has at least one custom 4-byte opcode that doesn't fit any other type.
treating that opcode as NOP for now.
have a feeling it might be something to do with the other integrated hardware, might be 'execute co-processor code chain at this address' or something similar
It isn't a standard JSL (Jump Subroutine Long) like the SNES cpu opcode in the same place as this, it seems to point at some code-like structures tho)
could also be a secondary operation mode with different encoding like ARM's Thumb mode tho I guess.
We currently only have a single XaviX based dump (taitons1) but there are more on the way. I'm going to see if the code flow makes any sense at all with these missing, or if any of it gives a clue as to what they should actually do.
* xavix - let's call these callf and retf then
after further investigation these are some kind of extra 'long jump' subroutine / task handlers, the 0x80 also being a custom opcode was throwing me off trying to identify them before.
looks like they might have been hacking 65816 features into the regular 6502 core?
* prepare for extra address bits (nw)
* better program flow (nw)
