* Made it a bit easier to cross-compile for x86-64 or i686 on an AArch64
Windows system.
* Choose the default native recompiler back-end based on predefined
macros rather than requiring the build scripts to set it.
* Don't require every target without a native recompiler to declare
this.
* Got rid of the code that was supposed to set -m32 or -m64 when
building GENie (it didn't work - it tried to use ARCHITECTURE before
setting it).
* Avoid relying on the unreliable PROCESSOR_ARCHITECTURE environment
variable.
* Got rid of stuff for versions of Xcode that are definitely no longer
supported.
* Got rid of workarounds for very old Linux distros.
* Use newer makefile syntax for if/else/if structures, comment some else
and endif statements for clarity.
- New machine driver for Lucky Bar.
- Added special NVRAM for Lucky Bar.
- Simulated the Lucky Bar MCU.
- Fixed animalhsb and animalhsc graphics.
- Added workaround and various fixes.
- Fixed Lucky Bar reels, backgroung, and mask colors.
- Hooked the Lucky Bar MCU, and added a workaround about.
- Added callbacks and handlers to the Lucky Bar MCU
for future full support.
- First step of cleanning up the driver.
Systems promoted to working
---------------------------
Lucky Bar (W-4 with mc68705 MCU) [Roberto Fresca, Grull Osgo]
Clones promoted to working
--------------------------
Animal House (set 2) [Roberto Fresca, Grull Osgo]
Animal House (set 3) [Roberto Fresca, Grull Osgo]
Attempt to enable SSE features explicitly specified in ARCHOPTS. It
will still fall back to SSE 2 if you just use -march= to enable later
SSE features.
* Change hexadecimal prefix from $ to 0x ($ means something else in MIPS assembler syntax) and omit for small numbers
* mips1, mips3, psx: Use shorthand mnemonics bal, beqz(l), bnez(l), li, move, neg, negu, not where applicable
* mips1, mips3, psx: Add delay slot to jr ra for stepping out
* mips1, mips3: Remove invalid instructions from other MIPS cores and use .word syntax for invalid instructions
* mips3: Fix field spacing for some instructions
This was changed in 822c3b4232 but it
never worked for multiple reasons:
* The comment mentions saving around CALLC, but there is no code to save
and restore around CALLC, DEBUG and RECOVER, all of which can clobber
callee-saved registers.
* Numerous opcode handlers assume XMM0 and XMM1 can be used as scratch
registers, but this change mapped them to UML F0 and F1. This
resulted in F0 and F1 getting clobbered by many UML instructions.
* Fixed master volume control.
* Fixed output range.
* Fixed sweep, wave RAM corruption and GBA read/write emulation.
* Use integer bit fields for pulse duty cycle tables.
* Reduced duplication made some variables const, improved member names.
* machine/msm6200.cpp: Scan matrix on a timer until a change is detected.
* sound/upd934g.cpp: Fixed play sample command.
* casio/cz1.cpp: Added MSM6200 clock input frequency.
New systems marked not working
---------------
Casio CPS-2000 [BCM, Devin Acker]
ROLAND could clobber source registers or produce incorrect results if
the desination was the same UML register as the shift or mask.
Fixed a bug in the logic for deciding whether to use a temporary
register for the mask for ROLINS.
Also optimised ROLAND and ROLINS some more (particularly translation
from UML's left rotate to ARM's right rotate) and removed a special case
that the simplifier now takes care of.
* Elfin will eventually get into a state where it ignores coins.
Protection is conceptually similar to The X-Files.
-cpu/uml.cpp, cpu/drcuml.cpp: Made it possible to build with logging
simplifications enabled (in uml.cpp it logs each step, in drcuml.cpp it
logs the net change). It will produce absoluely massive logs, though.
-cpu/drcuml.cpp: Removed woefully inadequate and badly rotted "backend
validation" code.
- Turbo Poker II palette decoded from bipolar PROMs.
- Adjusted the Poker Plus palette to 256 entries.
- Dedicated Turbo Poker II memory map and machine config.
* cpu/drcbearm64.cpp: Optimised setting up carry flag for ADDC and SUBB.
There's no need to preserve the NZV flags so a two-instruction
sequence can be used.
* cpu/drcbex64.cpp: Simplified code generation for CARRY. I have no
idea why it was preserving RAX at all - it always uses RAX as a
scratch register.
