* Illustrates how to keep existing memory read/write handlers
This is slower than caching the device interface, but does not have an impact on
devices accessed at a low frequency like in this case.
* added ATTR_FORCE_INLINE to osdcomm.h
* added ATTR_NONNULL
* moved U64 S64 fram mamecore.h to osdcomm.h
* define SETJMP_GNUC_PROTECT() in osdcomm.h for use in ppc602, ppc603
- Added a video_screen_register_vbl_cb() function for registering VBLANK callbanks
- Changed inptport.c and debugcpu.c to make use the VBLANK callbacks
- Added video_screen_get_time_until_vblank_start()
- CCPU and anything using cpu_scalebyfcount() are currently broken
- I did some fairly extensive testing, but this is a very signficant internal change,
so some things may have broke
to use the macros.
Added the concept of device classes. Devices specify their class
in their get_info function. Classes can be used to walk through
devices at a more general level than their type. Functions have
been added to iterate through devices by class just as you can
by type.
Removed some unused fields from device_config.
- Since the Commodore 40xx computers program an HSYNC width that extends past the end of
the scanline, I am clamping it in lack of anything better to do.
- Define a new MDRV_CPU_VBLANK_INT_HACK() (ZV: defined in deprecat.h) which is a copy of the current MDRV_CPU_VBLANK_INT()
- Find all the places where VBLANK_INT is used with something other than 1 interrupt per frame and change it to the new macro
- Remove the "# per frame" parameter from the MDRV_SCREEN_VBLANK_INT() and add a screen tag in its place; updated all callers appropriately.
- ZV: Added some validation of the interrupt setup to validate.c
The idea behind this is that using a VBLANK interrupt with more than one interrupt per frame in conceptually wrong.
The screen tag will allow us to move the interrupt timing code from cpuexec.c to video.c, where it really belongs.
Subject: A fix for the z80pio
Hi there,
Here is a one-line fix for the z80pio.
At the moment when the interrupt control word is sent (with interrupts
enabled), an interrupt occurs. In reality, interrupts are disabled until
the interrupt mask byte is sent.
Subject: MPU4 Changes part 2
Right, I've added a bit of CTS pin checking logic, so that the status
flag is actually set when the pin changes state.
I've also simplified the MPU4 ACIA clock logic, but it's still not ideal
(Ideally, the ACIA should only run one transmit or receive event each
time the PTM O1 pin goes high, but that's not possible right now, so I
just set the clocks as close to off as I can when the pin is low, and to
something that approximates the distance between output state changes
when it's on). There's also a few more little cleanups based on
schematics and flyers from TAFA, and an emulation of the master reset
behaviour. Incidentally, if anyone wants to see just why this isn't
kicking into life now, by all means do, since there's nothing left that
I can see that it can get hung up on, other than the video chip, and the
aforementioned ACIA logic.
Subject: uPD7801, uPD78C05, and uPD78C06 cpu cores added to the uPD7810
cpu core
This patch adds basic support for the NEC uPD7801, uPD78C05, and
uPD78C06 cpus to the uPD7810 cpu core.
